Nvidia Jetson AGX Xavier Series Guide

DG-09840-001_v2.5 | December 2021
Jetson AGX Xavier Series Product
Design Guide

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | ii
Document History
DG-09840-001_v2.5
Version Date Description of Change
August 29, 2018 Initial Release
November 15, 2018 Pin Description Table
•Updated pin types for UPHY[9:8] in full pin descriptions
table
General
•Updated module name to Jetson AGX Xavier
Overview
•Updated Jetson AGX Xavier Interfaces table PCIe and
I2S functions
•Updated # of UARTs to 5
Main Connector Details
•Added text and figure for standoff requirements
•Added 2.5mm height connector option for carrier board
Power
•Updated Power and System Pin Desc. table (and full
table]
•Updated Usage columns
•Updated pin type column
•Corrected title of Table 8
•Added SYS_VIN_HV Input and simplified DC Jack figure
•Added note for MCU based power button supervisor
designs
•Added non-MCU based power-on circuit description
•Updated Power Discharge to match latest reference
design
USB
•Updated Simple USB Type A Connection Example figure
•Added note under USB type C example that designs
related to microcode.
•Removed level shifter on USB Micro ID signal and
added note
PCIe
•Updated PCIe figure and table Root Port and added
PEX_L5 control.
•Updated PCIe RST pull-up value figure/table and
checklist.

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | iii
Version Date Description of Change
•Added PCIe Endpoint Connection figure and table
•Updated PCIe Intra-pair skew length
•Updated range and value for PCIe AC cap for GEN3.
Video Input
•Updated Misc. Pin Descriptions table for
UART4_TX/CTS
Audio
•Corrected I2S1/DAP1 signals descriptions
UART
•Added UART7 option on module SPI2 pins
Debug
•Added simple debug UART connection section
Strapping
•Added notes for to pull-up resistors on RAM_CODE
straps.
Design Checklist
•Added pull-up on OVERTEMP_N
•Updated terminations for GPIO30
•Added power jack option to Carrier Board Supplies
section
•Removed AC caps for UFS
•Updated pin types for UPHY[9:8]
February 20, 2019 Power
•SYS_VIN_HV Input: Updated note on Type C PD support
•Updated Simplified Button Power-on Circuitry figure
•Power Button Supervisor: Updated note related
firmware
USB
•Updated note related to Type C firmware
•Updated USB Type C figure and notes for test points.
•Updated USB Type A Connection figure
•Updated USB Micro AB Connection figure
PCIe
•Updated PEX_WAKE_N usage in Pin Description tables
•Corrected connection figures for for
NVHS0_SLVS_REFCLK
UFS
•Updated figure module pin #s/names for UFS CLK/RST.
MIPI CSI

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | iv
Version Date Description of Change
•Updated with relaxed skews based on frequency
(0.4*UI)
I2C
•Updated figure module pin #s for I2C3
Boundary Scan
•Updated Boundary Scan figure module pin #s
Pin Descriptions
•Corrected I2S1 pin #s, description and direction.
2.0 May 12, 2020 Main 699-pin Connector Details
•Added Module Installation and Removal Section
Video Input
•Added SLVS XCE and SCLR signals to Pin Desc.
•Added pin tolerance were applicable
•Updated control signal direction to match SLVS usage
•Update SLVS connection figure:
•Corrected XCE and XCLR connections and changed to
generic name for SLVS imager/connector in figure
•Added SLVS connections tables
I2C and Design Checklist (I2C section)
•Added note for series resistors on I2C for M.2 sockets
2.1 July 27, 2020 •Update Table 2-1 to C5 only supports EP
•Added Chapter 4 on reference design considerations
•Added DV/Dt section (Section 5.5.1) including optional disable
or tuning
•Added optional additional diode to DV/dt circuit to allow more
drop before triggering system shutdown (asserting
VDDIN_PWR_BAD_N) in Figure 5-12
•Added descriptions per lane for data lane pin descriptions
table (Table 7-2)
•Added more details to the “Usage/Description” column in
Table 7-3
•Updated to reflect RP only and added details for EP usage to
the PCIe clock and control pin descriptions table (Table 7-4)
•Updated Section 7.2 “PCI Express” for C5 only as EP
•Updated Figure 7-4 for C5 only as EP
•Removed C0 and C4 as EP in Figure 7-5
•Added UPHY_REFCLK1/2_N/P pins but indicated it is unused
as EP not supported on C0 and C4 in Table 7-14
•Added NVHS0_SLVS_REFCLK_N/P pin to Table 7-14
•Removed C0 and C4 from Table 7-15 as these are no longer
supported as Eps

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | v
Version Date Description of Change
•Added NVHS0_SLVS_REFCLK_N/P and PEX_WAKE_No pins
to Table 7-15
•Added load switch on 3.3V to eDP/DP connector in Figure 9-1
•Updated Figure 9-3 to show load switch providing 5V to the
connector and added related note
•Removed mention of debug and added note in Table 13-10
•Removed mention of debug connector and changed UART2
connection on CB to UART USB bridge in Figure 13-7
•Added Section 15.1 “USB Recovery Mode”
•Removed UART2 as debug UART and removed related note
in Figure 15-1
•Replaced example showing UART2 with one showing UART3
instead and removed note in Figure 15-2
•Removed mention of UART2 in Section 15.2.2 and the table
listed in the section
•Added bring-up checklist to the attachments and listed in
Chapter 18
2.2 November 18, 2020 •Added notes to Figure 5-3, Figure 5-4, and Figure 7-3
•Added note to clarify PCIe clock output and RFCLK input
signaling type to Figure 7-4
•Added insertion loss S-parameter plot figure (Figure 7-6)
•Updated Table 10-5 based on new guidelines from IOSI
based on improved model
2.3 January 28, 2021 •Updated to include Jetson AGX Xavier Industrial (JAXi)
•Updated pin description attachment
2.4 June 8, 2021 •Attachment: Updated pin description Excel file
•Module spacing: Updated Section 3.3: Module to Carrier
Board Standoff Height Recommendations
Updated mating connector spacing tolerance and column
titles/spacing numbers in Table 3-1 and Table 3-2
•Updated STANDBY_ACK_N description in Table 5-1: Power,
System, and Thermal Pin Descriptions.
•PCIE: Table 7-4: PCIe Clock and Control Pin Descriptions;
updated CLKREQ, RST and WAKE pin descriptions.
•USB: Updated Figure 7-1: Simple USB Type A Connection
Example.
•I2S: Updated Table 12-1: Jetson AGX Xavier Audio Pin
Description to indicate I2S6 (DAP6 on SoC) is not supported
for JAXi.
2.5 December 2, 2021 •Corrected Table 2-2 (Pinout Matrix) to have GPIO12 (pin E10)
called out for Safety MCU usage

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | vi
Version Date Description of Change
•Removed MPIO Pad Code and Power-on Reset columns
from Pin Desc. tables throughout document (these are
included in the attached full pin desc. spreadsheet).
•Added more power handshake signal details before Power
On and Power Off Sequencing sections.
•Updated power sequencing figures.
•Updated USB Micro AB connection to connect ID pin to
generic GPIO and added related note
•Added note under USB Micro AGB connection
recommending load switch with current protection be used
•Updated pin description types for 3.3V tolerant pins (PCIe
control)
•Added CSI CPHY 3-Trio options. Updated Note 1 under pin
description table.
•Updated Audio pin descriptions Usage/Descriptions and
Usage on carrier board for DAP6
•Corrected SoC pin name for GPIO05 for JAXi.
•Updated USB Recovery Mode section to include minimum
requirements for entering recovery mode.
•Updated title of AN for Boundary scan in Debug and
Strapping sections.

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | vii
Table of Contents
Chapter 1. Introduction...........................................................................................1
1.1 References.......................................................................................................................... 1
1.2 Abbreviations and Definitions............................................................................................ 1
Chapter 2. Jetson AGX Xavier .................................................................................3
Chapter 3. Main Connector Details.........................................................................8
3.1 Connector Pin Orientations ............................................................................................... 9
3.2 Module to Carrier Board Spacing Details....................................................................... 10
3.3 Module to Carrier Board Standoff Height Recommendations ...................................... 11
3.4 Module Installation and Removal.................................................................................... 12
Chapter 4. Reference Design Considerations.......................................................14
Chapter 5. Power ..................................................................................................16
5.1 Supply Allocation.............................................................................................................. 18
5.2 Power Sequencing............................................................................................................ 19
5.3 SYS_VIN_HV Input ............................................................................................................ 22
5.4 Power-On.......................................................................................................................... 22
5.4.1 Power-On No MCU..................................................................................................... 22
5.4.1.1 Auto Power-On Option No MCU ......................................................................... 23
5.4.2 Power Button Supervisor MCU Power-On ............................................................... 24
5.4.2.1 Defined behaviors ............................................................................................... 25
5.4.2.2 Power OFF -> Power ON (Power Button Case) ................................................. 25
5.4.2.3 Power OFF -> Power ON (Auto-Power-On Case).............................................. 26
5.4.2.4 Power ON -> Power OFF (Power Button Held Low > 10 Seconds)................... 27
5.5 Power Discharge .............................................................................................................. 28
5.5.1 DV/Dt Circuit Considerations .................................................................................... 28
5.6 Power and Voltage Monitoring ........................................................................................ 30
5.6.1 Power Loss Detection................................................................................................ 30
5.6.2 Power Monitor............................................................................................................ 31
5.7 Deep Sleep or SC7............................................................................................................ 32
Chapter 6. General Routing Guidelines ................................................................34
6.1 Signal Name Conventions................................................................................................ 34
6.2 Routing Guideline Format................................................................................................ 35
6.3 Signal Routing Conventions............................................................................................. 35
6.4 Routing Guidelines ........................................................................................................... 35
6.5 General PCB Routing Guidelines .................................................................................... 36
Chapter 7. USB, PCIe, and UFS ............................................................................37

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | viii
7.1 USB ................................................................................................................................... 41
7.1.1 USB 2.0 Design Guidelines........................................................................................ 43
7.1.2 USB 3.1 Design Guidelines........................................................................................ 43
7.1.3 Common USB Routing Guidelines ............................................................................ 46
7.2 PCI Express ...................................................................................................................... 47
7.2.1 PCIe Design Guidelines up to Gen3 .......................................................................... 50
7.2.2 PCIe Gen4 Design Guidelines.................................................................................... 53
7.3 UFS.................................................................................................................................... 57
7.3.1 UFS Design Guidelines .............................................................................................. 57
Chapter 8. Gigabit Ethernet ..................................................................................59
Chapter 9. Display.................................................................................................63
9.1 DP and eDP....................................................................................................................... 65
9.1.1 DP and eDP Routing Guidelines................................................................................ 66
9.2 HDMI ................................................................................................................................. 69
Chapter 10. Video Input ..........................................................................................77
10.1 MIPI CSI ............................................................................................................................ 77
10.1.1 CSI D-PHY Design Guidelines ................................................................................... 87
10.1.2 CSI C-PHY Mode Design Guidelines ......................................................................... 88
10.2 SLVS Camera Interface.................................................................................................... 89
10.2.1 SLVS Design Guidelines............................................................................................. 92
Chapter 11. SDIO and SD Card ...............................................................................94
11.1 SD Card............................................................................................................................. 94
Chapter 12. Audio ...................................................................................................98
12.1.1 I2S Design Guidelines .............................................................................................. 101
12.1.2 DMIC Design Guidelines .......................................................................................... 102
Chapter 13. Miscellaneous Interfaces..................................................................103
13.1 I2C ............................................................................................................................... 103
13.1.1 I2C Design Guidelines.............................................................................................. 105
13.1.2 De-bounce ................................................................................................................ 107
13.2 SPI ............................................................................................................................... 107
13.2.1 SPI Design Guidelines.............................................................................................. 108
13.3 UART ............................................................................................................................... 110
13.4 CAN ............................................................................................................................... 112
Chapter 14. Fan ....................................................................................................114
Chapter 15. Debug and Strapping ........................................................................116
15.1 USB Recovery Mode....................................................................................................... 116
15.2 JTAG and Debug UART................................................................................................... 117

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | ix
15.2.1 JTAG.......................................................................................................................... 118
15.2.2 Debug UART ............................................................................................................. 119
15.3 Strapping Pins ................................................................................................................ 119
15.4 Boundary Scan Test Mode ............................................................................................. 120
15.5 Safety MCU JAXi Only..................................................................................................... 121
Chapter 16. Pads ..................................................................................................123
16.1 MPIO Pad Behavior when Associated Power Rail is Enabled...................................... 123
16.2 Schmitt Trigger Usage................................................................................................... 123
16.3 Pins Pulled and Driven During Power-on..................................................................... 123
16.4 Pad Drive Strength ......................................................................................................... 124
Chapter 17. Unused Interface Terminations ........................................................125
17.1 Unused MPIO Interfaces................................................................................................ 125
17.2 Unused SFIO Interface Pins........................................................................................... 125
Chapter 18. Design and Bring-up Checklists .......................................................126
Chapter 19. General Layout Guidelines................................................................127
19.1 Via Guidelines ................................................................................................................. 127
19.1.1 Via Count and Trace Width ...................................................................................... 127
19.1.2 Via Placement .......................................................................................................... 127
19.1.3 Via Placement and Power and Ground Corridors.................................................. 127
19.2 Connecting Vias.............................................................................................................. 129
19.3 Trace Guidelines............................................................................................................. 129
19.3.1 Layer Stack-Up ........................................................................................................ 129
19.3.2 Trace Length ............................................................................................................ 129
Chapter 20. Stack-Ups .........................................................................................130
20.1 Reference Design Stack-ups......................................................................................... 130
20.1.1 Importance of Stack-up Definition.......................................................................... 130
20.1.2 Impact of Stack-up Definition on Design................................................................ 130
Chapter 21. Transmission Line Primer ................................................................131
21.1 Basic Board Level Transmission Line Theory .............................................................. 131
21.1.1 Characteristics......................................................................................................... 131
21.2 Physical Transmission Line Types ................................................................................ 132
21.2.1 Microstrip Transmission Line ................................................................................. 132
21.2.2 Stripline Transmission Line .................................................................................... 132
21.3 Drive Characteristics ..................................................................................................... 133
21.4 Receiver Characteristics................................................................................................ 133
21.5 Transmission Lines and Reference Planes.................................................................. 134
Chapter 22. Design Guideline Glossary ................................................................137

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | x
Chapter 23. USB SS and Wireless Coexistence....................................................139
23.1 Mitigation Techniques.................................................................................................... 139
Chapter 24. Jetson AGX Xavier Pin Description....................................................141

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xi
List of Figures
Figure 2-1. System Block Diagram ..........................................................................................4
Figure 3-1. 699-pin Connector Dimensions.............................................................................8
Figure 3-2. 699-pin Connector Pin Orientations......................................................................9
Figure 3-3. 5.5 mm Height on Carrier Board – Molex Part # 2034560003...........................10
Figure 3-4. 2.5 mm Height on Carrier Board – Molex Part # 2048430001...........................10
Figure 3-5. Module Removal...................................................................................................13
Figure 5-1. Power Block Diagram ..........................................................................................18
Figure 5-2. Power Up Sequence – Power Button Case.........................................................20
Figure 5-3. Power Down Sequence Controlled Case ............................................................21
Figure 5-4. Power Down Sequence Uncontrolled Case ........................................................21
Figure 5-5. Simplified DC Jack Power Connections..............................................................22
Figure 5-6. Simplified Button Power-On Circuitry ................................................................23
Figure 5-7. Optional ACOK Circuitry.......................................................................................24
Figure 5-8. Power-On Button Circuit .....................................................................................25
Figure 5-9. Power-OFF to On Sequence Power Button Case ...............................................26
Figure 5-10. Power-OFF to On Sequence Auto Power-On Case ............................................27
Figure 5-11. Power-On to OFF Power Button Held Low > 10 Seconds ..................................28
Figure 5-12. Power Discharge ..................................................................................................30
Figure 5-13. VIN Loss Detection Circuit...................................................................................31
Figure 5-14. Power Monitor ......................................................................................................31
Figure 6-1. Signal Routing Example.......................................................................................36
Figure 7-1. Simple USB Type A Connection Example ...........................................................41
Figure 7-2. Jetson AGX Xavier Carrier Board Design USB Type C Connection Example....42
Figure 7-3. USB 3.1 USB Micro AB Connection Example .....................................................42
Figure 7-4. PCIe Root Port Connection Example ..................................................................48
Figure 7-5. PCIe Endpoint Connection Example....................................................................49
Figure 7-6. Insertion Loss S-Parameter Plot (SDD21)..........................................................52
Figure 7-7. UFS Connections Example ..................................................................................57
Figure 8-1. Ethernet Connections ..........................................................................................60
Figure 8-2. Gigabit Ethernet Magnetics and RJ45 Connections...........................................60
Figure 9-1. DP and eDP Connection Example .......................................................................65
Figure 9-2. DP and eDP Differential Main Link Topology .....................................................66
Figure 9-3. HDMI Connection Example..................................................................................70
Figure 9-4. HDMI CLK and Data Topology .............................................................................71
Figure 10-1. Camera Control Connections ..............................................................................84
Figure 10-2. Camera CSI D-PHY Connections.........................................................................85
Figure 10-3. Camera CSI C-PHY Connections.........................................................................86

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xii
Figure 10-4. SLVS Connections ................................................................................................91
Figure 11-1. Micro SD Card Socket Connection Example.......................................................95
Figure 12-1. Audio Device Connections..................................................................................100
Figure 13-1. I2C Connections..................................................................................................105
Figure 13-2. SPI Connections .................................................................................................108
Figure 13-3. Basic SPI Master and Slave Connections .........................................................108
Figure 13-4. SPI Point-Point Topology ...................................................................................108
Figure 13-5. SPI Star Topologies............................................................................................108
Figure 13-6. SPI Daisy Topologies..........................................................................................109
Figure 13-7. Jetson AGX Xavier UART Connections ..............................................................111
Figure 13-8. Jetson AGX Xavier CAN Connections ................................................................112
Figure 14-1. Jetson AGX Xavier Fan Connection Example....................................................115
Figure 15-1. JTAG and UART Debug Connections.................................................................117
Figure 15-2. Simple Debug UART Header Connections........................................................117
Figure 15-3. Example Buffer Between Pin Associated with SoC Strap and Connected Device
.............................................................................................................................120
Figure 15-4. Boundary Scan Connections..............................................................................120
Figure 15-5. Safety MCU Connections ...................................................................................122
Figure 19-1. Via Placement for Good Power Distribution .....................................................128
Figure 19-2. Good Current Flow Resulting from Correct Via Placement ............................128
Figure 19-3. Poor Current Flow Resulting from Incorrect Via Placement ..........................128
Figure 21-1. Typical Transmission Lin Circuit.......................................................................131
Figure 21-2. Microstrip Transmission Line............................................................................132
Figure 21-3. Stripline Transmission Line...............................................................................132
Figure 21-4. Transmission Line Height..................................................................................134
Figure 21-5. Crosstalk on Reference Plane...........................................................................135
Figure 21-6. Power Plane Cuts Example ...............................................................................135
Figure 21-7. Power Plane Cuts Example when Decouple Capacitors are abundant ..........135
Figure 21-8. Switching Reference Planes..............................................................................136
Figure 21-9. Reference Plane Switch Using Via ....................................................................136

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xiii
List of Tables
Table 1-1. Abbreviations and Definitions................................................................................2
Table 2-1. Jetson AGX Xavier Specifications ..........................................................................3
Table 2-2. Connector Pinout Matrix Part 1: Columns A-F.....................................................5
Table 2-3. Connector Pinout Matrix Part 2: Columns G-L ....................................................6
Table 3-1. Standoff Height Calculations for 5.5 mm Height Connector Case....................11
Table 3-2. Standoff Height Calculations for 2.5 mm Height Connector Case....................12
Table 5-1. Power, System, and Thermal Pin Descriptions..................................................16
Table 5-2. Internal Power Subsystem Allocation.................................................................18
Table 5-3. Simplified Button Power Circuitry Timing ..........................................................23
Table 5-4. Power Button Supervisor Control Signals..........................................................24
Table 5-5. Power-OFF to On Timing Power Button Case ....................................................26
Table 5-6. Power-OFF to On Timing Auto Power-On Case .................................................27
Table 5-7. Power-On to OFF Timing Power Button Held Low > 10 Seconds......................28
Table 5-8. Jetson AGX Xavier Signal Wake Events...............................................................32
Table 6-1. Signal Type Codes ................................................................................................34
Table 7-1. USB 2.0 Pin Descriptions.....................................................................................37
Table 7-2. UPHY Data Lane Pin Descriptions USB 3.1, PCIe, and UFS ..............................37
Table 7-3. NVHS for PCIe x8 Data Lan Pin Descriptions .....................................................38
Table 7-4. PCIe Clock and Control Pin Descriptions ...........................................................39
Table 7-5. UFS and Miscellaneous USB Control Pin Descriptions.....................................40
Table 7-6. USB 3.1, PCIe and UFS Lane Mapping Configurations......................................40
Table 7-7. USB 2.0 Interface Signal Routing Requirements ...............................................43
Table 7-8. USB 3.1 Interface Signal Routing Requirements ...............................................43
Table 7-9. USB 2.0 Signal Connections ................................................................................47
Table 7-10. USB 3.1 Signal Connections ................................................................................47
Table 7-11. Recommended USB Observation Test Points for Initial Boards .......................47
Table 7-12. PCIe Interface Signal Routing Requirements up to Gen3..................................50
Table 7-13. PCIe Gen4 Interface Signal Routing Requirements ...........................................53
Table 7-14. PCIe Signal Connections Module I/Fs Configured as Root Ports......................54
Table 7-15. PCIe Signal Connections Module I/F Configured as Endpoint ..........................56
Table 7-16. Recommended PCIe Observation Test Points for Initial Boards.......................56
Table 7-17. UFS Interface Signal Routing Requirements .....................................................57
Table 7-18. UFS Signal Connections ......................................................................................58
Table 8-1. Jetson AGX Xavier Gigabit Ethernet Pin Descriptions........................................59
Table 8-2. RGMII Interface Signal Routing Requirements ..................................................61
Table 8-3. Ethernet MDI Interface Signal Routing Requirements ......................................61
Table 8-4. Ethernet Signal Connections...............................................................................62

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xiv
Table 8-5. Recommended Gigabit Ethernet Observation Test Points for Initial Boards ...62
Table 9-1. Jetson AGX Xavier HDMI, eDP, and DP Pin Description ....................................63
Table 9-2. DP and HDMI Pin Mapping ..................................................................................64
Table 9-3. DP and eDP Main Link Signal Routing Requirements .......................................66
Table 9-4. DP and eDP Signal Connections .........................................................................69
Table 9-5. Recommended DP and eDP Observation Test Points for Initial Boards...........69
Table 9-6. HDMI Interface Signal Routing Requirements ...................................................71
Table 9-7. HDMI Signal Connections ....................................................................................76
Table 9-8. Recommended HDMI and DP Observation Test Points for Initial Boards ........76
Table 10-1. Jetson AGX Xavier CSI Pin Description ...............................................................77
Table 10-2. Jetson AGX Xavier Camera Miscellaneous Pin Description ..............................80
Table 10-3. CSI Configurations D-PHY Mode .........................................................................80
Table 10-4. CSI Configurations C-PHY Mode – x2 and x4......................................................82
Table 10-5. CSI Configurations C-PHY – x3 and x1................................................................83
Table 10-6. MIPI CSI D-PHY Interface Signal Routing Requirements ..................................87
Table 10-7. MIPI CSI C-PHY Interface Signal Routing Requirements ..................................88
Table 10-8. MIPI CSI Signal Connections ...............................................................................88
Table 10-9. Miscellaneous MIPI Camera Connections..........................................................89
Table 10-10. Recommended CSI Observation Test Points for Initial Boards.........................89
Table 10-11. Jetson AGX Xavier SLVS EC Camera Pin Description ........................................89
Table 10-12. SLVS Interface Signal Routing Requirements....................................................92
Table 10-13. SLVS Camera Signal Connections ......................................................................93
Table 10-14. Non-Module SLVS Reference Clock Connections..............................................93
Table 11-1. SDIO, SD Card, and eMMC Interface Mapping ...................................................94
Table 11-2. Jetson AGX Xavier SDMMC Pin Descriptions......................................................94
Table 11-3. SDCARD Interface Signal Routing Requirements..............................................95
Table 11-4. SD Card Loading vs. Drive Type...........................................................................96
Table 11-5. SDCARD Signal Connections...............................................................................97
Table 11-6. Recommended SDCARD Observation Test Points for Initial Boards................97
Table 12-1. Jetson AGX Xavier Audio Pin Description............................................................98
Table 12-2. I2S Interface Mapping ..........................................................................................99
Table 12-3. I2S Interface Signal Routing Requirements .....................................................101
Table 12-4. I2S and Miscellaneous Codec Signal Connections...........................................101
Table 12-5. DMIC Interface Signal Routing Requirements .................................................102
Table 12-6. DMIC Signal Connections ..................................................................................102
Table 13-1. Jetson AGX Xavier I2C Pin Description..............................................................103
Table 13-2. I2C Interface Mapping........................................................................................104
Table 13-3. I2C Interface Signal Routing Requirements .....................................................106
Table 13-4. I2C Signal Connections ......................................................................................106
Table 13-5. De-bounce Settings – Fast Mode Plus, Fast Mode, and Standard Mode........107

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xv
Table 13-6. Jetson AGX Xavier SPI Pin Description .............................................................107
Table 13-7. SPI Interface Signal Routing Requirements.....................................................109
Table 13-8. SPI Signal Connections......................................................................................109
Table 13-9. Recommended SPI Observation Test Points for Initial Boards.......................109
Table 13-10. Jetson AGX Xavier UART Pin Description..........................................................110
Table 13-11. UART Signal Connections ..................................................................................111
Table 13-12. Reserved UART4_RX Routing Requirements ...................................................112
Table 13-13. Jetson AGX Xavier CAN Pin Description ...........................................................112
Table 13-14. CAN Interface Signal Routing Requirements...................................................113
Table 13-15. CAN Signal Connections....................................................................................113
Table 14-1. Jetson AGX Xavier Fan Pin Description.............................................................114
Table 14-2. Fan Signal Connections .....................................................................................115
Table 15-1. Jetson AGX Xavier JTAG Pin Description ..........................................................118
Table 15-2. JTAG Signal Connections...................................................................................118
Table 15-3. Debug UART Connections..................................................................................119
Table 15-4. Strapping Pins ....................................................................................................119
Table 15-5. Safety MCU Related Partial Pin Descriptions...................................................121
Table 16-1. MPIO Maximum Output Drive Current ..............................................................124
Table 17-1. Unused MPIO Pins and Pin Groups...................................................................125

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 1
Chapter 1. Introduction
This design guide contains recommendations and guidelines for engineers to follow to create
a product that is optimized to achieve the best performance from the interfaces supported by
the NVIDIA®Jetson AGX Xavier™series System-on-Module (SOM).
This design guide provides detailed information on the capabilities of the hardware module,
which may differ from supported configurations by provided software. Refer to software
release documentation for information on supported capabilities.
Note: References to Jetson AGX Xavier applies to any of the Jetson AGX Xavier series of modules
including Jetson AGX Xavier Industrial (JAXi) except where explicitly noted.
Refer to the following documents or models listed for more information. Always use the latest
revision of all documents.

Jetson AGX Xavier Series Module Data Sheet
 Xavier Series Processors Technical Reference Manual
 Jetson AGX Xavier Series Developer Kit Carrier Board Specification
 Jetson AGX Xavier Series Module Pinmux
 Jetson AGX Xavier Series Thermal Design Guide
 Jetson AGX Xavier Series Developer Kit Carrier Board Design Files
 Jetson AGX Xavier Series Developer Kit Carrier Board BOM
 Jetson AGX Xavier Series Supported Component List
1.2 Abbreviations and Definitions
Table 1-1 lists abbreviations that may be used throughout this document and their definitions.

Introduction
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 2
Table 1-1. Abbreviations and Definitions
Abbreviation Definition
CEC Consumer Electronic Control
CAN Controller Area Network
DP VESA®DisplayPort®(output)
eDP Embedded DisplayPort
eMMC Embedded MMC
HDMI™High Definition Multimedia Interface
I2C Inter IC
I2S Inter IC Sound Interface
LDO Low Dropout (voltage regulator)
LPDDR4x Low Power Double Data Rate DRAM, Fourth-generation
PCIe (PEX) Peripheral Component Interconnect Express interface
PCM Pulse Code Modulation
PHY Physical Layer
PMIC Power Management IC
RTC Real Time Clock
SDIO Secure Digital I/O Interface
SLVS Scalable Low Voltage Signaling
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver-Transmitter
UFS Universal Flash Storage
USB Universal Serial Bus

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 3
Chapter 2. Jetson AGX Xavier
Jetson AGX Xavier resides at the center of the embedded system solution and includes:
Power (PMIC/Regulators, etc.)
DRAM (LPDDR4x)
eMMC
Power and Voltage Monitors
Thermal Sensor
Table 2-1. Jetson AGX Xavier Specifications
Category Function Category Function
USB USB 2.0 (x4)
USB 3.1 (Up to x3)
PCIe x5 (x1 Root Port or Endpoint
and x4 Root Port only
Camera CSI (6x2 or 4x4) D-PHY and C-
PHY
Display HDMI / DP (up to x3) see note
HPD x3, CEC x1, DP_AUX/DDC
x3
LAN Gigabit Ethernet RGMII I/F SPI x3
SD Card SD card or SDIO Fan PWM and TACH
Audio I2S (x4), control and clock
Digital Mic and Speaker IFs
Debug JTAG and UART
CAN x2 System Power control, Reset, Alerts
I2C x8 Power Main Inputs (HV and MV)
UART x5
Note: HDMI and DP share the same pins. See Chapter 9 for display details.

Jetson AGX Xavier
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 4
Figure 2-1. System Block Diagram
Jetson AGX Xavier
LPDDR4x eMMC
SYS_VIN_HV USB 2.0 3x
1RGMII
UART 3x
I2S x4
I2C 8x
CSI: 4 x4, or 6 x2
HDMI_DP 3x
SD CARD
USB 3.13x
Debug: JTAG & UART
CAM MCLK 2x
GPIO s1
Xavier SoC
Thermal
Sensor D P_ AUX 3x
Power Subsystem
PMIC
Re gul at ors
Power/Vo ltage Monitors
DMIC x4
DSPK x2
CAN 2x
UFS x1
PCIe: 2 x1, 1 x2,
1 x4, & 1 x8
2
SPI 3x1
PWM 4x
AUD_M CLK UFS CLK/RST
SYS_VIN_MV
Rail Discharg e
HPD 3x, CEC 1x
GP Clocks x2
FAN
Safety ( JAXi only):
V M I2 C/IN T
T EMP_A LERT _OUT
(See note 1)
SLVS 1 x82
(Not on JAXi)
Notes:
1. SPI2, RGMII, GPIO31, and GPIO33 are available to use with a Safety MCU.
2. PCIe x8 interface and SLVS share the same pins.

Jetson AGX Xavier
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 5
Table 2-2. Connector Pinout Matrix Part 1: Columns A-F
A B C D E F
01 SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV
02 SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV
03 PRSNT0 SYS_VIN_HV GND SYS_VIN_HV GND SYS_VIN_HV
04 SDCARD_D2 GND RGMII_RD0 GND I2S2_FS GND
05 SDCARD_CMD RGMII_TXC RGMII_RXC RGMII_RX_CTL RGMII_RD3 I2S2_DOUT
06 UFS0_REF_CLK SDCARD_CLK UFS0_RST_N SDCARD_D3 RGMII_SMA_MDC I2S2_DIN
07 GPIO29 GND I2S1_SDOUT GND RGMII_SMA_MDIO GND
08 PEX_WAKE_N GPIO11 PEX_L5_CLKREQ_
N
I2S1_FS SDCARD_D0 SDCARD_D1
09 GND PEX_L1_RST_N GND PEX_L1_CLKREQ_
N
GND GPIO16
10 USB2_P RSVD USB1_N PEX_L0_RST_N GPIO12 GPIO15
11 USB2_N GND USB1_P GND PEX_L0_CLKREQ_
N
GND
12 GND UPHY_RX10_P GND UPHY_RX11_P GND USB0_P
13 GND UPHY_RX10_N GND UPHY_RX11_N GND USB0_N
14 UPHY_RX8_N GND UPHY_RX9_N GND PEX_CLK0_N GND
15
UPHY_RX8_P
GND
UPHY_RX9_P
GND
PEX_CLK0_P
GND
16 GND UPHY_RX6_P GND UPHY_RX7_P GND PEX_CLK1_P
17 GND UPHY_RX6_N GND UPHY_RX7_N GND PEX_CLK1_N
18 UPHY_RX4_P GND UPHY_RX5_N GND RSVD GND
19 UPHY_RX4_N GND UPHY_RX5_P GND RSVD GND
20 GND UPHY_RX2_N GND UPHY_RX3_P GND PEX_CLK3_P
21 GND UPHY_RX2_P GND UPHY_RX3_N GND PEX_CLK3_N
22 UPHY_RX0_P GND UPHY_RX1_N GND PEX_CLK4_N GND
23 UPHY_RX0_N GND UPHY_RX1_P GND PEX_CLK4_P GND
24
GND
NVHS0_SLVS_
RX1_N
GND
NVHS0_SLVS_RX0_
P
GND
PEX_CLK5_P
25 GND NVHS0_SLVS_
RX1_P
GND NVHS0_SLVS_RX0_
N
GND PEX_CLK5_N
26 NVHS0_SLVS_
RX3_P
GND NVHS0_SLVS_
RX2_N
GND UPHY_REFCLK1_N GND
27 NVHS0_SLVS_RX3_
N
GND NVHS0_SLVS_RX2_
P
GND UPHY_REFCLK1_P GND
28 GND NVHS0_SLVS_
RX5_N
GND NVHS0_SLVS_
RX4_P
GND RSVD
29
GND
NVHS0_SLVS_
RX5_P
GND
NVHS0_SLVS_RX4_
N
GND
RSVD
30 NVHS0_SLVS_
RX7_P
GND NVHS0_SLVS_
RX6_N
GND NVHS0_SLVS_
REFCLK0_P
GND
31 NVHS0_SLVS_
RX7_N
GND NVHS0_SLVS_
RX6_P
GND NVHS0_SLVS_
REFCLK0_N
GND
32 GND RSVD GND RSVD GND RSVD
33 GND RSVD GND RSVD GND RSVD
34
RSVD
GND
RSVD
GND
RSVD
GND
35 RSVD GND RSVD GND RSVD GND
36 GND RSVD GND RSVD GND RSVD
37 GND RSVD GND RSVD GND RSVD
38 RSVD GND RSVD GND CSI0_D1_N GND
39 RSVD GND RSVD GND CSI0_D1_P GND
40 GND RSVD GND RSVD GND RSVD
41 CSI2_D0_P GND CSI2_D1_N GND CSI0_D0_N GND
42 CSI2_D0_N CSI2_CLK_N CSI2_D1_P CSI5_D0_P CSI0_D0_P CSI0_CLK_N
43 GND CSI2_CLK_P GND CSI5_D0_N GND CSI0_CLK_P
44 CSI7_D0_P GND CSI5_CLK_P GND CSI3_D0_N GND