Cypress S6J3200 Series User manual
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2 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 3
Preface
Thank you for your continued use of Cypress semiconductor products.
Read this manual and "Data Sheet" thoroughly before using products in this family.
Purpose of This Manual and Intended Readers
This manual explains the functions and operations of this family and describes how it is used. The manual
is intended for engineers engaged in the actual development of products using this family.
*This manual explains the configuration and operation of the peripheral functions, but does not cover the
specifics of each device in the family.
Users should refer to the respective data sheets of devices for device-specific details.
4 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Table of Contents
CHAPTER 1: Overview......................................................................................................................21
1. Overview ..............................................................................................................................22
2. Document Definition.............................................................................................................22
3. Register Attribute..................................................................................................................23
3.1. Read and Write.......................................................................................................23
3.2. Protection ...............................................................................................................23
3.3. Register Information ...............................................................................................24
4. Abbreviation..........................................................................................................................24
CHAPTER 2: Function List.................................................................................................................27
1. Function List.........................................................................................................................28
2. Optional Function .................................................................................................................31
2.1. Basic Option ...........................................................................................................31
2.2. ID............................................................................................................................36
2.3. Restriction ..............................................................................................................36
CHAPTER 3: Product Description......................................................................................................38
1. Overview ..............................................................................................................................39
2. Product Description..............................................................................................................39
2.1. Ethernet..................................................................................................................45
2.2. Reset Signal ...........................................................................................................45
3. Note......................................................................................................................................47
3.1. Status Flag Clear....................................................................................................47
3.2. Error Response ......................................................................................................47
3.3. Register Initial Value...............................................................................................48
3.4. Restriction ..............................................................................................................51
CHAPTER 4: Block Diagram..............................................................................................................52
1. Block Diagram......................................................................................................................53
2. Note......................................................................................................................................53
CHAPTER 5: Clock Configuration......................................................................................................54
1. Overview ..............................................................................................................................55
2. Operation..............................................................................................................................55
2.1. Spread Spectrum Clock Generator (SSCG) ...........................................................59
3. Remark.................................................................................................................................60
CHAPTER 6: Operation Mode ...........................................................................................................61
1. Overview ..............................................................................................................................62
2. Configuration........................................................................................................................62
3. Registers ..............................................................................................................................62
CHAPTER 7: Memory and Base Address Map..................................................................................63
1. Memory Map.........................................................................................................................64
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 5
2. Base Address Map...............................................................................................................66
3. Note......................................................................................................................................73
CHAPTER 8: IRQ and NMI Map........................................................................................................74
1. IRQ Map...............................................................................................................................75
2. NMI Map...............................................................................................................................83
CHAPTER 9: DMA Channel Activation Factors .................................................................................84
1. Factors List...........................................................................................................................85
2. Note......................................................................................................................................90
CHAPTER 10: Port Description ...........................................................................................................91
1. Port Description List .............................................................................................................92
2. Remark...............................................................................................................................111
CHAPTER 11: Port Configuration......................................................................................................112
1. Overview ............................................................................................................................113
2. Configuration and Block Diagram.......................................................................................114
3. Operation............................................................................................................................115
3.1. Resource Input Configuration Module .................................................................. 115
3.2. Port Output Function Configuration ......................................................................192
3.3. Analog I/O Setting ................................................................................................205
3.4. Input Level Setting................................................................................................205
3.5. Output Drive Capacity Setting ..............................................................................209
3.6. Port Status............................................................................................................213
3.7. Function Port Group .............................................................................................214
3.8. Key Code Register ...............................................................................................217
4. Registers ............................................................................................................................218
5. Configuration Procedure.....................................................................................................218
5.1. Resource I/O Port (Both Direction) .......................................................................219
5.2. Resource Input .....................................................................................................220
5.3. Resource Output ..................................................................................................221
5.4. Port Function Input ...............................................................................................222
5.5. Port Function Output ............................................................................................223
5.6. Analog Function Input or Output...........................................................................224
6. Precautions.........................................................................................................................225
6.1. Noise Filter ...........................................................................................................225
CHAPTER 12: State Transition..........................................................................................................227
1. Overview ............................................................................................................................228
2. Diagram of State Transition................................................................................................229
3. Fetching the Operation Mode.............................................................................................231
4. Changes to PSS and RUN .................................................................................................235
CHAPTER 13: Low-voltage Detection................................................................................................238
1. Overview ............................................................................................................................239
2. Configuration and Block Diagram.......................................................................................239
3. Operation............................................................................................................................240
3.1. LVD operation.......................................................................................................240
3.2. Configurations ......................................................................................................240
4. Registers ............................................................................................................................241
5. Electric Characteristics.......................................................................................................244
CHAPTER 14: Serial Programming ...................................................................................................245
1. Overview ............................................................................................................................246
Table of Contents
6 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
2. Memory Map.......................................................................................................................246
3. FLASH Sector Configuration ..............................................................................................246
4. Port Configuration...............................................................................................................246
5. Operation............................................................................................................................247
5.1. Timing Chart .........................................................................................................247
5.2. RAM Executing Communication Protocol.............................................................247
5.3. Operation Flow .....................................................................................................251
6. Note....................................................................................................................................252
6.1. PSC Port State .....................................................................................................252
CHAPTER 15: 12-/10-/8-bit Analog to Digital Converter....................................................................253
1. Overview ............................................................................................................................254
2. Configuration and Block Diagram.......................................................................................256
3. Operation of A/D Converter................................................................................................257
3.1. A/D Conversion Flow............................................................................................257
3.2. Logical Channel Mapping to Analog Input Signals ...............................................259
3.3. Logical Channel Data Protection Function ...........................................................259
3.4. Logical Channel Triggering and Priority................................................................261
3.5. Group Processing.................................................................................................263
3.6. Multiple Conversion Logical Channels..................................................................271
3.7. Forced Stop..........................................................................................................274
3.8. A/D Converter Calibration.....................................................................................275
3.9. DMA Transfer Function.........................................................................................277
3.10. Range Comparator Function ................................................................................277
3.11. Pulse Detection Function......................................................................................280
3.12. Debug Mode.........................................................................................................282
4. Setup Procedure Examples................................................................................................283
4.1. Control of A/D Conversion ....................................................................................283
4.2. Setting of Global A/D Conversion .........................................................................284
4.3. Setting of Logical Channel....................................................................................285
4.4. Setting of Range Comparator...............................................................................286
4.5. Setting of Pulse Detection ....................................................................................287
4.6. A/D Conversion ....................................................................................................288
4.7. Range Comparator ...............................................................................................290
4.8. Pulse Detection ....................................................................................................291
5. Registers ............................................................................................................................292
5.1. A/D Channel Control Registers (ADC12Bn_CHCTRL0 to 63)..............................293
5.2. A/D Channel Status Registers (ADC12Bn_CHSTAT0 to 63) ................................297
5.3. A/D Conversion Data Registers (ADC12Bn_CD0 to 63) ......................................299
5.4. Pulse Counter Control Registers (ADC12Bn_PCCTRL0 to 63)............................301
5.5. A/D Conversion Done Interrupt Flag Registers (ADC12Bn_CDONEIRQ0 to 1) ...303
5.6. A/D Conversion Done Interrupt Enable Registers (ADC12Bn_CDONEIRQE0 to
1) ..........................................................................................................................306
5.7. A/D Conversion Done Interrupt Clear Registers (ADC12Bn_CDONEIRQC0 to 1)309
5.8. Group Interrupted Interrupt Flag Registers (ADC12Bn_GRPIRQ0 to 1)...............312
5.9. Group Interrupted Interrupt Enable Registers (ADC12Bn_GRPIRQE0 to 1) ........315
5.10. Group Interrupted Interrupt Clear Registers (ADC12Bn_GRPIRQC0 to 1) ..........317
5.11. Range Comparator Interrupt Flag Registers (ADC12Bn_RCIRQ0 to 1) ...............319
5.12. Range Comparator Interrupt Enable Registers (ADC12Bn_RCIRQE0 to 1) ........323
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 7
5.13. Range Comparator Interrupt Clear Registers (ADC12Bn_RCIRQC0 to 1)...........325
5.14. Pulse Counter Interrupt Flag Registers (ADC12Bn_PCIRQ0 to 1) .......................327
5.15. Pulse Counter Interrupt Enable Registers (ADC12Bn_PCIRQE0 to 1) ................330
5.16. Pulse Counter Interrupt Clear Registers (ADC12Bn_PCIRQC0 to 1)...................332
5.17. A/D Channel Trigger Status Flag Registers (ADC12Bn_TRGST0 to 1)................335
5.18. A/D Channel Trigger Clear Registers (ADC12Bn_TRGCL0 to 1) .........................339
5.19. A/D Channel Trigger Overrun Flag Registers (ADC12Bn_TRGOR0 to 1) ............343
5.20. A/D Channel Trigger Overrun Clear Registers (ADC12Bn_TRGORC0 to 1)........346
5.21. Range Comparator Over Threshold Flag Registers (ADC12Bn_RCOTF0 to 1) ...348
5.22. Conversion Done DMA Select Registers (ADC12Bn_CDDS0 to 3)......................351
5.23. A/D Converter Comparison Time Setting Register (ADC12Bn_CT) .....................353
5.24. A/D Converter Resumption Time Setting Register (ADC12Bn_RT)......................354
5.25. A/D Converter Sampling Time Setting Registers (ADC12Bn_ST0 to 3) ...............355
5.26. A/D Converter Offset Compensation Setting Register (ADC12Bn_OCV).............356
5.27. A/D Converter Gain Compensation Setting Register (ADC12B_GCV).................357
5.28. A/D Converter Global Control Register (ADC12Bn_CTRL) ..................................358
5.29. A/D Converter Global Status Register (ADC12Bn_STAT) ....................................361
5.30. Range Comparator Upper Threshold Registers (ADC12Bn_RCOH0 to 7)...........363
5.31. Range Comparator Lower Threshold Registers (ADC12Bn_RCOL0 to 7) ...........364
5.32. Full Range Comparator Upper Threshold Registers (ADC12Bn_FRCOH0 to 7)
.............................................................................................................................365
5.33. Full Range Comparator Lower Threshold Registers (ADC12Bn_FRCOL0 to 7)
.............................................................................................................................367
5.34. A/D Multiple Conversion Channel Control Registers (ADC12Bn_MCCTRL0 to 3)
.............................................................................................................................369
5.35. A/D Multiple Conversion Channel Status Registers (ADC12Bn_MCSTAT0 to 3)
.............................................................................................................................371
CHAPTER 16: Stepper Motor Controller............................................................................................372
1. Overview ............................................................................................................................373
2. Configuration and Block Diagram.......................................................................................374
3. Operation of the Stepper Motor Controller..........................................................................376
3.1. Operation of PWM Pulse Generator .....................................................................376
3.2. Selection of Motor Drive Signals...........................................................................380
3.3. Synchronization System of Stepper Motor Controller ...........................................381
3.4. Operation of the SMC Trigger Delay Function......................................................382
4. Registers ............................................................................................................................385
4.1. PWM Control Register (PWC) ..............................................................................386
4.2. PWM1 and PWM2 Compare Registers (PWC1, PWC2) ......................................389
4.3. PWM Selection Register (PWS) ...........................................................................393
4.4. PWM Selection Set Register (PWSS) ..................................................................396
4.5. SMC Trigger Delay Register (PTRGDL) ...............................................................398
CHAPTER 17: Trigger Configuration of Stepper Motor Controller .....................................................399
1. Overview ............................................................................................................................400
2. Configuration and Block Diagram.......................................................................................400
3. Operation............................................................................................................................401
4. Registers ............................................................................................................................401
4.1. SMC Trigger Selection Register (SMCTGg_PTRGS)...........................................402
4.2. SMC Trigger Register (SMCTGg_PTRG).............................................................405
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8 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
CHAPTER 18: Sound Generator........................................................................................................407
1. Overview ............................................................................................................................408
2. Configuration......................................................................................................................409
3. Operations..........................................................................................................................410
3.1. Relation between the Amplitude Data Register (SGAR) and PWM Pulse ............412
3.2. Relation between the Frequency Data Register (SGFR) and Tone Pulse Signal
.............................................................................................................................413
3.3. Relation between the PWM Cycle Data Register (SGPCR) and PWM Cycle.......414
3.4. Relation between the DMA Transfer Update Enable Register (SGDER) and DMA
Settings ................................................................................................................415
3.5. Sound Generator Operation .................................................................................420
3.6. Continuous Operation of Sound Generator by MCU ............................................423
3.7. Sound Generator Operation with DMA .................................................................425
3.8. Interrupt of Sound Generator................................................................................442
4. Registers ............................................................................................................................443
4.1. DMA Transfer Update Enable Register (SGDER).................................................444
4.2. Sound Control Register (SGCR)...........................................................................446
4.3. Amplitude Data Register (SGAR) .........................................................................450
4.4. Frequency Data Register (SGFR) ........................................................................451
4.5. Tone Output Number Register (SGNR) ................................................................452
4.6. Time Cycle Register (SGTCR) .............................................................................453
4.7. Increase and Decrease Data Register (SGIDR)...................................................454
4.8. PWM Cycle Data Register (SGPCR)....................................................................455
4.9. DMA Transfer Intermediate Register (SGDMAR) .................................................456
4.10. Interrupt Clear Register (SGCCR) ........................................................................458
CHAPTER 19: Sound Waveform Generator ......................................................................................459
1. Overview ............................................................................................................................460
2. Configuration and Block Diagram.......................................................................................461
3. Operation of the Sound Waveform Generator....................................................................462
3.1. Sound Source Specifications................................................................................462
3.2. Interrupt ................................................................................................................464
3.3. SWFG Sound Source Generation Start................................................................464
3.4. SWFG Sound Source Generation Stop ................................................................464
3.5. Continuous SWFG Sound Source Generation .....................................................465
3.6. Filter .....................................................................................................................466
4. Registers ............................................................................................................................468
4.1. Waveform Generator Channel Enable Register (WGCHEN)................................468
4.2. Waveform Generator Channel Start Register (WGCHSTART) .............................470
4.3. Waveform Generator Channel Address1 Register (WGCHADD1) .......................472
4.4. Waveform Generator Channel Address2 Register (WGCHADD2) .......................474
4.5. Waveform Generator Channel Address3 Register (WGCHADD3) .......................476
4.6. Waveform Generator Channel Monaural Register (WGCHMONO)......................477
4.7. Waveform Generator Channel n Control Register1 (WGCHnCTRL1, n=0 to 4)
.............................................................................................................................479
4.8. Waveform Generator Channel n Control Register2 (WGCHnCTRL2, n=0 to 4)
.............................................................................................................................483
4.9. Waveform Generator Channel n Control Register3 (WGCHnCTRL3, n=0 to 4)
.............................................................................................................................485
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 9
4.10. Waveform Generator Channel Clear Register (WGCHCLR) ................................488
4.11. Waveform Generator Interrupt Enable Register (WGINTREN).............................490
4.12. Waveform Generator Interrupt State Register (WGINTRSTATE) .........................492
4.13. Waveform Generator Interrupt Clear Register (WGINTRCLR) .............................494
4.14. Waveform Generator AHB Bus Error Register (WGAHBERR) .............................496
CHAPTER 20: Sound Mixer...............................................................................................................498
1. Overview ............................................................................................................................499
2. Configuration and Block Diagram.......................................................................................500
3. Operation of the Sound Mixer.............................................................................................501
3.1. Basic Mixing Operation Procedure .......................................................................501
3.2. Volume Effects......................................................................................................503
3.3. Sound Source Input and Internal Mixing Process Mode.......................................504
3.4. Interrupt ................................................................................................................505
3.5. Data Request Control ...........................................................................................505
3.6. Data Output Control..............................................................................................506
3.7. AHB Slave Interface .............................................................................................506
3.8. AHB Master Interface ...........................................................................................507
3.9. Input Buffer (FIFO) ...............................................................................................507
3.10. Sound Source Sampling Rate ..............................................................................508
4. Registers ............................................................................................................................509
4.1. Mixer Channel Register (MXCH) ..........................................................................509
4.2. Mixer Output Control Register (MXOCTRL) ......................................................... 511
4.3. Mixer Date Request Control Register (MXDRQCTRL) .........................................513
4.4. Mixer Input Control Register (MXICTRL)..............................................................515
4.5. Mixer Channel Monaural Register (MXCHMONO) ...............................................517
4.6. Mixer Channel Volume1 Register (MXCHVOL1) ..................................................519
4.7. Mixer Channel Volume2 Register (MXCHVOL2) ..................................................520
4.8. Mixer Channel Volume3 Register (MXCHVOL3) ..................................................521
4.9. Mixer Channel Mute Register (MXCHMUTE) .......................................................522
4.10. Mixer Channel Fade_In/Out1 Register (MXCHFADE1) ........................................524
4.11. Mixer Channel Fade_In/Out2 Register (MXCHFADE2) ........................................526
4.12. Mixer Channel Fade_In/Out3 Register (MXCHFADE3) ........................................528
4.13. Mixer Channel Fade_In/Out4 Register (MXCHFADE4) ........................................530
4.14. Mixer Channel Fade_in/out5 Register (MXCHFADE5) .........................................532
4.15. Mixer Mixed Fade_In/Out Register (MXMXDFADE) .............................................534
4.16. Mixer Channel Fade_In/Out Enable Register (MXCHFADEEN) ...........................535
4.17. Mixer Buffer Clear Register (MXBUFFCLR) .........................................................537
4.18. Mixer FADE_In/Out Clear Register (MXFADECLR)..............................................539
4.19. Mixer Interrupt Enable Register (MXINTREN)......................................................541
4.20. Mixer Interrupt Status Register (MXINTRSTATE).................................................544
4.21. Mixer Interrupt Clear Register (MXINTRCLR) ......................................................547
4.22. Mixer Input Buffer Count1 Register (MXINBUFFCNT1) .......................................550
4.23. Mixer Input Buffer Count2 Register (MXINBUFFCNT2) .......................................553
4.24. Mixer Channel Buffer Count Register (MXCHBUFFCNT) ....................................555
4.25. Mixer Output Buffer Count Register (MXOUTBUFFCNT).....................................557
4.26. Mixer AHB Bus Error Register (MXAHBERR) ......................................................559
4.27. Mixer WFGn Data Address Register (MXWFGnDADR, n=0 to 4) ........................562
4.28. Mixer PCM/I2S n Data Address Register0-15 (MXPMISnDADR0-15, n=0 to 4)...563
Table of Contents
10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5. Appendix ............................................................................................................................564
5.1. Gain for Volume Control .......................................................................................564
5.2. Fade In/Fade Out Time.........................................................................................571
5.3. Digital Filter ..........................................................................................................572
CHAPTER 21: Ethernet MAC ............................................................................................................575
1. Overview ............................................................................................................................576
2. Configuration and Block Diagram.......................................................................................578
3. Operation of the Ethernet MAC ..........................................................................................579
3.1. Direct Memory Access Interface ...........................................................................579
3.2. MAC Transmitter Block.........................................................................................594
3.3. MAC Receiver Block.............................................................................................595
3.4. Checksum Offload for IP, TCP, and UDP..............................................................595
3.5. MAC Filtering Block ..............................................................................................597
3.6. IEEE Std 1588 and IEEE Std 802.1AS Support ...................................................600
3.7. MAC IEEE Std 802.3 Pause Frame Support ........................................................605
3.8. MAC PFC Based Pause Frame Support ..............................................................607
3.9. Energy Efficient Ethernet Support ........................................................................609
3.10. LPI Operation in Ethernet MAC ............................................................................609
3.11. IEEE Std 802.1Qav Support – Credit Based Shaping ..........................................610
3.12. PHY Interface .......................................................................................................610
3.13. Jumbo Frames......................................................................................................610
4. Registers ............................................................................................................................611
4.1. Network Control Register (ETHERNETn_network_control)..................................619
4.2. Network Configuration Register (ETHERNETn_network_configuration) ..............623
4.3. Network StatusNetwork Status Register (ETHERNETn_network_status) ............628
4.4. DMA Configuration Register (ETHERNETn_dma_config) ....................................630
4.5. Transmit Status Register (ETHERNETn_transmit_status) ...................................634
4.6. RX Buffer Queue Base Address Register (ETHERNETn_receive_q_ptr).............636
4.7. TX Buffer Queue Base Address Register (ETHERNETn_transmit_q_ptr)............638
4.8. Receive Status Register (ETHERNETn_receive_status) .....................................640
4.9. Interrupt Status Register (ETHERNETn_int_status).............................................642
4.10. Interrupt Enable Register (ETHERNETn_int_enable)...........................................647
4.11. Interrupt Disable Register (ETHERNETn_int_disable) .........................................650
4.12. Interrupt Mask Register (ETHERNETn_int_mask) ...............................................653
4.13. PHY Maintenance Register (ETHERNETn_phy_management) ...........................660
4.14. Receive Pause Quantum Register (ETHERNETn_pause_time) ..........................662
4.15. Transmit Pause Quantum Register (ETHERNETn_tx_pause_quantum)..............663
4.16. TX Partial Store and Forward Register (ETHERNETn_pbuf_txcutthru)................664
4.17. RX Partial Store and Forward Register (ETHERNETn_pbuf_rxcutthru) ...............666
4.18. Jumbo-Frame Maximum Length Register (ETHERNETn_jumbo_max_length)....668
4.19. AXI Maximum Pipeline Register (ETHERNETn_axi_max_pipeline) .....................669
4.20. Hash Bottom Register (ETHERNETn_hash_bottom) ...........................................671
4.21. Hash Top Register (ETHERNETn_hash_top).......................................................672
4.22. Specific Address Bottom i Register (ETHERNETn_spec_add_bottom_i) (i=1 to 4)
.............................................................................................................................673
4.23. Specific Address Top i Register (ETHERNETn_spec_add_top_i) (i=1 to 4) .........674
4.24. Type ID Match i Register (ETHERNETn_spec_type_i) (i= 1 to 4) ........................676
4.25. IPG Stretch Register (ETHERNETn_stretch_ratio) ..............................................677
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 11
4.26. Stacked VLAN Register (ETHERNETn_stacked_vlan) ........................................678
4.27. Transmit PFC Pause Register (ETHERNETn_tx_pfc_pause) ..............................679
4.28. Specific Address Mask 1 Bottom Register (ETHERNETn_mask_add1_bottom)
.............................................................................................................................681
4.29. Specific Address Mask 1 Top Register (ETHERNETn_mask_add1_top) .............682
4.30. RX PTP Unicast IP Destination Address Register (ETHERNETn_rx_ptp_unicast)
.............................................................................................................................683
4.31. TX PTP Unicast IP Destination Address Register (ETHERNETn_tx_ptp_unicast)
.............................................................................................................................684
4.32. Receive DMA Data Buffer Address Mask Register
(ETHERNETn_dma_addr_or_mask) ....................................................................685
4.33. IEEE 1588 Timer Comparison Value Nanoseconds Register
(ETHERNETn_tsu_nsec_cmp).............................................................................687
4.34. IEEE 1588 Timer Comparison Value Seconds Bottom Register
(ETHERNETn_tsu_sec_cmp)...............................................................................688
4.35. IEEE 1588 Timer Comparison Value Seconds Top Register
(ETHERNETn_tsu_msb_sec_cmp) ......................................................................689
4.36. PTP Event Frame Transmitted Seconds [47:32] Register
(ETHERNETn_tsu_ptp_tx_msb_sec) ...................................................................690
4.37. PTP Event Frame Received Seconds [47:32] Register
(ETHERNETn_tsu_ptp_rx_msb_sec)...................................................................691
4.38. PTP Peer Event Frame Transmitted Seconds [47:32] Register
(ETHERNETn_tsu_peer_tx_msb_sec).................................................................692
4.39. PTP Peer Event Frame Received Seconds [47:32] Register
(ETHERNETn_tsu_peer_rx_msb_sec).................................................................693
4.40. Identification and Revision Register (ETHERNETn_revision_reg) .......................694
4.41. Octets Transmitted Bottom Register (ETHERNETn_octets_txed_bottom) ...........695
4.42. Octets Transmitted Top Register (ETHERNETn_octets_txed_top).......................696
4.43. Frames Transmitted Register (ETHERNETn_frames_txed_ok) ...........................697
4.44. Broadcast Frames Transmitted Register (ETHERNETn_broadcast_txed) ...........698
4.45. Multicast Frames Transmitted Register (ETHERNETn_multicast_txed)...............699
4.46. Pause Frames Transmitted Register (ETHERNETn_pause_frames_txed) ..........700
4.47. 64 Byte Frames Transmitted Register (ETHERNETn_frames_txed_64) ..............701
4.48. 65 To 127 Byte Frames Transmitted Register (ETHERNETn_frames_txed_65) ..702
4.49. 128 To 255 Byte Frames Transmitted Register (ETHERNETn_frames_txed_128)
.............................................................................................................................703
4.50. 256 To 511 Byte Frames Transmitted Register (ETHERNETn_frames_txed_256)
.............................................................................................................................704
4.51. 512 To 1023 Byte Frames Transmitted Register
(ETHERNETn_frames_txed_512) ........................................................................705
4.52. 1024 To 1518 Byte Frames Transmitted Register
(ETHERNETn_frames_txed_1024) ......................................................................706
4.53. Greater Than 1518 Byte Frames Transmitted Register
(ETHERNETn_frames_txed_1519) ......................................................................707
4.54. Transmit Under Runs Register (ETHERNETn_tx_underruns)..............................709
4.55. Single Collision Frames Register (ETHERNETn_single_collisions) .....................710
4.56. Multiple Collision Frames Register (ETHERNETn_multiple_collisions)................ 711
4.57. Excessive Collisions Register (ETHERNETn_excessive_collisions) ....................712
Table of Contents
12 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.58. Late Collisions Register (ETHERNETn_late_collisions) .......................................713
4.59. Deferred Transmission Frames Register (ETHERNETn_deferred_frames) .........714
4.60. Carrier Sense Errors Register (ETHERNETn_crs_errors)....................................715
4.61. Octets Receive Bottom Register (ETHERNETn_octets_rxed_bottom).................716
4.62. Octets Receive TOP Register (ETHERNETn_octets_rxed_top)...........................717
4.63. Frames Received Register (ETHERNETn_frames_rxed_ok)...............................718
4.64. Broadcast Frames Received Register (ETHERNETn_broadcast_rxed)...............719
4.65. Multicast Frames Received Register (ETHERNETn_multicast_rxed) ..................720
4.66. Pause Frames Received Register (ETHERNETn_pause_frames_rxed)..............721
4.67. 64 Byte Frames Received Register (ETHERNETn_frames_rxed_64)..................722
4.68. 65 To 127 Byte Frames Received Register (ETHERNETn_frames_rxed_65)......723
4.69. 128 To 255 Byte Frames Received Register (ETHERNETn_frames_rxed_128)
.............................................................................................................................724
4.70. 256 To 511 Byte Frames Received Register (ETHERNETn_frames_rxed_256)
.............................................................................................................................725
4.71. 512 To 1023 Byte Frames Received Register (ETHERNETn_frames_rxed_512)
.............................................................................................................................726
4.72. 1024 To 1518 Byte Frames Received Register
(ETHERNETn_frames_rxed_1024) ......................................................................727
4.73. Greater than 1518 Byte Frames Received Register
(ETHERNETn_frames_rxed_1519) ......................................................................728
4.74. Undersized Frames Received Register (ETHERNETn_undersized_frames) .......729
4.75. Oversize Frames Received Register (ETHERNETn_excessive_rx_length) .........730
4.76. Jabbers Received Register (ETHERNETn_rx_jabbers) .......................................731
4.77. Frame Check Sequence Errors Register (ETHERNETn_fcs_errors) ...................732
4.78. Length Field Frame Errors Register (ETHERNETn_rx_length_errors).................733
4.79. Receive Symbol_Errors Register (ETHERNETn_rx_symbol_errors) ...................734
4.80. Alignment Errors Register (ETHERNETn_alignment_errors) ...............................735
4.81. Receive Resource Errors Register (ETHERNETn_rx_resource_errors) ..............736
4.82. Receive Over Runs Register (ETHERNETn_rx_overruns)...................................737
4.83. IP Header Checksum Errors Register (ETHERNETn_rx_ip_ck_errors) ...............738
4.84. TCP Checksum Errors Register (ETHERNETn_rx_tcp_ck_errors) ......................739
4.85. UDP Checksum Errors Register (ETHERNETn_rx_udp_ck_errors).....................740
4.86. Receive DMA Flushed Packets Register (ETHERNETn_auto_flushed_pkts) ......741
4.87. IEEE 1588 Timer Increment Sub Nanoseconds Register
(ETHERNETn_tsu_timer_incr_sub_nsec) ............................................................743
4.88. IEEE 1588 Timer Seconds [47:32] Register (ETHERNETn_tsu_timer_msb_sec)
.............................................................................................................................744
4.89. IEEE 1588 Timer Seconds [31:0] Register (ETHERNETn_tsu_timer_sec) ..........745
4.90. IEEE 1588 Timer Nanoseconds Register (ETHERNETn_tsu_timer_nsec) ..........746
4.91. IEEE 1588 Timer Adjust Register (ETHERNETn_tsu_timer_adjust).....................747
4.92. IEEE 1588 Timer Increment Register (ETHERNETn_tsu_timer_incr) ..................748
4.93. PTP Event Frame Transmitted Seconds [31:0] Register
(ETHERNETn_tsu_ptp_tx_sec)............................................................................750
4.94. PTP Event Frame Transmitted Nanoseconds Register
(ETHERNETn_tsu_ptp_tx_nsec)..........................................................................751
4.95. PTP Event Frame Received Seconds [31:0] Register
(ETHERNETn_tsu_ptp_rx_sec)............................................................................752
Table of Contents
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 13
4.96. PTP Event Frame Received Nanoseconds Register
(ETHERNETn_tsu_ptp_rx_nsec)..........................................................................753
4.97. PTP Peer Event Frame Transmitted Seconds [31:0] Register
(ETHERNETn_tsu_peer_tx_sec)..........................................................................754
4.98. PTP Peer Event Frame Transmitted Nanoseconds Register
(ETHERNETn_tsu_peer_tx_nsec)........................................................................755
4.99. PTP Peer Event Frame Received Seconds [31:0] Register
(ETHERNETn_tsu_peer_rx_sec) .........................................................................756
4.100. PTP Peer Event Frame Received Nanoseconds Register
(ETHERNETn_tsu_peer_rx_nsec) .......................................................................757
4.101. Transmit Pause Quantum 1 Register (ETHERNETn_tx_pause_quantum1).........758
4.102. Transmit Pause Quantum 2 Register (ETHERNETn_tx_pause_quantum2).........759
4.103. Transmit Pause Quantum 3 Register (ETHERNETn_tx_pause_quantum3).........760
4.104. Receive LPI Transitions Register (ETHERNETn_rx_lpi) ......................................761
4.105. Received LPI Time Register (ETHERNETn_rx_lpi_time) .....................................762
4.106. Transmit LPI Transitions Register (ETHERNETn_tx_lpi)......................................763
4.107. Transmit LPI Time Register (ETHERNETn_tx_lpi_time).......................................764
4.108. Design Configuration 3 Register (ETHERNETn_designcfg_debug3)...................765
4.109. Design Configuration 4 Register (ETHERNETn_designcfg_debug4) ...................766
4.110. Design Configuration 5 Register (ETHERNETn_designcfg_debug5)...................767
4.111. Design Configuration 6 Register (ETHERNETn_designcfg_debug6) ...................769
4.112. Design Configuration 7 Register (ETHERNETn_designcfg_debug7)...................772
4.113. Design Configuration 8 Register (ETHERNETn_designcfg_debug8)...................774
4.114. Design Configuration 9 Register (ETHERNETn_designcfg_debug9)...................776
4.115. Design Configuration 10 Register (ETHERNETn_designcfg_debug10) ...............778
4.116. Interrupt Status Queue i Register (ETHERNETn_int_status_qi) (i=1 to 3) ...........780
4.117. TX Buffer Queue 1 Base Address Register (ETHERNETn_transmit_q1_ptr) .......782
4.118. TX Buffer Queue 2 Base Address Register (ETHERNETn_transmit_q2_ptr) .......784
4.119. TX Buffer Queue 3 Base Address Register (ETHERNETn_transmit_q3_ptr) .......786
4.120. RX Buffer Queue 1 Base Address Register (ETHERNETn_receive_q1_ptr)........788
4.121. RX Buffer Queue 2 Base Address Register (ETHERNETn_receive_q2_ptr)........790
4.122. RX Buffer Queue 3 Base Address Register (ETHERNETn_receive_q3_ptr)........792
4.123. RX Buffer Size Queue i Register (ETHERNETn_rxbuf_size_qi) (i=1 to 3) ...........794
4.124. CBS Control Register (ETHERNETn_cbs_control) ..............................................796
4.125. CBS IdleSlope Queue A Register (ETHERNETn_cbs_idleslope_q_a) .................798
4.126. CBS IdleSlope Queue B Register (ETHERNETn_cbs_idleslope_q_b).................799
4.127. MSB Buffer Queue Base Address Register
(ETHERNETn_msb_buff_q_base_addr_reg) .......................................................800
4.128. TX BD Control Register (ETHERNETn_tx_bd_control) ........................................801
4.129. RX BD Control Register (ETHERNETn_rx_bd_control) .......................................803
4.130. Screening Type 1 Register i (ETHERNETn_screening_type_1_register_i) (i=0 to
15) ........................................................................................................................805
4.131. Screening Type 2 Register i (ETHERNETn_screening_type_2_register_i) (i=0 to
15) ........................................................................................................................807
4.132. Interrupt Enable Queue i Register (ETHERNETn_int_enable_qi) (i=1 to 3) .........809
4.133. Interrupt Disable Queue i Register (ETHERNETn_int_disable_qi) (i=1 to 3)........ 811
4.134. Interrupt Mask Queue i Register (ETHERNETn_int_mask_qi) (i=1 to 3) ..............813
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14 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.135. EtherType 2 Register i (ETHERNETn_screening_type_2_ethertype_reg_i) (i=0 to
7) ..........................................................................................................................816
4.136. Type2 Compare Word 0 i Register (ETHERNETn_type2_compare_i_word_0)
(i=0 to 31) .............................................................................................................817
4.137. Type2 Compare Word 1 i Register (ETHERNETn_type2_compare_i_word_1)
(i=0 to 31) .............................................................................................................818
5. Functional Limitations.........................................................................................................820
5.1. The interrupts on the pause frame reception........................................................820
5.2. Priority Flow Control - pausing the transmitting the frames ..................................820
5.3. Priority Queuing - screening using DS/TC field in IP header ................................820
5.4. Priority Queuing - screening using compare_offset = "10" or "11" ........................820
5.5. Enable/Disable the partial store and forward mode ..............................................820
5.6. PTP - single step time stamping...........................................................................820
5.7. PTP/gPTP - The ptp_sync_frame_transmitted interrupt .......................................820
5.8. PTP/gPTP - TSU timer comparison with 0............................................................821
CHAPTER 22: Media Local Bus Interface (MediaLB)........................................................................822
1. Overview ............................................................................................................................823
2. Configuration and Block Diagram.......................................................................................825
3. Operation of the MediaLB...................................................................................................830
3.1. Notes on Using MediaLB......................................................................................830
3.2. List of References.................................................................................................830
4. Registers ............................................................................................................................831
4.1. MediaLBn Device Control Configuration Register (MLBn_DCCR) .......................837
4.2. MediaLBn System Status Configuration Register (MLBn_SSCR) ........................841
4.3. MediaLBn System Data Configuration Register (MLBn_SDCR) ..........................844
4.4. MediaLBn System Mask Configuration Register (MLBn_SMCR) .........................845
4.5. MediaLBn Version Control Configuration Register (MLBn_VCCR).......................848
4.6. MediaLBn Synchronous Base Address Configuration Register (MLBn_SBCR) ...850
4.7. MediaLBn Asynchronous Base Address Configuration Register (MLBn_ABCR)
.............................................................................................................................852
4.8. MediaLBn Control Base Address Configuration Register (MLBn_CBCR) ............854
4.9. MediaLBn Isochronous Base Address Configuration Register (MLBn_IBCR) ......856
4.10. MediaLBn Channel Interrupt Configuration Register (MLBn_CICR).....................858
4.11. MediaLBn AHB Master Control Register (MLBn_AHBMCTL)...............................860
4.12. MediaLBn Channel Entry Configuration Register (MLBn_CECR0 -
MLBn_CECR15)...................................................................................................861
4.13. MediaLBn Channel Status Configuration Register (MLBn_CSCR0 -
MLBn_CSCR15)...................................................................................................865
4.14. MediaLBn Channel Current Buffer Configuration Register (MLBn_CCBCR0 -
MLBn_CCBCR15) ................................................................................................871
4.15. MediaLBn Channel Next Buffer Configuration Register (MLBn_CNBCR0 -
MLBn_CNBCR15) ................................................................................................873
4.16. MediaLBn Local Channel Buffer Configuration Register (MLBn_LCBCR0 -
MLBn_LCBCR15).................................................................................................875
4.17. MediaLBn Module Identification Register (MLBn_MID) ........................................877
CHAPTER 23: Stereo Audio DAC......................................................................................................878
1. Overview ............................................................................................................................879
2. Configuration and Block Diagram.......................................................................................879
Table of Contents
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 15
3. Operation............................................................................................................................880
3.1. Initialization...........................................................................................................880
3.2. Using DMA Transfers to Update DADR Register..................................................881
3.3. Output Data Values of the Analog DAC ................................................................881
3.4. Switching Clock Frequencies of the Analog DAC .................................................882
3.5. Minimum Writing Interval between the DAOSR and DACR Registers..................882
3.6. Interrupt ................................................................................................................882
3.7. AHB Slave Interface .............................................................................................883
3.8. FIFO .....................................................................................................................883
3.9. Frequency of CLKPI and CLKDA .........................................................................884
3.10. Sampling Frequency and Oversampling Setting of D/A Converter .......................884
3.11. Output Stop Control of Analog DAC .....................................................................886
3.12. Bridge-tied Load (BTL) .........................................................................................886
4. Registers ............................................................................................................................887
4.1. DAC Over Sampling Register(DAOSR)................................................................887
4.2. DAC Configuration (DACR) ..................................................................................889
4.3. DAC BUSY Register(DABUSY)............................................................................891
4.4. DAC Control Register(DACTRL) ..........................................................................893
4.5. DAC FLUSH Register(DAFLUSH)........................................................................895
4.6. Interrupt Enable Register(INTREN) ......................................................................897
4.7. Interrupt State Register (INTRSTAT) ....................................................................899
4.8. Interrupt Clear Register (INTCTR)........................................................................901
4.9. DAC Polarity Configuration Register (DPCR).......................................................903
4.10. Data 0..15 Register (DADR) .................................................................................905
CHAPTER 24: Inter-IC Sound (I2S)...................................................................................................906
1. Overview ............................................................................................................................907
2. Configuration and Block Diagram.......................................................................................908
3. Operations of the I2S..........................................................................................................909
3.1. I2S Frame Construction........................................................................................909
3.2. I2S Configuration and Operation Modes .............................................................. 911
3.3. Bit Alignment ........................................................................................................917
3.4. FIFO Construction ................................................................................................919
3.5. Caution Summary.................................................................................................922
4. Registers ............................................................................................................................923
4.1. Reception FIFO Data Register (I2Sn_RXFDAT0 to 15)........................................926
4.2. Transmission FIFO Data Register (I2Sn_TXFDAT0 to 15) ...................................928
4.3. Control Register (I2Sn_CNTREG)........................................................................929
4.4. Channel Control Register 0 (I2Sn_MCR0REG)....................................................934
4.5. Channel Control Register 1 (I2Sn_MCR1REG)....................................................938
4.6. Channel Control Register 2 (I2Sn_MCR2REG)....................................................939
4.7. Operation Control Register (I2Sn_OPRREG).......................................................940
4.8. Software Reset Register (I2Sn_SRST) ................................................................942
4.9. Interrupt Control Register (I2Sn_INTCNT) ...........................................................943
4.10. Status Register (I2Sn_STATUS)...........................................................................947
4.11. DMA Activate Register (I2Sn_DMAACT) ..............................................................951
4.12. Debug Register (I2Sn_DEBUG) ...........................................................................953
4.13. Module ID Register (I2Sn_MIDREG)....................................................................955
Table of Contents
16 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
CHAPTER 25: Programmable CRC...................................................................................................956
1. Overview ............................................................................................................................957
2. Configuration and Block Diagram.......................................................................................958
3. Operation of the Programmable CRC.................................................................................958
3.1. CRC Operation Flowcharts...................................................................................958
3.2. CRC Input Data and Checksum Calculation Flow ................................................962
3.3. CRC Calculation Example ....................................................................................965
4. Registers ............................................................................................................................966
4.1. CRC Polynomial Register (CRCn_POLY).............................................................967
4.2. CRC Seed Register (CRCn_SEED) .....................................................................968
4.3. CRC Final XOR Register (CRCn_FXOR).............................................................969
4.4. CRC Configuration Register (CRCn_CFG) ..........................................................970
4.5. CRC Write Register (CRCn_WR) .........................................................................973
4.6. CRC Read Register (CRCn_RD)..........................................................................974
CHAPTER 26: PCMPWM..................................................................................................................975
1. Overview ............................................................................................................................976
2. Configuration and Block Diagram.......................................................................................977
2.1. Block Diagram ......................................................................................................977
2.2. Configuration of the PCMPWM Module................................................................978
2.3. Output Configuration ............................................................................................982
3. Operation of the PCMPWM................................................................................................983
3.1. Description of the PCM to PWM Conversion Process ..........................................983
3.2. PWM Cycle Time Configuration............................................................................988
3.3. PCM Data Sample Input.......................................................................................988
3.4. Interrupts ..............................................................................................................989
3.5. Dead Timer Operation ..........................................................................................989
4. Registers ............................................................................................................................990
4.1. PCMPWM Control Register (PCMPWMi_CONTROL)..........................................991
4.2. PCMPWM Output Control Register (PCMPWMi_OCTRL) ...................................994
4.3. PCMPWM Clock Select Register (PCMPWMi_CLKSEL) .....................................996
4.4. PCMPWM Count Period Register (PCMPWMi_COUNTP)...................................997
4.5. PCM Offset Register (PCMPWMi_PCMOFFS) ....................................................998
4.6. PCM Interrupt Enable Register (PCMPWMi_INTREN).........................................999
4.7. PCM Interrupt Status Register (PCMPWMi_INTRSTAT) ....................................1001
4.8. PCM Interrupt Clear Register (PCMPWMi_INTRCLR).......................................1003
4.9. PCM Data Register 0..15 (PCMPWMi_DATA)....................................................1005
CHAPTER 27: HyperBus Interface ..................................................................................................1006
1. Overview ..........................................................................................................................1007
2. Block Diagram..................................................................................................................1007
3. Operation of the HYPERBUSI..........................................................................................1008
3.1. HyperBus Core...................................................................................................1008
3.2. Tx/Rx Controller.................................................................................................. 1011
3.3. C/A Coder...........................................................................................................1012
3.4. FIFO ...................................................................................................................1013
3.5. CS REG (Control Status Register) .....................................................................1014
3.6. AXI Slave Interface.............................................................................................1015
4. Registers ..........................................................................................................................1016
4.1. Controller Status Register (HYPERBUSIn_CSR) ...............................................1017
Table of Contents
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 17
4.2. Interrupt Enable Register (HYPERBUSIn_IEN)..................................................1020
4.3. Interrupt Status Register (HYPERBUSIn_ISR)...................................................1022
4.4. Memory Base Address Register (HYPERBUSIn_MBR0 to 1) ............................1024
4.5. Memory Configuration Register (HYPERBUSIn_MCR0 to 1).............................1025
4.6. Memory Timing Register (HYPERBUSIn_MTR0 to 1) ........................................1027
4.7. General Purpose Output Register (HYPERBUSIn_GPOR)................................1030
4.8. Write Protection Register (HYPERBUSIn_WPR) ...............................................1031
4.9. Test Register (HYPERBUSIn_TEST) .................................................................1032
CHAPTER 28: LCD Controller .........................................................................................................1033
1. Overview ..........................................................................................................................1034
2. Features ...........................................................................................................................1035
3. Configuration....................................................................................................................1036
4. Operation..........................................................................................................................1037
4.1. Operation of LCD Controller/Driver (LCDC) .......................................................1037
4.2. 1/2 Duty Output Waveform .................................................................................1039
4.3. 1/3 Duty Output Waveform.................................................................................1042
4.4. 1/4 Duty Output Waveform .................................................................................1045
4.5. Static Drive Output Waveform............................................................................1048
5. Setting..............................................................................................................................1051
6. Registers ..........................................................................................................................1053
6.1. LCD Control Register 0: LCR0 ...........................................................................1054
6.2. Data Memory for Display: VRAM........................................................................1056
6.3. LCDC Control Register 1: LCR1.........................................................................1058
6.4. Common Pin Switching Register: LCDCMR.......................................................1059
6.5. LCDC Static Control Register: LCRS .................................................................1060
6.6. Static LCD Display Data Register: LDR..............................................................1062
6.7. Key Code Register: LCD_KEYCDR ...................................................................1064
6.8. Segment Output Register: SEGER.....................................................................1067
6.9. Common Output V Pin Control Register: COMVER ...........................................1068
7. Q&A..................................................................................................................................1070
7.1. How can I Set Pins to COM Output Pins or SEG Output Pins?..........................1071
7.2. How to Set VRAM?.............................................................................................1073
7.3. How can I Setting the Frame Cycle? ..................................................................1074
7.4. How can I Set the Bias? .....................................................................................1075
7.5. How can I Set the Duty?.....................................................................................1075
7.6. How can I Control the LCD Operation Start/Stop? .............................................1075
7.7. How can I Execute/Cancel the Display?.............................................................1076
7.8. How can I Display during the PSS Timer Mode (Main Oscillation Operation/ Sub
Oscillation Operation)? .......................................................................................1077
7.9. How can I Select either Internal or External for the Division Resistor?...............1078
7.10. How can I Select Pin of V3 Voltage? ..................................................................1078
7.11. How can I Select either Internal or External for the Division Resistor?...............1079
7.12. How can I Adjust the Brightness When the Internal Division Resistor is Used?
...........................................................................................................................1080
7.13. How can I Block the Current with the External Division Resistor When the LCD
Stops? ................................................................................................................1080
7.14. How can I Display/Non-display the LCD with Static Drive (ST0 to ST8)?...........1081
8. Sample Program...............................................................................................................1082
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18 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
9. Notes................................................................................................................................1089
CHAPTER 29: Indicator PWM .........................................................................................................1090
1. Overview ..........................................................................................................................1091
2. Configuration and Block Diagram.....................................................................................1091
3. Operation of Indicator PWM .............................................................................................1092
3.1. Indicator PWM Timer ..........................................................................................1092
3.2. PWM Timer Count Operation Start.....................................................................1093
3.3. Timer Count Operation Stop...............................................................................1094
3.4. Counter Value Updating while PWM Counter Operation is in Progress..............1095
3.5. Indicator PWM Interrupts....................................................................................1096
3.6. Operation Flowchart ...........................................................................................1098
4. Registers ..........................................................................................................................1100
4.1. Timer Control Register (ITMCR)......................................................................... 1101
4.2. Count Control Register (ICNTCR) ...................................................................... 1104
4.3. Status Control Register (ISTC)........................................................................... 1106
4.4. Status Control Clear Register (ISTCC)............................................................... 1108
4.5. Status Control Set Register (ISTCS) ...................................................................1110
4.6. PWM Cycle Setting Register (IPCSR) .................................................................1112
4.7. PWM Duty Setting Register (IPDUT)...................................................................1113
5. Precautions for Using This Device....................................................................................1115
5.1. Notes to Observe When Accessing a Register....................................................1115
5.2. Indicator PWM Operation Precautions ................................................................1115
CHAPTER 30: FPD-Link Converter .................................................................................................1116
1. Overview ..........................................................................................................................1117
2. Configuration and Block Diagram.....................................................................................1117
3. Operation..........................................................................................................................1119
3.1. Register IF...........................................................................................................1119
3.2. Output Signal Selection for FPD-Link..................................................................1119
3.3. FPD-Link Control ................................................................................................ 1120
3.4. Power ON/Power DOWN Sequence .................................................................. 1120
4. Registers ..........................................................................................................................1122
4.1. Unlock Registers (UNLOCK) .............................................................................. 1123
4.2. Control0 Registers (CTRL0) ............................................................................... 1125
4.3. Control1 Registers (CTRL1) ............................................................................... 1127
4.4. Channel Select Registers (CH_SEL).................................................................. 1130
4.5. TXn Configuration Registers (TXn_CONF (n: 0 to 4)) ........................................ 1131
4.6. GDC Control Register (GDCCR) ........................................................................ 1133
CHAPTER 31: Memory Protection Unit for AXI................................................................................1135
1. Overview ..........................................................................................................................1136
2. Configuration and Block Diagram.....................................................................................1137
3. Operation of the MPU AXI................................................................................................1138
4. Registers ..........................................................................................................................1144
4.1. MPU AXI Control Register (MPUXn_CTRL0) ..................................................... 1147
4.2. MPU AXI NMI Enable Register (MPUXn_NMIEN).............................................. 1149
4.3. MPU AXI Write Error Control Register (MPUXn_WERRC)................................. 1150
4.4. MPU AXI Write Error Address Register (MPUXn_WERRA)................................ 1151
4.5. MPU AXI Read Error Control Register (MPUXn_RERRC) ................................. 1152
4.6. MPU AXI Read Error Address Register (MPUXn_RERRA) ................................ 1153
Table of Contents
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 19
4.7. MPU AXI Region Control Registers (MPUXn_CTRL1 to 8) ................................ 1154
4.8. MPU AXI Start Address Registers (MPUXn_SADDR1 to 8) ............................... 1155
4.9. MPU AXI End Address Registers (MPUXn_EADDR1 to 8) ................................ 1156
4.10. MPU AXI Unlock Register (MPUXn_UNLOCK) .................................................. 1157
4.11. MPU AXI Module ID Register (MPUXn_MID) ..................................................... 1158
5. Notes on Using MPU AXI .................................................................................................1159
CHAPTER 32: Memory Protection Unit for AHB..............................................................................1161
1. Overview ..........................................................................................................................1162
2. Configuration and Block Diagram.....................................................................................1163
3. Operation of the MPU AHB...............................................................................................1164
4. Registers ..........................................................................................................................1168
4.1. MPU AHB Control Register (MPUHn_CTRL0) ................................................... 1171
4.2. MPU AHB NMI Enable Register (MPUHn_NMIEN) ............................................ 1173
4.3. MPU AHB Memory Error Control Register (MPUHn_MERRC)........................... 1174
4.4. MPU AHB Memory Error Address Register (MPUHn_MERRA) ......................... 1175
4.5. MPU AHB Region Control Registers (MPUHn_CTRL1 to 8) .............................. 1176
4.6. MPU AHB Start Address Registers (MPUHn_SADDR1 to 8) ............................. 1177
4.7. MPU AHB End Address Registers (MPUHn_EADDR1 to 8)............................... 1178
4.8. MPU AHB Unlock Register (MPUHn_UNLOCK) ................................................ 1179
4.9. MPU AHB Module ID Register (MPUHn_MID) ................................................... 1180
5. Notes on Using the MPU AHB..........................................................................................1181
CHAPTER 33: Graphics Subsystem................................................................................................1184
1. Overview ..........................................................................................................................1185
1.1. Feature Summary............................................................................................... 1185
2. Configuration and Block Diagram.....................................................................................1186
2.1. Block Diagrams .................................................................................................. 1186
2.2. The 3D Graphics Core........................................................................................ 1187
2.3. The 2D Graphics Core........................................................................................ 1187
2.4. High Performance Bus Matrix............................................................................. 1187
2.5. Memory Protection Units ( MPU ) ....................................................................... 1187
2.6. Bus Monitor ........................................................................................................ 1187
2.7. Video RAM ......................................................................................................... 1188
2.8. DDR High-Speed SPI ......................................................................................... 1188
2.9. HyperBus[TM] Interface ........................................................................................ 1188
2.10. Interrupts ............................................................................................................ 1189
2.11. Address Map ...................................................................................................... 1191
2.12. Key Codes.......................................................................................................... 1192
3. Operation of the Graphics Subsystem..............................................................................1193
3.1. Common Setup................................................................................................... 1193
3.2. The 2D Graphics Core / 3D Graphics Core Display Setup ................................. 1199
4. Registers ..........................................................................................................................1203
4.1. General...............................................................................................................1203
4.2. SubSysCtrl .........................................................................................................1207
4.3. Memory Protection Unit ......................................................................................1285
4.4. High Performance Bus Matrix.............................................................................1286
4.5. Bus Monitor ........................................................................................................1287
5. References.......................................................................................................................1296
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