Denon DVD-310 User manual

SERVICE MANUAL
MODEL DVD-310
DVD VIDEO PLAYER
For Japan model
16-11, YUSHIMA 3-CHOME, BUNKYOU-KU, TOKYO 113-0034 JAPAN
S-1129V.01 DE/CDM 0307
注 意
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
● 本機の仕様は性能改良のため、予告なく変更すること
があります。
● 補修用性能部品の保有期間は、製造打切後 8年です。
Some illustrations using in this service manual are
slightly different from the actual set.
●
●
Please use this service manual with referring to
the operating instructions without fail.
●
For purposes of improvement, specifications and
design are subject to change without notice.
●
修理の際は､必ず取扱説明書を参照の上、作業を行って,
ください。
● 本文中に使用しているイラストは、説明の都合上現物
と多少異なる場合があります。
Ver. 1

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2
DVD-310
SAFETY PRECAUTIONS
Thefollowingcheckshouldbeperformedforthecontinuedprotectionofthecustomerandservicetechnician.
LEAKAGE CURRENT CHECK
Beforereturningtheunittothecustomer,makesureyoumakeeither(1)aleakagecurrentcheckor(2)alinetochassis
resistancecheck.Iftheleakagecurrentexceeds0.5milliamps,oriftheresistancefromchassistoeithersideofthe
powercordislessthan460kohms,theunitisdefective.
LASER RADIATION
Donotstareintobeamorviewdirectlywithopticalinstruments,class3Alaserproduct.
(1)
(2)
500V
1M
(1)
(2)

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3
DVD-310
BLOCK DIAGRAM

4
4
DVD-310
半導体一覧表
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
主な半導体を記載しています。汎用の半導体は記載を省略しています。
●IC's
Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
注): IC No. の前の記号は、基板の名称を表します。
AV: A/V P.W.B. ME: MECHA P.W.B.
FR: FRONT P.W.B. SM: SMPS P.W.B.
ES6028FW (ME: U9)
FunctionI/OPin No. Pin Name
ES6038 Terminal Function
1, 18, 27, 59,
68, 75, 92, 99,
104, 130, 148, VEE I I/O power supply.
157, 159, 164,
183, 193, 201
8, 17, 26, 34,
43, 52, 60, 67,
76, 84, 91, 98,
103, 112, 120, VSS I Ground.
129, 138, 147,
156, 163, 171,
177, 184, 192,
200, 208
23:19, 16:10,
7:2, 207:204 LA[21:0] O Device address output.
9, 35, 44, 83,
121, 139, 172 VCC I Core power supply.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VEE
LA4 LA5 LA6 LA7 LA8 LA9
VSS
VCC
LA10 LA11 LA12 LA13 LA14 LA15 LA16
VSS VEE
LA17 LA18 LA19 LA20 LA21
RESET#
TDMDX
VSS VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2 TSD3
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
VSS
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
VEE
VSS
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
VSS
VEE
DCAS#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
VEE
VSS
DB0
DB1
DB2
DB3
DB4
DB5
VCC
VSS
DB6
DB7
DB8
DB9
DB10
DB11
VSS
VEE
DB12
DB13
DB14
DB15
DCS1#
VSS
VEE
DCS0#
DQM
DSCK
VSS
VEE
VSS HA1 HA0 HCS3FX# HCS1FX# HIOCS16# HRD# HWR# VEE VSS HIORDY HRST# HIRQ HRDQ# HWRQ# HD15 HD14 VCC VSS HD13 HD12 HD11 HD10 HD9 HD8 HD7 VEE VSS HD6 HD5 HD4 HD3 HD2 HD1 HD0 VCC VSS HSYNC# VSYNC# PCLKQSCN PCLK2XSCN YUV7 YUV6 YUV5 VSS ADVEE YUV4 YUV3 YUV2 YUV1 YUV0 DCLK
VSS
LA3
LA2
LA1
LA0
CAMIN1
CAMIN0
VEE
VSS
LWRHL#
LWRLL#
LD15
LD14
LD13
LD12
VEE
VSS
LD11
LD10
LD9
LD8
LD7
LD6
LD5
VSS
VEE
LD4
LD3
LD2
LD1
LD0
VSS
LCS3#
LCS2#
LCS1#
LCS0#
VCC
VSS
LOE#
AUX[7]
AUX[6]
AUX[5]
AUX[4]
AUX[3]
VEE
VSS
AUX[2]
AUX[1]
AUX[0]
VEE
HA2
VEE

5
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DVD-310
24 RESET# I Reset input, active low.
25 TDMDX O TDM transmit data.
28 TDMDR I TDM receive data.
29 TDMCLK I TDM clock input.
30 TDMFS I TDM frame sync.
31 TDMTSC# O TDM output enable.
TWS O Audio transmit frame sync.
SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type
0 0 0 VCO off.
0 0 1 DCLK
32 0 1 0 Bypass mode
0 1 1 DCLK x 2
1 0 0 DCLK x 4.5
1 0 1 DCLK x 3
1 1 0 DCLK x 3.5z
1 1 1 DCLK x 4
33 TSD0 O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.
36 TSD1 O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.
37 TSD[2] O Audio transmit serial data output 2.
38 TSD[3] O Audio transmit serial data output 3.
39 MCLK I/O Audio master clock for audio DAC.
40 TBCK O Audio transmit bit clock.
SPDIF O S/PDIF output.
SEL_PLL3 I Clock source select.
41 SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
42,48 NC No connect pins. Leave open.
45 RSD I Audio receive serial data.
46 RWS I Audio receive frame sync.
47 RBCK I Audio receive bit clock.
49 XIN I Crystal input.
50 XOUT O Crystal output.
51 AVEE I Analog power for PLL.
66:61, 58:53 DMA[11:0] O DRAM address bus [11:0]
69 DCAS# O DRAM column address strobe,
70 DSCK_EN O DRAM clock enable.
71 DWE# O DRAM write enable.
72 DRAS# O DRAM row address strobe.
73 DMBS0 O SDRAM bank select 0.
74 DMBS1 O SDRAM bank select 1.
96:93, 90:85,
82:77 DB[15:0] I/O DRAM data bus [15:0]
97, 100 DCS[1:0]# O SDRAM chip select [1:0]
101 DQM O Data input/output mask.
102 DSCK O Output clock to SDRAM.
105 DCLK I 27 MHz clock input to PLL.
106 UDAC OVideo UDAC output.
107 VREF I Internal voltage to video DAC.
108 CDAC OVideo CDAC output.
109 COMP I Compensation input.
110 RSET I DAC current adjustment resistor input.
111 ADVEE I Analog power for video DAC.
113 YDAC OVideo YDAC output.
FunctionI/O
Pin No. Pin Name

6
6
DVD-310
114 VDAC OVideo VDAC output.
115 YUV7 O YUV7 pixel output data.
116 PCLK2XSCN I/O 27 MHz video output pixel clock.
117 PCLKQSCN O 13.5 MHz video output pixel clock.
118 VSYNC# I/O Vertical sync, active low.
119 HSYNC# I/O Horizontal sync, active low.
127:122 HD[5:0] I/O Host data I/O [5:0].
128 HD[6] I/O Host data I/O [6].
131 HD[7] I/O Host data I/O [7].
132 HD[8] I/O Host data bus 8.
133 HD[9] I/O Host data bus line 9.
134 HD[10] I/O Host data bus line 10.
135 HD[11] I/O Host data bus line 11.
136 HD[12] I/O Host data bus line 12.
137 HD[13] I/O Host data bus line 13.
140 HD[14] I/O Host data bus line 14.
141 HD[15] I/O Host data bus line 15.
142 HWRQ# O Host write request.
143 HRRQ# O Host read request.
144 HIRQ I/O Host interrupt.
145 HRST# O Host reset.
146 HIORDY I Host I/O ready.
149 HWR# I/O Host write.
150 HRD# O Host read.
151 HIOCS16# I Device16-bit data transfer.
152 HCS1FX# O Host select 1.
153 HCS3FX# O Host select 3.
158, 155:154 HA[2:0] I/O Host address bus.
160 AUX[0] O I2C DATA.
162 AUX[2] I/O Auxiliary ports 2.
165 AUX[3] I/O Auxiliary ports 3.
169:166 AUX[7:3] I/O Auxiliary ports 7:3.
170 LOE# O Device output enable.
176:173 LCS[3:0]# O Chip select [3:0].
197:194,
191:185, LD[15:0] I/O EPROM device data bus.
182:178
198 LWRLL# O Device low-byte write enable.
199 LWRHL# O Device high-byte write enable.
202 CAMIN0 I Camera YUV 0.
203 CAMIN1 I Camera YUV 1.
FunctionI/O
Pin No. Pin Name
161AUX[1]OI2C CLK.

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DVD-310
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AVSS-DS
XSRFIN
XSIPIN
AVDD5-DS
XSDSSLV
XSRSLINT
VDD
XSAWRC
XSRFGC
XSEFGC
XSFOCUS
XSTRACK
XSSLEG
AVDD5-DA
XSMOTOR
AVSS-DA
XSRFRPLP
XSTELP
XSVREF2
XSRFRP
XSTEXI
AVSS-AD
XSTEI
XSFEI
XSAEI
AVDD5-AD
XSSBAD
GND
XSDFCT
XSCSJ
XSCLK
XSDATA
XSLDC
XSFGIN
XSSPDON
XSFLAG(3)
XSFLAG(2)
XSFLAG(1)
XSFLAG(0)
XMP1_7
XMP1_6
GND
NC
XMP1_4
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
XRD(3)
XRD(12)
GND
XRD(2)
XRD(13)
XRD(1)
XRD(14)
XRD(0)
XRD(15)
XHD(7)
XHD(8)
XHD(6)
XHD(9)
XHD(5)
XHD(10)
XHD(4)
XHD(11)
VDD
XHD(3)
XHD(12)
XHD(2)
XHD(13)
GND
XHD(1)
XHD(14)
XHD(0)
XHD(15)
XHDRQ
XHIOWJ
XHIORJ
XHIORDY
XHDACKJ
XHINT
XHCS16J
XHA(1)
XHPDIAGJ
XHA(0)
XHA(2)
XHCS1J
XHCS3J
XHDASPJ
XMA(15)
XMA(14)
XMA(13)
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
XMP1_3
XMFSCSJ
XMP1_2
XGPIO(2)
XMP1_1
XMRSTJ
XGPO(1) XGPO(0)
XCRSTJ
XMPSENJ
VDD
XMALE
XMP1_0
VDD
XOSC1 XOSC2
GND
XMD(0) XMD(1) XMD(2) XMD(3) XMD(4) XMD(5) XMD(6) XMD(7)
XMCSJ
XMRDJ
XMWRJ
XMINT1J
XMA(11) XMA(10)
VDD
XMA(9) XMA(8) XMA(7) XMA(6) XMA(5) XMA(4) XMA(3) XMA(2) XMA(1) XMA(0)
XMA(12)
GND
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
XSAWRCVCO XSVREFO XSPDOFTR2 XSVR_PLL XSFTROPI XSFDO AVSS_PL XSPLLFTR2 AVDD5_PL XSFDIREF XSPDIREF GND XTSLRF XTPLCK VDD XRA(3) XRA(2) XRA(1) XRA(0) XRA(4) XRA(5) XRA(6) GND XRA(7) XRA(10) XRA(11) VDD XRA(8) XRA(9) XROEJ VDD XRCASJ XRRASJ XRSDCLK XRWEJ XRD(7) XRD(8) XRD(6) GND XRD(9) XRD(5) XRD(10) XRD(4) XRD(11)
Data
Separator
ATAPI
&
MPEG
I/F
Digital
Servo
DVD-DSP RAM
Arbiter
Target
Search
ROM
C3 ECC
EDC
MPEG
DEC.
Motor
Driver
PC
4M DRAM
CD-DSP MCU
M
M5705
M5705 Terminal Function
M5705 (ME:U1)
DescriptionPin No. Pin Name Type
2 XSRFIN I/A Analog RF signal input after passing through the equalizer
3 XSIPIN I/A Inverting input pin of data slicer
5 XSDSSLV O/A Slice level output pin
6 XSRSLINT I/A Reference current setting pin for analog data slicer
8 XSAWRC O/A Output for enlarge VCO range. Analog output from DAC buffer
9 XSRFGC O/A RF gain control output
10 XSEFGC O/A E,F gain control output
11 XSFOCUS O/A Output voltage level for focusing buffer IC
12 XSTRACK O/A Output voltage level for tracking buffer IC
13 XSSLEG O/A Output voltage level for sledge buffer IC
15 XSMOTOR O/A Output voltage level for spindle motor buffer IC
17 XSRFRPLP I/A High bandwidth low pass filter input for RFRP
18 XSTELP I/A High bandwidth low pass filter input for TE
19 XSVREF2 I/A 2.1V reference voltage input
20 XSRFRP I/A RF ripple/envelope signal input
21 XSTEXI I/A Tracking zero crossing input signal
23 XSTEI I/A Tracking error input signal
24 XSFEI I/A Focus error input signal
25 XSCEI I/A 1. Center error input signal
2. Photo Interrupt input

8
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DVD-310
DescriptionPin No. Pin Name Type
27 XSSBAD I/A Sub-beam addition signal input
166 XSPDIREF I/A Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
167 XSFDIREF I/A Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
169 XSPLLFTR2 I/A Data PLL loop filter pin#2
171 XSFDO O/A Output node of frequency detector charge pump circuit
172 XSFTROPI I/A Input node of loop filter OP circuit
173 XSVR_PLL I/A PLL reference voltage input
174 XSPDOFTR2 I/A Phase detector filter pin#1
175 XSVREFO O/A Reference voltage output
176 XSAWRCVCO I/A Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
29 XSDFCT I Detect detection signal input
30 XSCSJ O Chip select signal for accessing control registers
31 XSCLK O Clock output for accessing control registers
32 XSDATA I/O Registers data input/output pin
33 XSLDC O Laser diode on/off control output for both CD/DVD
34 XSFGIN I Motor Hall sensor input
35 XSSPDON O Spindle motor on output
36, 37, 38, 39 XSFLAG[3:0] O These pins are used to monitor some status of servo control block
48, 51, 52 XGPIO[2:0] I/O 1. These pins are used as general purpose I/O bus
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
40 XMP1_7 I/O Internal microcontroller programmable I/O port 1.7.
41 XMP1_6 I/O Internal microcontroller programmable I/O port 1.6.
43 XMP1_5 I/O This pin is now changed to be NC.
44 XMP1_4 I/O Internal microcontroller programmable I/O port 1.4.
45 XMP1_3 I/O Internal microcontroller programmable I/O port 1.3.
47 XMP1_2 I/O Internal microcontroller programmable I/O port 1.2.
49 XMP1_1 I/O Internal microcontroller programmable I/O port 1.1.
57 XMP1_0 I/O Internal microcontroller programmable I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16)
46 XMFSCSJ I/O Output chip select connected to external flash ROM chip enable pin
54 XMPSENJ I/O Output program store enable connected to external ROM PSENJ pin.
56 XMALE I/O This signal is used as address latch signal in address/data mux mode
70 XMCSJ I/O 1. This signal must be asserted for all microcontroller accesses to the register of this chip
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
71 XMRDJ I/O 1. This signal is used as the Read Strobe signal
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
72 XMWRJ I/O This signal is used as the Wire Strobe signal
73 XMINT1J I/O 1. This signal is an interrupt line to the microcontroller
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
74, 75, 77, 78,
XMA[15:0] I/O These pins are used as address bus
79, 80, 81, 82,
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65, XMD[7:0] I/O These pins are used as data bus for the 16-bit processor mode, or the address/data mux
66, 67, 68, 69 bus for the 8-bit processor mode.
163 XTPLCK I/O PLCK test pin
164 XTSLRF I/O SLRF test pin
59 XOSC1 I Crystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
60 XOSC2 O Crystal output
53 XCRSTJ I Chip Reset. As asserted low input generates a component reset that stops all operations within
the chip and deasserts all output signals. All input/output signals are set to input.
94 XHCS1J I This pin is used to select the command block task file registers
93 XHCS3J I This pin is used to select the control block task file registers
103 XHIORJ I Asserted by the host during a host I/O read operation
104 XHIOWJ I Asserted by the host during a host I/O write operation
105 XHDRQ O
1.
DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
2. MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
101 XHDACKJ I
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
99 XHCS16J O
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
50 XHRSTJ I Host Reset. The reset of ATA bus
100 XHINT O
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected

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DVD-310
DescriptionPin No. Pin Name Type
97 XHPDIAGJ I/O This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
92 XHDASPJ I/O This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. This pin is used for Master/Slave drive communication and/or for driving an LED
102 XHIORDY I/O
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
95, 96, 98 XHA[2:0] I Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
XHD[15.0] I/O
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
106, 107, 108, 2.
MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
109, 111, 112, 3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
113, 114, 116, bit3-0 and VCD I/F is as follow
117, 118, 119, HD0—CD-DATA
120, 121, 122, HD1—CD-LRCK
123 HD2—CD-BCK
HD3—CD-C2PO
143 XRSDCLK O This signal is the clock output for SDRAM
147 XROEJ O This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
142 XRWEJ O This signal is asserted low when a buffer memory write operation is active
144 XRRASJ O This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
145 XRCASJ O This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA[8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
148, 149, 151, 0: By registers to decide input/output
152, 153, 155, RA[6] : System test pin output
156, 157, 158, XRA[11:0] O 1: Normal operation
159, 160, 161 0: System test pin output
RA[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (internal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
124, 125, 126,
XRD[15:0] I/O These signals are the 8-bit parallel data lines to/from the buffer memory.
127, 128, 129,
131, 132, 134,
135, 136, 137,
138, 139, 140,
141
4 AVDD5_DS Analog Power +5V for Data Slicer part
14 AVDD5_DA Analog Power +5V for DAC part
26 AVDD5_AD Analog Power +5V for ADC part
168 AVDD5_PL Analog Power +5V for Data PLL part
7, 55, 58, 76,
VDD Power +3.3V for digital core logic and pad
115, 146,
150, 162
1 AVSS_DS Analog Ground for Data Slicer part
16 AVSS_DA Analog Ground for DAC part
22 AVSS_AD Analog Ground for ADC part
170 AVSS_PL Analog Ground for Data PLL part
28, 42, 61,
GND Digital Ground core logic and pad.
88, 110, 130,
138, 154, 165

10
10
DVD-310
SP3721A Terminal Function
SP3721A (ME:U2)
DescriptionPin No. Pin Name Type
1, 2 DVDREP, DVDREN I RF Signal Inputs. Differential RF signal attenuator input pins
63 CDRF I RF Signal Inputs. Single-ended RF signal attenuator input pin
59, 60 AIP, AIN I AGC Amplifier Inputs. Differential AGC amplifier input pins
53, 54 DIP, DIN I Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended output buffer
and full wave rectifier
32 FDCHG# I
Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches. A low
level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for
the MIRR bottom hold circuit. (open high)
49 HOLD1 I Hold Control. A TLL compatible control pin which, when pulled high, disables the RF AGC charge
pump and holds the RF AGC amplifier gain at its present value. (open high)
11~14 D, C, B, A I Photo Detector Interface Inputs. Inputs from the main beam Photo detector matrix outputs
5~8 A2, B2, C2, D2 I Photo Detector Interface Inputs. AC coupled inputs for the DPD from the main beam Photo
detector matrix outputs
15~16 F, E I CD tracking Error Inputs. Inputs from the CD photo detector error outputs.
3~4 PD1, PD2 I CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs
40 MEI I Mirror Envelope Inputs. The SIGO envelope input pin
35 MIN I RF signal Input for Mirror. AC coupled inputs for the mirror detection circuit from the pull-in signal
output. (PI)
21 DVDPD I APC Input. DVD APC input pin from the monitor photo diode
23 CDPD I APC Input. CD APC input pin from the monitor photo diode
25 LDON# I APC Output On/Off. APC output control pin. A low level activates the LD output. (open high)
61, 62 ATON/ATOP O Differential Attenuator Output. Attenuator outputs
51, 52 FNN, FNP O Differential Normal Output. Filter normal outputs
57 SIGO O Single Ended Normal Output. Single-ended RF output
64 CDRFDC O CD RF Signal Output. Single ended CD RF summing output
42 FE O Focusing Error Signal Output. Focus error output reference to VCI
41 TE O Tracking Error Signal Output. Tracking error output reference to VCI
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MLPF
MEVO
MIN
PI
DFT
TPH
MEV
MEI
TE
FE
CE
LCN
LCP
SCLK
SDATA
SDEN
E
F
A
B
C
D
CN
CP
D2
C2
B2
A2
PD2
PD1
DVDRFN
DVDRFP
32313029282726252423222120191817
49505152535455565758596061626364
HOLD1 VNA FNN FNP DIP DIN RX BYP SIGO VPA AIP AIN ATON ATOP CDRF CDRDDC
FDCHG#
VIB VIP
VIIRR
VPB
VCI
VC
LDON#
CDLD
CDPD
DVDLD
DVDPD
VNB
NC
VCI2
CDTE
TOP VIEW

11
11
DVD-310
DescriptionPin No. Pin Name Type
43 CE O Center Error Signal Output. Center error output reference to VCI
34 NEVO O SIGO Bottom Envelope Output. Bottom envelope for mirror detection
37 DFT O Defect Output. Pseudo CMOS output. When a defect is detected, the DFT output goes high. Also
the servo AGC output can be monitored at this pin, when CAR bits 7-4 are ‘0011’
29 MIRR O Mirror Detect Output. Mirror Detect comparator output. Pseudo CMOS output
36 PI O Pull-in Signal Output. The summing signal output of A, B, C, D or PD1, PD2 for mirror detection.
Reference to VCI
22 DVDLD O APC output. DVD APC output pin to control the laser power
24 CDLD O APC output. CD APC output pin to control the laser power
56 BYP I/O The RF AGC integration capacitor CBYP, is connected between BYP and VPA
9 CP I/O Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CN pin
10 CN I/O Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CP pin
45 LCP — Center Error LPF pin. An external capacitance is connected between this pin and the LCN pin
44 LCN — Center Error LPF pin. An external capacitance is connected between this pin and the LCP pin
30 MP — MIRR signal Peak hold pin. An external capacitance is connected to between this pin and VPB
31 MB — MIRR signal Bottom hold pin. An external capacitance is connected to between this pin and VPB
39 MEV — Sigo Bottom Envelope pin. An external capacitance is connected to between this pin and VPB
17 CDTE — CD Tracking. E-F Opamp output for feedback
38 TPH — PI Top Hold pin. An external capacitance is connected to between this pin and VPB
26 VC — Reference Voltage output. This pin provides the internal DC bias reference voltage (+2.5V lix).
Output Impedance is less than 50ohms
27 VCI — Reference Voltage input. DC bias voltage input for the servo input reference
18 VCI2 — Reference Voltage input. DC bias voltage input for the servo input reference
55 RX — Reference Resistor Input. An external 8.2kohm, 1% resistor is connected from this pin to ground
to establish a precise PTAT (proportional to absolute temperature) reference current for the filter
33 MLPF — MIRR signal LPF pin. An external capacitance is connected between this pin and VPB
19 NC — No Connect
48 SDEN I Serial Data Enable. Serial Enable CMOS input. A high level input enable the serial port (Not to be
left open)
47 SDATA I/O Serial Data. Serial data bi-directional CMOS pin. NRZ programming data for the internal registers
is applied to this input ( Not to be left open)
46 SCLK I Serial Clock. Serial Clock CMOS input. The clock applied to this pin is synchronized with the data
applied to SDATA (Not to be left open)
58 VPA Power. Power supply pin for the RF block and serial port
28 VPB Power. Power supply pin for the servo block
50 VNA Ground. Ground pin for the RF block and serial port
20 VNB Ground. Ground pin for the servo bolck

12
12
DVD-310
GMS87C2020Q (FR: IC91)
BLOCK DIAGRAM
ALU
Interrupt Controller
Data Memory
8-bit
ADC
8-bit
Counter
Timer/
Program
Memory
Data Table
PC
8-bit Basic
Timer
Interval
Watchdog
Timer
PC
R4 R5
R2
PSW
Syst em controller
Timing generator
System
Clock Controller
Clock
Generator
RESET
XIN
XOUT
R40 / T0O
R41
R50
R20~R27
VDD
VSS
Power
Supply
8-bit serial
R51
R52
R53 / SCLK
R54 / SIN
R55 / SOUT
R56 / PWM1O/T1O
R57
R1
R10~R17
R3
R30~R35
Interface
Buzzer
Driver
R6
R60 / AN0
R61 / AN1
R62 / AN2
R63 / AN3
R64 / AN4
R65 / AN5
R66 / AN6
R67 / AN7
(448 bytes)
10-bit
AVDD AVSS
ADC Power
Supply
Stack Pointer
R0
R04
R03/BUZO
R02/EC0
R00/INT0 Vdisp/RA
R7
R70 / AN8
R71 / AN9
R72 / AN10
R42
R43 R73 / AN11
Sub System
Clock Controller
SXIN
SXOUT
R05
R06
R07
R01/INT1
RA
PWM
AX Y
High Voltage Port

13
13
DVD-310
R51
R30
R31
R32
R33
R34
R35
RA
R40
R41
R42
R43
R50
T0O
Vdisp
R66
R04
R03
R02
R01
R00
VDD
AVDD
R73
R72
R71
R70
R67
AN6
AN8
AN7
R27 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R26 R06 R05
R52 R54 R55 R56 R57
RESET
XI
XO
VSS
R74 R75
AVSS
R60 R61 R62 R63 R53 R64 R65
SIN
SOUT
PWM1O/T1O
SXI
SXO
AN0 AN1 AN2 AN3
SCLK
AN4 AN5
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
48 47 46 45
44 43 42 41 40 39
38 37 36 35 34 33
51
50
49
32
31
30
29
28
27
26
25
24
23
22
21
20
52
53
54
55
56
57
58
59
60
61
62
63
64
64MQFP
AN9
AN11
AN10
INT0
EC0
INT1
BUZO
High Voltage Port
GMS81C2012/20
PIN NAME In/Out Function
Basic Alternate
VDD - Supply voltage
VSS - Circuit ground
RA (V
disp
)I(I) 1-bit high-voltage Input only port High-voltage input power supply pin
RESET I Reset signal input
XIN I Oscillation input
XOUT O Oscillation output
SXIN(R74) I Sub Oscillation input General I/O ports
SXOUT(R75) O Sub Oscillation output
R00 (INT0) I/O (I)
8-bit high-voltage I/O ports
External interrupt 0 input
R01 (INT1) I/O (I) External interrupt 1 input
R02 (EC0) I/O (I) Timer/Counter 0 external input
R03 (BUZO) I/O (O) Buzzer driving output
R04~R07 I/O
R10~R17 I/O 8-bit high-voltage I/O ports
R20~R27 I/O 8-bit high-voltage I/O ports
R30~R35 I/O 6-bit high-voltage I/O ports
R40 (T0O) I/O (O) 4-bit general I/O ports Timer/Counter 0 output
R41~R43 I/O
R50~R52 I/O
8-bit general I/O ports
R53 (SCLK) I/O (I/O) Serial clock source
R54 (SIN) I/O (I) Serial data input
R55 (SOUT) I/O (O) Serial data output
R56 (PWM1O/T1O) I/O (O) PWM 1 pulse output /Timer/Counter 1 out-
put
R57 I/O
R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports
Analog voltage input
R70~R73
(AN8~AN11) I/O (I) 4-bit general I/O ports
AVDD - Supply voltage input pin for ADC
AVSS - Ground level input pin for ADC
VDD - Supply voltage
VSS - Circuit ground
Port Function Description

14
14
DVD-310
HY57V65120BTC-75 (ME: U11)
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1 Bank Address Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
PIN DESCRIPTION

15
15
DVD-310
T431616A-8S(ME:U5)
PIN PIN NAME DESCRIPTION
CLK System Clock Active on the positive going edge to sample all input.
CKE Clock Enable
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
CS Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
BA Bank Select Address
A0 ~ A10/AP
DQ0 ~ DQ15
Address
Selects bank to activated during row address latch time.
Select bank for read/write during column address latch time.
Row/column aaddresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
L(U)DQM Data Input/Output Mask
Data Input/Output
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
VDD/VSS Power Supply/Ground
Data inputs/outputs are multiplexed on the same pins.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
VDDQ/VSSQ Data Output Power/Ground
N.C/RFU No Connection/Reserved
for Future Use
This pin is recommended to be left No Connection on the device.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Powe and ground for the input buffers and the core logic.
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
DQ10
VSSQ
DQ9
VDDQ
DQ8
N . C / RFU
UDQM
CLK
CKE
N . C
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26
27
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
PIN DESCRIPTION
VDDQ

16
16
DVD-310
MX29LV160ABTC-70 (ME: U10)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
S TAT E
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA L AT C H
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-A19
CE
OE
WE
RESET

17
17
DVD-310
BH7862FS Terminal Function
BH7862FS (AV: IC54)
COUT
TEST
TEST
MIXOUT
MIXFB
GND
YTRAP
PYOUT
PYFB
GND
PbOUT
N.C.
PrOUT
01CTRAP
02MUTE1 MUTE1
03
20k
1.5-6M
BPF
20k
6M
LPF
6M
LPF 6dB
75ohm
6dB
6dB
75ohm
20k
6M
LPF
12M
LPF
CLAMP
CLAMP
CIN
04GND
05YIN
06VCC
07GND
08PYIN
09GND
10PYTRAP
11VCC
12PbIN
13GND
14PrIN
15MUTE2 MUTE2
16PrTRAP
32
31
30
29
28
27
GND26
YOUT25
YFB24
GND23
22
21
20
19
18
17
75ohm
6dB
75ohm
6dB
75ohm
6dB
75ohm
1 CTRAP
10 PYTRAP Pin for LC resonation
16 PrTRAP
27 YTRAP
2 MUTE1 Mute control pin, L: C, MIX, Y simultaneous mute
3 CIN
12 PbIN Signal input pin, chroma signal & color-difference signal
14 PrIN
4, 7, 9, 13, 20, 23, 26, 28 GND GND pin
5 YIN Signal input pin, luminance signal
8 PYIN
6VCC Power supply for C, MIX, Y
11 Power supply for PY, Pb, Pr
15 MUTE2 Mute control pin, L: PY, Pb, Pr simultaneous mute
17 PrOUT Signal output pin, color-difference signal
19 PbOUT
18 N.C. 
21 PYFB Signal output pin, luminance signal (progressive)
22 PYOUT
24 YFB Signal output pin, luminance signal (interlace)
25 YOUT
29 MIXFB Signal output pin, Y/C MIX signal
30 MIXOUT
31 TEST TEST pin
32 COUT Signal output pin, chroma signal
Description
Pin No. Port

18
18
DVD-310
AT49F001N-70JC(ME:U3)
FAN8024BDTF(ME:U6)
Pin Configurations
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET RESET
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4 3 2 1
32 31 30
14 15 16 17 18 19 20
I/O1 I/O2
GND
I/O3 I/O4 I/O5 I/O6
A12 A15 A16 RESET * VCC WE NC
*Note: This pin is a DC on the AT49F001N(T).
28 27 26 25 24 23 22 21 20 19 18 17 16 15
12345
67 89 10 11 12 13 14
STBY REF IN4 CAP4.1 CAP4.2 IN3 VCCGND PVCC2 FB4 PGND2 DO3
−
DO3+ DO4
−
DO4+
IN1
CAP1.1
CAP1.2
IN2.1 IN2.2
OUT2
FB1
VCC
PGND1
DO2
−
DO2+
DO1
−
DO1+
PVCC1
-
+
-
+
10K
20K
7.5K
X2
7.5K
Loading
Driver
Actuator
Driver
-
+
10K15K
-
+
-
+
20K
10K
7.5K
7.5K
-
+
X2
-
+
10K25K
Sled
Driver
Actuator
Driver
PVCC2
VCCPVCC1
VCC
PVCC1
PVCC2
TSD
GND
GND
Pin Definitions
Pin Number Pin Name I/O Pin Function Description
1 IN1 I CH1 input
2 CAP1.1 - Connection with capacitor
3 CAP1.2 - for CH1
4 IN2.1 I OP-AMP CH2 input(+)
5 IN2.2 I OP-AMP CH2 input(-)
6 OUT2 O OP-AMP CH2 output
7 FB1 I Feedback for CH1
8 VCC - Signal Vcc
9 PVCC1 - Power Supply 1
10 PGND1 - Power Ground 1
11 DO2
− O Drive2 Output (-)
12 DO2+ O Drive2 Output (+)
13 DO1
− O Drive1 Output (-)
14 DO1+ O Drive1 Output (+)
15 DO4+ O Drive4 Output (+)
16 DO4
− O Drive4 Output (-)
17 DO3+ O Drive3 Output (+)
18 DO3
− O Drive3 Output (-)
19 PGND2 - Power Ground 2
20 FB4 - Feedback for CH4
21 PVCC2 - Power Supply 2
22 VCCGND - Vcc ground
23 IN3 I CH3 input
24 CAP4.2 - Connection with capacitor
25 CAP4.1 - for CH4
26 IN4 I CH4 input
27 REF I Bias voltage input
28 STBY I Stand-by input

19
19
DVD-310
FAN8423D3TF(ME:U7)
CS4392(ME: U16)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1234567 891011121314
NC
A3
NC
A2
NC
A1
GND
NC
H1+
H1-
H2+
H2-
H3+
H3-
CS1 VM NC VCC
FG1X
EC
ECR
S/S
DIR FG3X SB PC1 NC VH
FG1X
Generator
Start
Stop
-+
Reverse Rota-
tion
Logic
Short
Brake
Hall
Commutation
Selector
Detec-
tor
Direc-
tion
Upper
Distribu-
Lower
Distribu-
Hall Amp
TSD
Current Sense
Amp
Output
Current Limit
Absolute
Values
FG3X Generator
GND
GND
Pin Definitions
Pine Number Pin Name I/O Pin Function Description
1 NC - No connection
2 A3 O Output (A3)
3 NC - No connection
4 A2 O Output (A2)
5 NC - No connection
6 NC - No connection
7 A1 O Output (A1)
8 GND - Ground
9 H1+ I Hall signal (H1+)
10 H1- I Hall signal (H1-)
11 H2+ I Hall signal (H2+)
12 H2- I Hall signal (H2-)
13 H3+ I Hall signal (H3+)
14 H3- I Hall signal (H3-)
15 VH I Hall bias
16 NC - No connection
17 PC1 - Phase compensation capacitor
18 SB I Short brake
19 FG3X O FG waveform (3X)
20 DIR O Rotational direction output
21 ECR I Output current control reference
22 EC I Output current control voltage
23 S/S I Power save (Start/Stop switch)
24 FG1X O FG waveform (1X)
25 VCC - Supply voltage (Signal)
26 NC - No connection
27 VM - Supply voltage (Motor)
28 CS1 - Output current detection
RST
M1
M3
M2 M0
(SDA/CDIN) (SCL/CCLK) (AD0/CS) AMUTEC BMUTEC CMOUT FILT+
SCLK
LRCK
SDATA
AOUTB-
AOUTB+
AOUTA-
AOUTA+
REFERENCE
EXTERNAL
MUTE CONTROL
VOLUME
CONTROL
VOLUME
CONTROL
SERIAL
PORT MIXER
INTERPOLATION
FILTER
ANALOG
FILTER
△ Σ
DAC
△ Σ
DAC
ANALOG
FILTER
INTERPOLATION
FILTER
MODE SELECT
( CONTROL PORT)
MCLK
1
2
3
4
20
19
18
17
RST
VL
SDATA
SCLK
AMUTEC
AOUTA-
AOUTA+
VA
5
6
7
8
16
15
14
13
LRCK
MCLK
M3
(SCL/CCLK) M2
AGND
AOUTB+
AOUTB-
BMUTEC
9
10
12
11
(SDA/CDIN) M1
(AD0/CS) M0
CMOUT
FILT+

20
20
DVD-310
SN74HCU04PWR (ME: U8)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
Vcc
6A
6Y
5A
5Y
4A
4Y
15
1
2
3
4
5
6
7
8
5
16
14
13
12
11
10
9
A0
A1
A2
Q0
Q1
Q2
Q3
V
SS
V
DD
SDA
SCL
NC
Q7
Q6
Q5
Q4
BU2098F (AV: IC51)
I C Bus
Contoller
2
Write
Buffer
Latch
Power-On Reset Shift Register
8bit
Block Diagram
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
AT24C02N(ME: U13)
RC1117S285T(ME: Q4)
VOUT
3
2
1
IN
OUT
ADJ/GND
V6309M(ME: Q5)
GND Input
Output
FRONT
VIEW
Output
GND Input
FRONT
VIEW
AK79L08AZ (AV: IC53)
KA78L08AZ(AV: IC52)