Denon S-101 User manual
SERVICE MANUAL
DVD HOME THEATER SYSTEM
MODEL S-101
TOKYO, JAPAN
Denon Brand Company, D&M Holdings Inc.
Some illustrations using in this service manual are
slightly different from the actual set.
●
Please use this service manual with referring to the
operating instructions without fail.
●
For purposes of improvement, specifications and
design are subject to change without notice.
●
●
本文中に使用しているイラストは、説明の都合上現物
と多少異なる場合があります。
●
修理の際は、必ず取扱説明書を参照の上、作業を行っ
てください。
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
●
本機の仕様は性能改良のため、予告なく変更すること
があります。
●
補修用性能部品の保有期間は、製造打切後8年です。
注 意
X0244 V.01 DE/CDM 0507
For U.S.A., Canada
& Europe model
HOME THEATER SYSTEM (S-101) consists of DVD SURROUND RECEIVER (ADV-S101)
and SUB WOOFER (DSW-S101) and SPEAKER SYSTEM (SC-S101)
Ver. 1
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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2
S-101
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.
LASER RADIATION
Do not stare into beam or view directly with optical instruments, class 3A laser product.
注 意
注意事項をお守りください！
サービスのとき特に注意を必要とする個所について
は、キャビネット、部品、シャーシなどにラベルや
捺印で、注意事項を表示しています。これらの注意
書きおよび取扱説明書などの注意事項を必ずお守り
ください。
感電に注意！
(1)このセットは、交流電圧が印加されていますの
で、通電時に内部金属部に触れると感電するこ
とがあります。従って通電サービス時には、絶
縁トランスの使用や手袋の着用、部品交換に
は、電源プラグを抜くなどして、感電にご注意
ください。
(2)内部には、高電圧の部分がありますので、通電
時の取扱には、十分ご注意ください。
指定部品の使用！
セットの部品は難燃性や耐電圧など安全上の特性を
持ったものとなっています。従って交換部品は、使
用されていたものと同じ特性の部品を使用してくだ
さい。特に配線図、部品表に 印で指定されている
安全上重要な部品は必ず指定のものをご使用くださ
い。
部品の取付けや配線の引きまわしは、元どおりに！
安全上、テープやチューブなどの絶縁材料を使用し
たり、プリント基板から浮かして取付けた部品があ
ります。また内部配線は引きまわしやクランパーに
よって発熱部品や高圧部品に接近しないように配慮
されていますので、これらは必ず元どおりにしてく
ださい。
サービス後は安全点検を！
サービスのために取り外したねじ、部品、配線など
が元どおりになっているか、またサービスした個所
の周辺を劣化させてしまったところがないかなどを
点検し、外部金属端子部と、電源プラグの刃の間の
絶縁チェックをおこなうなど、安全性が確保されて
いることを確認してください。
サービス、点検時には次のことにご注意願います。
注 意
安全上重要な部品について
（絶縁チェックの方法）
電源コンセントから電源プラグを抜き、アンテナ
や、プラグなどを外し、電源スイッチを入れま
す。500Ｖ絶縁抵抗計を用いて、電源プラグのそれ
ぞれの端子と、外部露出金属部〔アンテナ端子、
ヘッドホン端子、マイク端子、入力端子など〕と
の間で、絶縁抵抗値が1ＭΩ以上であること、この
値以下のときは、セットの点検修理が必要です。
本機に使用している多くの電気部品、および機構部品
は安全上、特別な特性を持っています。この特性はほ
とんどの場合、外観では判別つきにくく、また、もと
の部品より高い定格（定格電力、耐圧）を持ったもの
を使用しても安全性が維持されるとは、限りません。
安全上の特性を持った部品は、このサービスマニュア
ルの配線図、部品表につぎのように表示していますの
で、必ず指定されている部品番号のものを使用願いま
す。
(1) 配線図…
(2) 部品表… マークで表示しています。
マークで表示しています。
指定された部品と異なるものを使用し
た場合には、感電、火災などの危険を
生じる恐れがあります。
注 意
安全上重要な部品について
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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3
S-101
各部のはずしかた
（組み立てるときは、逆の順序でおこなってください。）
1. ローダーパネルのはずしかた
(1) 電源を入れ「 (OPEN/CLOSE)」ボタンを押して、
ディスクトレイを開きます。
(2) ローダーパネルを持ち上げてはずします。
2. サイドパネル、ボトムカバーのはずしかた
(1) 底面よりネジを 13 本はずします。
(2) 裏面よりネジを 7 本はずし、サイドパネル、ボトムカ
バーをそれぞれ矢印の方向へはずします。
RDISASSEMBLY
(Follow the procedure below in reverse order when
reassembling.)
1. Loader Panel
(1) Switch on, and press [ (OPEN/CLOSE)] button
to open the Disc tray.
(2) Detach the Loader Panel by lifting.
2. Side Panel, Bottom Cover
(1) Remove 13 bottom screws.
(2) Remove 7 rear screws, then detach Side Panel and
Bottom Cover.
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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4
S-101
3. トップカバーのはずしかた
(1) トップカバーを止めている上部のネジ 9 本をはず
し、トップカバーを矢印の方向へはずします。
4. フロントパネルのはずしかた
(1) フロントパネルからの基板とシャーシを止めてい
るネジを 3 本はずします。
(2) フロントパネル側面を止めているネジ 4 本（左右各 2
本）をはずし、フロントパネルを矢印の方向へはずし
ます。
5. バックパネルのはずしかた
(1) 各端子を止めているネジおよびバックパネルと
シャーシを止めているネジをはずし、バックパネ
ルをはずします。
3. Top Cover
(1) Remove 9 top screws, then detach Top Cover.
4. Front Panel Ass’y
(1) Remove 3 Front panel screws, then detach P.W.B.
and chassis.
(2) Remove 4 Front panel side screws, then detach the
Front Panel Ass’y.
5. Front Panel Ass’y
(1) Remove earch terminal screws, Back Panel screws
and Chassis screws, then detch the Back Panel.
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
5
S-101
特殊操作方法
1. 初期化
※ファンクション、VOL 及び DVD メカ (RL-874) 等の
データを初期化します。
(1) ACコードがコンセントより外れていることを確認
します。(ACOFF)
(2) 本体の FUNCTION ボタンと OPEN/CLOSE( ) ボタ
ンを押しながら、AC コードをコンセントに接続
(ACON) します。
(3) ディスプレイと LED の全点灯を確認したら、本体
の FUNCTION ボタンと OPEN/CLOSE( ) ボタンを
離します。
(4) 約 3 秒後、ディスプレイに "INITIALIZE" が表示され
ます。
(5) 初期化完了 ("INITIALIZE" 消灯 ) 後、FUNCTION は
"DVD"、VOL位置は-∞(表示は"---dB")となります。
2. システムチェックモード
※バージョン表示等をおこないます。
(1) STANDBY 時、本体の STOP（ ）ボタンと A.FWD
（ ）ボタンを押しながら、ON/STANDBY ボタ
ンを押します。
(2) リモコン（RC-1007）の STATUS ボタンを押すこと
により
時間(TIME)→システムマイコンのバージョン(SYS
Ver) →システムマイコンのバージョンアップ日
(SYSDate）→DSP のバージョン (DSPVer) → DSP
のバージョンアップ日(DSPDate)→ドライブマイ
コンのバージョンアップ日 (DrDate) →ESS のバー
ジョン (EssVer) → Ess のバージョンアップ日 (Ess
Date) →地域番号 (RegionNo.)
の順に表示されます。
(3) 解除するにはAC コードを抜きます。(ACOFF)
( 注 1) DVD メカのドライブバージョン表示、ESS
のバージョン表示については、1 度ファン
クッションを DVD にしないと表示されま
せん。
Special operating procedures
1. Initialization
※This initializes the data for the function, volume,
DVD mechanism (RL-874), etc.
(1) Check that the AC cord is disconnected from the
power outlet. (AC OFF)
(2) While pressing the FUNCTION and OPEN/CLOSE
( ) buttons on the main unit, plug the AC cord into
the power outlet. (AC ON)
(3) Check that the entire display and all the LEDs light,
then release the FUNCTION and OPEN/CLOSE
()buttons.
(4) After about 3 seconds, "INITIALIZE" appears on the
display.
(5) After initialization is complete (when "INITIALIZE"
turns off), the function is set to "DVD" and the vol-
ume level is set to -∞("-dB" is displayed).
2. System check mode
※Use this to display the version information, etc.
(1) In the standby mode, while pressing the STOP ( )
and A.FWD ( ) buttons on the main unit, press
the ON/STANDBY button.
(2) Press the STATUS button on the remote control
unit (RC-1007) to display the following information,
in this order: Time (TIME) →System microproces-
sor version (SYS Ver) →Date of system micropro-
cessor version updating (SYS Date) →DSP ver-
sion (DSP Ver) →Date of DSP version updating
(DSP Date)→Date of drive microprocessor version
updating (Dr Date) →ESS version (Ess Ver) →
Date of ESS version updating (Ess Date) →Region
number (Region No.)
(3) To cancel, unplug the AC cord. (AC OFF)
NOTE 1: The DVD mechanism driver version and
ESS version are not displayed unless the
function is once set to DVD.
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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6
S-101
ADJUSTMENT
1. SETTING
(1) Connect the oscilloscope to the Y-signal, PB-signal and
CB-signal, PR-signal and CR-signal of ZONE2 COMPO-
NENT OUT terminal and each terminate at 75 Ohms.
※Use the 75 Ohms resistance must be 1%
(2) DVD test disc : DVDT-S01
(3) S OUT of DVD player is connected to AUX1 S IN.
2. Before Adjustment
2.1. Setting the Oscilloscope as below.
(1) PB/CB, PR/CR
(a) TIME/DIV : 10μs
(b) VOLT/DIV : 100mV
(Use the probe : x10 )
(2) Y
(a) TIME/DIV : 10μs
(b) VOLT/DIV : 200mV
(Use the probe : x10 )
Power on. Power Supply
USA & Canada : 120V
Europe : 230V
Japan : 100V
China & Korea : 220V
2.2. Setup the DVD player and confirmation of the
stators
(1) Set to "INTERLACED" mode at the COMPONENT OUT.
(2) Confirm the DVD player’s out put level is equal as the
item 2.4. in following.
2.3. Preparation
(1) Push the FUNCTION knob to select "AUX1" input.
(2) Push [OPEN/CLOSE] button of DVD player, then open
the Disc Tray.
Set DVD test disc (DVDT-S01) on the Disc Tray, and
then push [CLOSE] button.
(3) DVD player FL display appear "STOP", push [PLAY] but-
ton to playback DVD.
(4) Push the [DISPLAY] button of remote control of DVD
player unit and then appear the ON-Screen Display (GUI)
on the monitor TV.
(5) Push the [+10] and [2] button, select Title 12 of DVD.
(6) Push the [ENTER] button, playback Title 12.
(color bar 75%)
調整
1. セッティング手順
(1) セットの ZONE2COMPONENTOUT の端子（Y,PB/CB,
PR/CR）をそれぞれオシロスコープ（終端抵抗：75Ω）
に接続します。
※ 75Ω 抵抗は 1％品を使用する事。
(2) DVD テストディスク：DVDT-S01 を用意します。
(3) DVD プレーヤーの SOUT を AUX1SIN に接続します。
2. 調整のまえに
2.1. オシロスコープを下記に設定
(1) PB/CB,PR/CR
(a) TIME/DIV : 10μs
(b) VOLT/DIV : 100mV
（プローブ x10 使用）
(2) Y
(a) TIME/DIV : 10μs
(b) VOLT/DIV : 200mV
（プローブ x10 使用）
電源電圧 ： 100V
2.2. DVD プレーヤの設定と確認
(1) COMPONENTOUTの設定を"インターレース"にします。
(2) DVD プレーヤーの出力が以下 2.4. に合っていることを
確認します。
2.3. 準備手順
(1) FUNCTION ノブを押し、入力を "AUX1" に切り替えます。
(2) DVD プレーヤーの「OPEN/CLOSE」ボタンを押しトレイ
を開き、トレイ上に DVD テストディスク（DVDT-S01）
をセット後、「CLOSE」ボタンを押します。
(3) DVD プレーヤーの表示管上に "STOP" が表示されてか
ら、「PLAY」ボタンを押し、ディスクを再生します。
(4) DVD プレーヤーのリモコンの「DISPLAY」ボタンを押
しグラフィカル・ユーザー・インターフェイス (GUI) 画
面を出します。
(5) 番号ボタンの｢ +10 ｣ , ｢ 2 ｣ボタンを押し、Title12 を選択
します。
(6) 「ENTER」ボタンを押し、Title12 を再生します。
（75％カラーバー信号）。
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
7
S-101
2.4. Procedure
(1) Adjust the signal of COMPONENT OUT by the wave of
oscilloscope.
(a) Target, Y-signal
Point : 1U-3695-3 VR601
Adjustment Value : 714 ±35mV
Waveform
(b) Target, PB/CB-signal
Point : 1U-3695-3 VR602
Adjustment Value : *525 ±25mV
Waveform
(c) Target, PR/CR-signal
Point : 1U-3695-3 VR603
Adjustment Value : *525 ±25mV
Waveform
* : 486 ±10mV for U.S.A. & Canada model
Y
Y-signal COMPONENT OUT
PB/CB-signal COMPONENT OUT
PB
PR/CR-signal COMPONENT OUT
PR/CR
2.4. 手順
(1) COMPONENTOUTの信号レベルをオシロスコープ上の
波高値で調整します。
(a) Y 信号レベル
調整個所 ： 1U-3695-3VR601
調整値 ： 714 ± 35ｍV
波形
(b) PB/CB信号レベル
調整個所 ： 1U-3695-3VR602
調整値 ： 525 ± 25ｍV
波形
(c) PR/CR信号レベル
調整個所 ： 1U-3695-3VR603
調整値 ： 525 ± 25ｍV
波形
Y
COMPONENTOUT の Y 信号レベル
PB/CB
COMPONENTOUT の PB/CB信号レベル
PR/CR
COMPONENTOUT の PR/CR信号レベル
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
8
S-101
BLOCK DIAGRAM
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㪪㪧
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㪍㪋㪤
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㪪㪰㪪㪫㪜㪤㩷㫌㪚㪦㪤
㪤㪊㪇㪍㪉㪎㪝㪟㪧㪞㪧
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㪤㪬㪫㪜
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㪄
㪄
㪄
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㪄
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㪦㫌㫋㫇㫌㫋㩷㪞㪸㫀㫅㩷㪘㫄㫇㪑
㩷㪇㪆㪂㪉㪆㪂㪋㪆㪂㪍㪆㪂㪏㪆
㪂㪈㪇㪆㪂㪈㪉㪻㪙
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IN
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OUT
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㪦㪬㪫
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1
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2
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9
4
2
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1
3
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2
2
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6
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1
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9
9
2
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2
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1
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6
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
10
S-101
SEMICONDUCTORS / 半導体一覧表
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
主な半導体を記載しています。汎用の半導体は記載を省略しています。
1. IC’s
ES6128F (RL-S874: U9)
FunctionI/OPin No. Pin Name
ES6128 F Terminal Function
1, 18, 27, 59,
68, 75, 92, 99,
104, 130, 148, VEE I I/O power supply.
157, 159, 164,
183, 193, 201
8, 17, 26, 34,
43, 52, 60, 67,
76, 84, 91, 98,
103, 112, 120, VSS I Ground.
129, 138, 147,
156, 163, 171,
177, 184, 192,
200, 208
23:19, 16:10,
7:2, 207:204 LA[21:0] O Device address output.
9, 35, 44, 83,
121, 139, 172 VCC I Core power supply.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
VSS
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
VEE
VSS
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
VSS
VEE
DCAS#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
VEE
VSS
DB0
DB1
DB2
DB3
DB4
DB5
VCC
VSS
DB6
DB7
DB8
DB9
DB10
DB11
VSS
VEE
DB12
DB13
DB14
DB15
DCS1#
VSS
VEE
DCS0#
DQM
DSCK
VSS
VEE
VSS
HA1
HA0
HCS3FX#
HCS1FX#
HIOCS16#
HRD#
HWR#
VEE
VSS
HIORDY
HRST#
HIRQ
HRDQ#
HWRQ#
HD15
HD14
VCC
VSS
HD13
HD12
HD11
HD10
HD9
HD8
HD7
VEE
VSS
HD6
HD5
HD4
HD3
HD2
HD1
HD0
VCC
VSS
HSYNC#
VSYNC#
PCLKQSCN
PCLK2XSCN
YUV7
YUV6
YUV5
VSS
ADVEE
YUV4
YUV3
YUV2
YUV1
YUV0
DCLK
VSS
LA3
LA2
LA1
LA0
CAMIN1
CAMIN0
VEE
VSS
LWRHL#
LWRLL#
LD15
LD14
LD13
LD12
VEE
VSS
LD11
LD10
LD9
LD8
LD7
LD6
LD5
VSS
VEE
LD4
LD3
LD2
LD1
LD0
VSS
LCS3#
LCS2#
LCS1#
LCS0#
VCC
VSS
LOE#
AUX[7]
AUX[6]
AUX[5]
AUX[4]
AUX[3]
VEE
VSS
AUX[2]
AUX[1]
AUX[0]
VEE
HA2
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
VSS
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
VEE
VSS
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
VSS
VEE
DCAS#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
VEE
VSS
DB0
DB1
DB2
DB3
DB4
DB5
VCC
VSS
DB6
DB7
DB8
DB9
DB10
DB11
VSS
VEE
DB12
DB13
DB14
DB15
DCS1#
VSS
VEE
DCS0#
DQM
DSCK
VSS
VEE
VSS
HA1
HA0
HCS3FX#
HCS1FX#
HIOCS16#
HRD#
HWR#
VEE
VSS
HIORDY
HRST#
HIRQ
HRDQ#
HWRQ#
HD15
HD14
VCC
VSS
HD13
HD12
HD11
HD10
HD9
HD8
HD7
VEE
VSS
HD6
HD5
HD4
HD3
HD2
HD1
HD0
VCC
VSS
HSYNC#
VSYNC#
PCLKQSCN
PCLK2XSCN
YUV7
YUV6
YUV5
VSS
ADVEE
YUV4
YUV3
YUV2
YUV1
YUV0
DCLK
VSS
LA3
LA2
LA1
LA0
CAMIN1
CAMIN0
VEE
VSS
LWRHL#
LWRLL#
LD15
LD14
LD13
LD12
VEE
VSS
LD11
LD10
LD9
LD8
LD7
LD6
LD5
VSS
VEE
LD4
LD3
LD2
LD1
LD0
VSS
LCS3#
LCS2#
LCS1#
LCS0#
VCC
VSS
LOE#
AUX[7]
AUX[6]
AUX[5]
AUX[4]
AUX[3]
VEE
VSS
AUX[2]
AUX[1]
AUX[0]
VEE
HA2
VEE
w
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1
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2
2
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1
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9
2
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2
9
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0
5
1
5
1
3
6
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3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
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11
S-101
24 RESET# I Reset input, active low.
25 TDMDX O TDM transmit data.
28 TDMDR I TDM receive data.
29 TDMCLK I TDM clock input.
30 TDMFS I TDM frame sync.
31 TDMTSC# O TDM output enable.
TWS O Audio transmit frame sync.
SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type
000VCOoff.
001DCLK
32 0 1 0 Bypass mode
0 1 1 DCLK x 2
1 0 0 DCLK x 4.5
1 0 1 DCLK x 3
110DCLKx3.5z
1 1 1 DCLK x 4
33 TSD0 O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.
36 TSD1 O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.
37 TSD[2] O Audio transmit serial data output 2.
38 TSD[3] O Audio transmit serial data output 3.
39 MCLK I/O Audio master clock for audio DAC.
40 TBCK O Audio transmit bit clock.
SPDIF O S/PDIF output.
SEL_PLL3 I Clock source select.
41 SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
42,48 NC No connect pins. Leave open.
45 RSD I Audio receive serial data.
46 RWS I Audio receive frame sync.
47 RBCK I Audio receive bit clock.
49 XIN I Crystal input.
50 XOUT O Crystal output.
51 AVEE I Analog power for PLL.
66:61, 58:53 DMA[11:0] O DRAM address bus [11:0]
69 DCAS# O DRAM column address strobe,
70 DSCK_EN O DRAM clock enable.
71 DWE# O DRAM write enable.
72 DRAS# O DRAM row address strobe.
73 DMBS0 O SDRAM bank select 0.
74 DMBS1 O SDRAM bank select 1.
96:93, 90:85,
82:77 DB[15:0] I/O DRAM data bus [15:0]
97, 100 DCS[1:0]# O SDRAM chip select [1:0]
101 DQM O Data input/output mask.
102 DSCK O Output clock to SDRAM.
105 DCLK I 27 MHz clock input to PLL.
106 UDAC OVideo UDAC output.
107 VREF I Internal voltage to video DAC.
108 CDAC OVideo CDAC output.
109 COMP I Compensation input.
110 RSET I DAC current adjustment resistor input.
111 ADVEE I Analog power for video DAC.
113 YDAC OVideo YDAC output.
FunctionI/O
Pin No. Pin Name
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0
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9
4
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1
3
9
4
2
2
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6
5
1
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9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
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http://www.xiaoyu163.com
12
S-101
114 VDAC OVideo VDAC output.
115 YUV7 O YUV7 pixel output data.
116 PCLK2XSCN I/O 27 MHz video output pixel clock.
117 PCLKQSCN O 13.5 MHz video output pixel clock.
118 VSYNC# I/O Vertical sync, active low.
119 HSYNC# I/O Horizontal sync, active low.
127:122 HD[5:0] I/O Host data I/O [5:0].
128 HD[6] I/O Host data I/O [6].
131 HD[7] I/O Host data I/O [7].
132 HD[8] I/O Host data bus 8.
133 HD[9] I/O Host data bus line 9.
134 HD[10] I/O Host data bus line 10.
135 HD[11] I/O Host data bus line 11.
136 HD[12] I/O Host data bus line 12.
137 HD[13] I/O Host data bus line 13.
140 HD[14] I/O Host data bus line 14.
141 HD[15] I/O Host data bus line 15.
142 HWRQ# O Host write request.
143 HRRQ# O Host read request.
144 HIRQ I/O Host interrupt.
145 HRST# O Host reset.
146 HIORDY I Host I/O ready.
149 HWR# I/O Host write.
150 HRD# O Host read.
151 HIOCS16# I Device16-bit data transfer.
152 HCS1FX# O Host select 1.
153 HCS3FX# O Host select 3.
158, 155:154 HA[2:0] I/O Host address bus.
160 AUX[0] O I2C DATA.
162 AUX[2] I/O Auxiliary ports 2.
165 AUX[3] I/O Auxiliary ports 3.
169:166 AUX[7:3] I/O Auxiliary ports 7:3.
170 LOE# O Device output enable.
176:173 LCS[3:0]# O Chip select [3:0].
197:194,
191:185, LD[15:0] I/O EPROM device data bus.
182:178
198 LWRLL# O Device low-byte write enable.
199 LWRHL# O Device high-byte write enable.
202 CAMIN0 I Camera YUV 0.
203 CAMIN1 I Camera YUV 1.
FunctionI/O
Pin No. Pin Name
161AUX[1]OI2CCLK.
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1
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1
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9
9
2
8
9
4
2
9
8
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1
3
9
4
2
2
9
6
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1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
13
S-101
M5705 (RL-S874: U1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AVSS-DS
XSRFIN
XSIPIN
AVDD5-DS
XSDSSLV
XSRSLINT
VDD
XSAWRC
XSRFGC
XSEFGC
XSFOCUS
XSTRACK
XSSLEG
AVDD5-DA
XSMOTOR
AVSS-DA
XSRFRPLP
XSTELP
XSVREF2
XSRFRP
XSTEXI
AVSS-AD
XSTEI
XSFEI
XSAEI
AVDD5-AD
XSSBAD
GND
XSDFCT
XSCSJ
XSCLK
XSDATA
XSLDC
XSFGIN
XSSPDON
XSFLAG(3)
XSFLAG(2)
XSFLAG(1)
XSFLAG(0)
XMP1_7
XMP1_6
GND
NC
XMP1_4
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
XRD(3)
XRD(12)
GND
XRD(2)
XRD(13)
XRD(1)
XRD(14)
XRD(0)
XRD(15)
XHD(7)
XHD(8)
XHD(6)
XHD(9)
XHD(5)
XHD(10)
XHD(4)
XHD(11)
VDD
XHD(3)
XHD(12)
XHD(2)
XHD(13)
GND
XHD(1)
XHD(14)
XHD(0)
XHD(15)
XHDRQ
XHIOWJ
XHIORJ
XHIORDY
XHDACKJ
XHINT
XHCS16J
XHA(1)
XHPDIAGJ
XHA(0)
XHA(2)
XHCS1J
XHCS3J
XHDASPJ
XMA(15)
XMA(14)
XMA(13)
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
XMP1_3
XMFSCSJ
XMP1_2
XGPIO(2)
XMP1_1
XMRSTJ
XGPO(1)
XGPO(0)
XCRSTJ
XMPSENJ
VDD
XMALE
XMP1_0
VDD
XOSC1
XOSC2
GND
XMD(0)
XMD(1)
XMD(2)
XMD(3)
XMD(4)
XMD(5)
XMD(6)
XMD(7)
XMCSJ
XMRDJ
XMWRJ
XMINT1J
XMA(11)
XMA(10)
VDD
XMA(9)
XMA(8)
XMA(7)
XMA(6)
XMA(5)
XMA(4)
XMA(3)
XMA(2)
XMA(1)
XMA(0)
XMA(12)
GND
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
XSAWRCVCO
XSVREFO
XSPDOFTR2
XSVR_PLL
XSFTROPI
XSFDO
AVSS_PL
XSPLLFTR2
AVDD5_PL
XSFDIREF
XSPDIREF
GND
XTSLRF
XTPLCK
VDD
XRA(3)
XRA(2)
XRA(1)
XRA(0)
XRA(4)
XRA(5)
XRA(6)
GND
XRA(7)
XRA(10)
XRA(11)
VDD
XRA(8)
XRA(9)
XROEJ
VDD
XRCASJ
XRRASJ
XRSDCLK
XRWEJ
XRD(7)
XRD(8)
XRD(6)
GND
XRD(9)
XRD(5)
XRD(10)
XRD(4)
XRD(11)
Data
Separator
ATAPI
&
MPEG
I/F
Digital
Servo
DVD-DSP RAM
Arbiter
Target
Search
ROM
C3 ECC
EDC
MPEG
DEC.
Motor
Driver
PC
4M DRAM
CD-DSP MCU
M
M5705
M5705 Terminal Function
DescriptionPin No. Pin Name Type
2 XSRFIN I/A Analog RF signal input after passing through the equalizer
3 XSIPIN I/A Inverting input pin of data slicer
5 XSDSSLV O/A Slice level output pin
6 XSRSLINT I/A Reference current setting pin for analog data slicer
8 XSAWRC O/A Output for enlarge VCO range. Analog output from DAC buffer
9 XSRFGC O/A RF gain control output
10 XSEFGC O/A E,F gain control output
11 XSFOCUS O/A Output voltage level for focusing buffer IC
12 XSTRACK O/A Output voltage level for tracking buffer IC
13 XSSLEG O/A Output voltage level for sledge buffer IC
15 XSMOTOR O/A Output voltage level for spindle motor buffer IC
17 XSRFRPLP I/A High bandwidth low pass filter input for RFRP
18 XSTELP I/A High bandwidth low pass filter input for TE
19 XSVREF2 I/A 2.1V reference voltage input
20 XSRFRP I/A RF ripple/envelope signal input
21 XSTEXI I/A Tracking zero crossing input signal
23 XSTEI I/A Tracking error input signal
24 XSFEI I/A Focus error input signal
25 XSCEI I/A 1. Center error input signal
2. Photo Interrupt input
w
w
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3
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1
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9
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2
8
9
4
2
9
8
T
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1
3
9
4
2
2
9
6
5
1
3
9
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14
S-101
DescriptionPin No. Pin Name Type
27 XSSBAD I/A Sub-beam addition signal input
166 XSPDIREF I/A Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
167 XSFDIREF I/A Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
169 XSPLLFTR2 I/A Data PLL loop filter pin#2
171 XSFDO O/A Output node of frequency detector charge pump circuit
172 XSFTROPI I/A Input node of loop filter OP circuit
173 XSVR_PLL I/A PLL reference voltage input
174 XSPDOFTR2 I/A Phase detector filter pin#1
175 XSVREFO O/A Reference voltage output
176 XSAWRCVCO I/A Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
29 XSDFCT I Detect detection signal input
30 XSCSJ O Chip select signal for accessing control registers
31 XSCLK O Clock output for accessing control registers
32 XSDATA I/O Registers data input/output pin
33 XSLDC O Laser diode on/off control output for both CD/DVD
34 XSFGIN I Motor Hall sensor input
35 XSSPDON O Spindle motor on output
36, 37, 38, 39 XSFLAG[3:0] O These pins are used to monitor some status of servo control block
48, 51, 52 XGPIO[2:0] I/O 1. These pins are used as general purpose I/O bus
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
40 XMP1_7 I/O Internal microcontroller programmable I/O port 1.7.
41 XMP1_6 I/O Internal microcontroller programmable I/O port 1.6.
43 XMP1_5 I/O This pin is now changed to be NC.
44 XMP1_4 I/O Internal microcontroller programmable I/O port 1.4.
45 XMP1_3 I/O Internal microcontroller programmable I/O port 1.3.
47 XMP1_2 I/O Internal microcontroller programmable I/O port 1.2.
49 XMP1_1 I/O Internal microcontroller programmable I/O port 1.1.
57 XMP1_0 I/O Internal microcontroller programmable I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16)
46 XMFSCSJ I/O Output chip select connected to external flash ROM chip enable pin
54 XMPSENJ I/O Output program store enable connected to external ROM PSENJ pin.
56 XMALE I/O This signal is used as address latch signal in address/data mux mode
70 XMCSJ I/O 1. This signal must be asserted for all microcontroller accesses to the register of this chip
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
71 XMRDJ I/O 1. This signal is used as the Read Strobe signal
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
72 XMWRJ I/O This signal is used as the Wire Strobe signal
73 XMINT1J I/O 1. This signal is an interrupt line to the microcontroller
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
74, 75, 77, 78,
XMA[15:0] I/O These pins are used as address bus
79, 80, 81, 82,
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65, XMD[7:0] I/O These pins are used as data bus for the 16-bit processor mode, or the address/data mux
66, 67, 68, 69 bus for the 8-bit processor mode.
163 XTPLCK I/O PLCK test pin
164 XTSLRF I/O SLRF test pin
59 XOSC1 I Crystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
60 XOSC2 O Crystal output
53 XCRSTJ I Chip Reset. As asserted low input generates a component reset that stops all operations within
the chip and deasserts all output signals. All input/output signals are set to input.
94 XHCS1J I This pin is used to select the command block task file registers
93 XHCS3J I This pin is used to select the control block task file registers
103 XHIORJ I Asserted by the host during a host I/O read operation
104 XHIOWJ I Asserted by the host during a host I/O write operation
105 XHDRQ O
1.
DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
2.
MPEG acknowledge.This pin is used as the ACKJ signal when MPEG interface mode is selected.
101 XHDACKJ I
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
99 XHCS16J O
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
50 XHRSTJ I Host Reset. The reset of ATA bus
100 XHINT O
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
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TEL 13942296513 QQ 376315150 892498299
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15
S-101
DescriptionPin No. Pin Name Type
97 XHPDIAGJ I/O This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
92 XHDASPJ I/O This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. This pin is used for Master/Slave drive communication and/or for driving an LED
102 XHIORDY I/O
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
95, 96, 98 XHA[2:0] I Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
XHD[15.0] I/O
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
106, 107, 108, 2.
MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
109, 111, 112, 3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
113, 114, 116, bit3-0 and VCD I/F is as follow
117, 118, 119, HD0—CD-DATA
120, 121, 122, HD1—CD-LRCK
123 HD2—CD-BCK
HD3—CD-C2PO
143 XRSDCLK O This signal is the clock output for SDRAM
147 XROEJ O This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
142 XRWEJ O This signal is asserted low when a buffer memory write operation is active
144 XRRASJ O This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
145 XRCASJ O This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA[8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
148, 149, 151, 0: By registers to decide input/output
152, 153, 155, RA[6] : System test pin output
156, 157, 158, XRA[11:0] O 1: Normal operation
159, 160, 161 0: System test pin output
RA[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (internal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
124, 125, 126,
XRD[15:0] I/O These signals are the 8-bit parallel data lines to/from the buffer memory.
127, 128, 129,
131, 132, 134,
135, 136, 137,
138, 139, 140,
141
4 AVDD5_DS Analog Power +5V for Data Slicer part
14 AVDD5_DA Analog Power +5V for DAC part
26 AVDD5_AD Analog Power +5V for ADC part
168 AVDD5_PL Analog Power +5V for Data PLL part
7, 55, 58, 76,
VDD Power +3.3V for digital core logic and pad
115, 146,
150, 162
1 AVSS_DS Analog Ground for Data Slicer part
16 AVSS_DA Analog Ground for DAC part
22 AVSS_AD Analog Ground for ADC part
170 AVSS_PL Analog Ground for Data PLL part
28, 42, 61,
GND Digital Ground core logic and pad.
88, 110, 130,
138, 154, 165
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TEL 13942296513 QQ 376315150 892498299
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16
S-101
M30627FHPGP (IC202: 1U-3694)
PIN
NO
Port
Function
Port
setting Port Name Explanation
1 VREF I VREF Reference Voltage Input for A/D converter
2 AVcc I AVcc Positive power
3 SIN4 O FL_CS Chip Enable output to FLD
4 SOUT4 SO FL_DA Serial Data output to FLD
5 CLK4 SO FL_CK Serial Clock output to FLD
6 P94 I BUSY1 Interrupt request from DSP
7 P93 I ACK1 Interrupt request from DSP
8 SOUT3 SO DSPMOSI Serial Data output to DSP
9 SIN3 SI DSPMISO Serial Data input from DSP
10 CLK3 O DSPSPICLK Serial Clock output to DSP
11 P141 O DSPSPICS Chip Enable output to DSP
12 P140 O FL_RST Reset output to FLD
13 BYTE GND
14 CNVSS Select input of Flash rom write Mode
15 P87 O 3811CLK Serial Clock output to BD3811
16 P86 O 3811DATA Serial Data output to BD3811
17 /RESET Reset input
18 XOUT Xtal output
19 VSS GND
20 XIN Xtal input
21 VCC1 Positive power
22 /NMI Positive power
23 /INT2 INT PROTECT Protect Signal input
24 /INT1 INT ESS CS(OP_CE) Chip Enable input from ESS
25 /INT0 I DIR INT1 Interrupt request from DIR
26 TA4IN I 50/60 50Hz/60Hz AC Input
27 P80 O NC(L:Output) Not Used: N. C.
28 P77 O NC(L:Output) Not Used: N. C.
29 P76 O NC(L:Output) Not Used: N. C.
30 P75 I VOL JOG-B VOL encoder Pulse-B input
31 P74 I VOL JOG-A VOL encoder Pulse-A input
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17
S-101
32 P73 O NC(L:Output) Not Used: N. C.
33 P72 O NC(L:Output) Not Used: N. C.
34 RXD2 O NC(L:Output) Not Used: N. C.
35 TXD2 O NC(L:Output) Not Used: N. C.
36 TXD1 SO USB/IPOD_TXD Serial Data output to USB/IPOD
37 VCC1 Positive power
38 RXD1 SI USB/IPOD_RXD Serial Data input from USB/IPOD
39 VSS GND
40 CLK1 O NC(L:Output) Not Used: N. C.
41 P64 O NC(L:Output) Not Used: N. C.
42 TXD0 SO ESS DO(OP_DO) Serial Data output to ESS
43 RXD0 SI ESS DI(OP_DI) Serial Data input from ESS
44 CLK0 SI ESS CK(OP_CLK) Serial Clock input from ESS
45 P60 I ESS ON(BE_ON) ESS Active Signal input.
46 P137 O NC(L:Output) Not Used: N. C.
47 P136 O NC(L:Output) Not Used: N. C.
48 P135 O NC(L:Output) Not Used: N. C.
49 P134 O NC(L:Output) Not Used: N. C.
50 P57 O NC(L:Output) Not Used: N. C.
51 P56 O NC(L:Output) Not Used: N. C.
52 P55 O SELCLK Clock select signal output for digital audio signal from AD1837
53 P54 O DVD ON/OFF DVD Drive Power ON/OFF output. H: Power ON
54 P133 O NC(L:Output) Not Used: N. C.
55 P132 O NC(L:Output) Not Used: N. C.
56 P131 I HP SW HEAD PHONE insert detect signal input. H: Detected
57 P130 O TRIGGER TRIGGER OUT. H:OUT
58 P53 I AUX IN SW Front AUX IN insert detect signal input. H: Detected
59 P52 O EXT_CLK Serial Clock output to control LED.
60 P51 O EXT_DATA Serial Data output to control LED.
61 P50 O NC(L:Output) Not Used: N. C.
62 P127 O VIDEO_A Serial Clock output to control BU2090(VIDEO CONVERT)
63 P126 O VIDEO_B Serial Clock output to control BU2090(VIDEO CONVERT)
64 P125 O VIDEO_C Serial Clock output to control BU2090(VIDEO CONVERT)
65 P47 O VIDEO_D Serial Clock output to control BU2090(VIDEO CONVERT)
66 P46 I VDET_V Detect Composite signal input.
67 P45 I VDET_S Detect S-VIdeo signal input.
68 P44 O BSE DSP Mute Output
69 P43 O ERR MUTE MUTE output at DSP Error.
70 P42 O SUB_SUM Signal output to SW summing control.
71 P41 O MULTI/DIR Select DSP input.
72 P40 O MIX/MULTI Select MIX/MULTI of ESS Output. H:MIX
73 P37 O P.ON/OFF Main POWER ON/STANDBY switching output. H:ON
74 P36 O SCART MUTE MUTE output to SCART Audio Output. H:MUTE
75 P35 O IPOD_ID iPOD ID connect output
76 P34 O SP-RELAY SP RELAY ON/OFF output. H:ON
77 P33 O HP-MUTE MUTE output to HEAD PHONE output. L:MUTE
78 P32 O PRE_MUTE MUTE output to PRE OUT. L:MUTE
79 P31 O AMP_MUTE MUTE output to POWER AMP IC. L:MUTE
80 P124 I TEST MODE CLOSE
81 P123 I TEMP_DETECT Temperature Detect signal input from posister
82 P122 O Not Used: N. C.
83 P121 O DIR RST Reset output to DIR
84 P120 O CLATCH Latch Output to AD1837.
85 VCC2 Positive power
86 P30 O CODEC_RST Reset output to AD1837
87 VSS GND
88 P27 O TU_POWER TUNER Power ON/OFF output. H: Power ON
89 P26 I STEREO "STEREO" indicator input from FM/AM TUNER pack
90 P25 I TUNED "TUNED" detect input from FM/AM TUNER pack
91 P24 O TMUTE MUTE output to TUNER. L:MUTE
92 P23 O SAN CE Chip Enable output to PLL/RDS/VR IC
93 P22 O SAN DI Serial Data input from PLL/RDS/VR IC
94 P21 O SAN CK Serial Clock output to PLL/RDS/VR IC
95 P20 I SAN DO Serial Data output to PLL/RDS/VR IC
96 /INT5 I DFRES Reset Input from ESS. L:RESET
97 P16 O Not Used: N. C.
PIN
NO
Port
Function
Port
setting Port Name Explanation
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TEL 13942296513 QQ 376315150 892498299
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18
S-101
98 /INT3 I REMOTE Remote Control signal input
99 P14 O SYR Reset output to RDS IC
100 P13 I DIR DOUT Serial Data input from DIR.
101 P12 O DIR/CODEC DIN Serial Data output to DIR.
102 P11 O DIR/CODEC CLK Serial Clock output to DIR.
103 P10 O DIR CE Chip Enable output to DIR.
104 P07 O E2P DI Serial Data output to EEPROM
105 P06 I E2P DO Serial Data input from EEPROM
106 P05 O E2P CK Serial Clock output to EEPROM
107 P04 O E2P CS Chip Enable output to EEPROM
108 P03 O USB/IPOD Select USB/iPOD port. H:USB
109 P02 O IPOD_CHARGE iPOD Charge Power ON/OFF output. H:Charge.
110 P01 I IPOD_CONNECT iPOD Connect detect signal input. L:Connected
111 P00 O VPP DSP rom (VPP) write Mode. L: UNLOCK(3.3V)
112 P117 O R/W DSP rom Write/READ.
113 P116 O DSP_IO_POW DSP IO Power Output. H:OFF
114 P115 O DSP_CORE_POW DSP CORE Power Output. H:ON
115 P114 O DSP_OSC_ON DSP OSC On Output.
116 P113 O ROM_RST Reset output to DSP ROM.
117 P112 O DSP_RST Reset output to DSP.
118 P111 I BUSY EPROM EPROM BUSY signal input from DSP.
119 P110 I FLAG3A Control signal input from DSP.
120 AN7 AD DIMMER IN Input signal from sensor of illumination
121 AN6 AD SLIDE SW1 IN Select signal input of Video Signal. H:FHDMI/M:FPROGRE/L:FINTINTERLACE
122 AN5 AD SLIDE SW2 IN Select signal input of Aspect. H:FWIDE M:FLB L:FPS
123 AN4 AD CONNECT IN Detect signal input with DSW-S101. H:FConnected with only Satellite SP. M:FOK
L:FConected with only SW.
124 AN3 AD MODE2 Initial Setting input for Region No of DVD.
125 AN2 AD MODE1 Initial Setting input the destination.(E2,E3)
126 AN1 AD KEY-0 Unit Operation Button input0
127 AVSS GND
128 AN0 AD KEY-1 Unit Operation Button input1
PIN
NO
Port
Function
Port
setting Port Name Explanation
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TEL 13942296513 QQ 376315150 892498299
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19
S-101
ADSP-21266SKSTZ-1C (IC906: 1U-3694)
1
36
37
73
72
108
144 109
TOP VIEW
PIN 1 INDICATOR
Pin Name
LQFP
Pin # Pin Name
LQFP
Pin # Pin Name
LQFP
Pin # Pin Name
LQFP
Pin #
V
DDINT
1V
DDINT
37 V
DDEXT
73 GND 109
CLKCFG0 2 GND 38 GND 74 V
DDINT
110
CLKCFG1 3 RD 39 V
DDINT
75 GND 111
BOOTCFG0 4 ALE 40 GND 76 V
DDINT
112
BOOTCFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113
GND 6 AD14 42 DAI_P11 (SD3A) 78 V
DDINT
114
V
DDEXT
7 AD13 43 DAI_P12 (SD3B) 79 GND 115
GND 8 GND 44 DAI_P13 (SCLK23) 80 V
DDEXT
116
V
DDINT
9V
DDEXT
45 DAI_P14 (SFS23) 81 GND 117
GND 10 AD12 46 DAI_P15 (SD4A) 82 V
DDINT
118
V
DDINT
11 V
DDINT
47 V
DDINT
83 GND 119
GND 12 GND 48 GND 84 V
DDINT
120
V
DDINT
13 AD11 49 GND 85 RESET 121
GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122
FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123
FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V
DDINT
124
AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK45) 89 SPICLK 125
GND 18 V
DDINT
54 V
DDINT
90 MISO 126
V
DDINT
19 GND 55 GND 91 MOSI 127
GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128
V
DDEXT
21 DAI_P3 (SCLK0) 57 V
DDEXT
93 V
DDINT
129
GND 22 GND 58 DAI_P20 (SFS45) 94 V
DDEXT
130
V
DDINT
23 V
DDEXT
59 GND 95 A
VDD
131
AD6 24 V
DDINT
60 V
DDINT
96 A
VSS
132
AD5 25 GND 61 FLAG2 97 GND 133
AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 CLKOUT 134
V
DDINT
27 DAI_P5 (SD1A) 63 V
DDINT
99 EMU 135
GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136
AD3 29 DAI_P7 (SCLK1) 65 V
DDINT
101 TDI 137
AD2 30 V
DDINT
66 GND 102 TRST 138
V
DDEXT
31 GND 67 V
DDINT
103 TCK 139
GND 32 V
DDINT
68 GND 104 TMS 140
AD1 33 GND 69 V
DDINT
105 GND 141
AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142
WR 35 DAI_P9 (SD2A) 71 V
DDINT
107 XTAL 143
V
DDINT
36 V
DDINT
72 V
DDINT
108 V
DDEXT
144
ADSP-21266SKSTZ-1C Terminal Function
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TEL 13942296513 QQ 376315150 892498299
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20
S-101
SP3721A (RL-S874: U2)
SP3721A Terminal Function
DescriptionPin No. Pin Name Type
1, 2 DVDREP, DVDREN I RF Signal Inputs. Differential RF signal attenuator input pins
63 CDRF I RF Signal Inputs. Single-ended RF signal attenuator input pin
59, 60 AIP, AIN I AGC Amplifier Inputs. Differential AGC amplifier input pins
53, 54 DIP, DIN I Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended output buffer
and full wave rectifier
32 FDCHG# I
Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches. A low
level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for
the MIRR bottom hold circuit. (open high)
49 HOLD1 I Hold Control. A TLL compatible control pin which, when pulled high, disables the RF AGC charge
pump and holds the RF AGC amplifier gain at its present value. (open high)
11~14 D, C, B, A I Photo Detector Interface Inputs. Inputs from the main beam Photo detector matrix outputs
5~8 A2, B2, C2, D2 I Photo Detector Interface Inputs. AC coupled inputs for the DPD from the main beam Photo
detector matrix outputs
15~16 F, E I CD tracking Error Inputs. Inputs from the CD photo detector error outputs.
3~4 PD1, PD2 I CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs
40 MEI I Mirror Envelope Inputs. The SIGO envelope input pin
35 MIN I RF signal Input for Mirror. AC coupled inputs for the mirror detection circuit from the pull-in signal
output. (PI)
21 DVDPD I APC Input. DVD APC input pin from the monitor photo diode
23 CDPD I APC Input. CD APC input pin from the monitor photo diode
25 LDON# I APC Output On/Off. APC output control pin. A low level activates the LD output. (open high)
61, 62 ATON/ATOP O Differential Attenuator Output. Attenuator outputs
51, 52 FNN, FNP O Differential Normal Output. Filter normal outputs
57 SIGO O Single Ended Normal Output. Single-ended RF output
64 CDRFDC O CD RF Signal Output. Single ended CD RF summing output
42 FE O Focusing Error Signal Output. Focus error output reference to VCI
41 TE O Tracking Error Signal Output. Tracking error output reference to VCI
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MLPF
MEVO
MIN
PI
DFT
TPH
MEV
MEI
TE
FE
CE
LCN
LCP
SCLK
SDATA
SDEN
E
F
A
B
C
D
CN
CP
D2
C2
B2
A2
PD2
PD1
DVDRFN
DVDRFP
32313029282726252423222120191817
49505152535455565758596061626364
HOLD1
VNA
FNN
FNP
DIP
DIN
RX
BYP
SIGO
VPA
AIP
AIN
ATON
ATOP
CDRF
CDRDDC
FDCHG#
VIB
VIP
VIIRR
VPB
VCI
VC
LDON#
CDLD
CDPD
DVDLD
DVDPD
VNB
NC
VCI2
CDTE
TOP VIEW
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Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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