Dialog Semiconductor DA6021 User manual

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
1 of 224
www.dialog-semiconductor.com
1. General Description
The DA6021 PMIC is a monolithic single chip power management IC for Intel® Atom™ Z3000 processor. It
provides all power supplies for tablet PC’s and can also be used in multiple embedded applications as well as
Netbooks and Nettops. It is designed to support platforms based on Intel’s Z3000 Atom processor series,
including DDR3 memory and various peripherals.
Integrated power management
Dialog Semiconductor’s new DA6021 uses a single supply voltage at a wide range of input voltage and provides
low noise supplies to all SoC voltage domains, DDR3 memory and many peripherals.
The DA6021 integrates 6 high performance low dropout (LDO) voltage regulators using Dialog’s patented Smart
Mirror™ technology for very low quiescent current. It includes 11 internal power switches and the control logic for
9 external switching devices. These include in-rush current control for platform power distribution simplification.
Six fully integrated high efficiency DC-DC buck converters provide current to Intel Atom platform’s various low
voltage domains as well as to the memory and the peripherals. Two buck-boost and one boost converter also
supply energy for the platform. All nine regulators are designed to support external component height of 1mm.
Ultra flexible power sequencer
The ultra-flexible power sequencer takes care of the complete platform start-up, state-transitioning and power-
down procedure. The DA6021 operates autonomously and reduces the power consumption when entering
stand-by or power down mode. The DA6021 is fully programmable and allows adaption to all Intel Atom
processor Z3000 and platform sequences. The OTP programmed power sequence is copied into operational
registers during power-up. Those registers can be overwritten by EEPROM after initial OTP copy routine or via
operational processor.
Auxiliary function
An analogue to digital converter (ADC) with 10-bit resolution combined with a multi-channel input multiplexer
allows measurement of the input supply voltage, battery ID, PMIC die temperature as well as 5 battery pack &
system temperatures. The number of external components is significantly reduced due to the integration of 16
GPIO’s, 3 channel PWM output signal generators, a multi-input detector with a charger control as well as a
programmable IRQ controller.
2. Key Features
■Two high efficiency buck converters with
integrated SVID interface running IMVP-7
protocol. These two quad phase DC/DC
regulators generate the voltages for CPU and
graphic cores
■One dual phase buck regulator for memory
supply supporting DDR3-L and -LP memory types
■3 single phase buck regulators supplying 1.0V,
1.05V and 1.8V towards the platform
■2 buck-boost converters generating 2.85V and
3.3V for the platform even if the input supply is
down to 2.7V
■Boost converter providing 5V for the USB
components
■3 LDOs with fixed output voltage
■2 LDO with programmable output voltage
■1 push-pull LDO used for DDR3 address line
termination
■11 integrated power rail switching devices
■9 external power rail switching devices
■Ultra flexible power sequencer programmable via
OTP/ EEPROM and register
■I2C communication interface for SoC access
■EEPROM interface for optional OTP over-writing
■16 general purpose I/Os with alternate functions
■16 channel 10-bit ADC including conditioning
circuits and programmable flexible sequencing for
automatic and manual measurements
■System voltage and temperature monitoring,
supervising
■Programmable IRQ controller
■1-wire digital battery interface including 2-wire
conversion
■3 channel PWM signal generation, flexible
frequency and duty cycle programmable
■Input power source detection, included with
charger control

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
2 of 224
www.dialog-semiconductor.com
Contents
1. General Description ..............................................................................................................................1
2. Key Features..........................................................................................................................................1
3. Revision History ................................................................................................................................. 13
4. Overview.............................................................................................................................................. 16
5. Block Diagram .................................................................................................................................... 17
Overview Diagram...................................................................................................................... 175.1
Detailed Block Diagram.............................................................................................................. 185.2
6. Operating Conditions......................................................................................................................... 19
Absolute Maximum Ratings ....................................................................................................... 196.1
Recommended Operating Conditions........................................................................................ 196.2
7. Ordering Information.......................................................................................................................... 20
8. Pinning Information............................................................................................................................ 21
9. Operating Conditions......................................................................................................................... 26
System Control Signals.............................................................................................................. 269.1
VDCIN_SENSE.............................................................................................................. 269.1.1
ACPRESENT................................................................................................................. 269.1.2
VBUS_SENSE............................................................................................................... 269.1.3
CHGDET_B.................................................................................................................... 269.1.4
VSYS1/2......................................................................................................................... 269.1.5
CHGSTAT...................................................................................................................... 269.1.6
ILIM[1:0]......................................................................................................................... 269.1.7
I2C_CLK......................................................................................................................... 269.1.8
I2C_DATA...................................................................................................................... 269.1.9
IRQ................................................................................................................................. 269.1.10
I2CM_CLK...................................................................................................................... 269.1.11
I2CM_DATA................................................................................................................... 269.1.12
PWRBTNIN_B................................................................................................................ 269.1.13
PWRBTN_B................................................................................................................... 269.1.14
PLTRST_B..................................................................................................................... 279.1.15
SLP_S0iX_B .................................................................................................................. 279.1.16
SLP_S3_B...................................................................................................................... 279.1.17
SLP_S4_B...................................................................................................................... 27
9.1.18
RSMRST_B.................................................................................................................... 279.1.19
DRAMPWROK............................................................................................................... 279.1.20
VCCAPWROK................................................................................................................ 279.1.21
COREPWROK............................................................................................................... 279.1.22
SUSPWRDNOK............................................................................................................. 279.1.23
BATLOW_B.................................................................................................................... 279.1.24
SUSCLK......................................................................................................................... 289.1.25
THERMTRIP_B.............................................................................................................. 289.1.26
PROCHOT_B................................................................................................................. 289.1.27
SDMMC3_1P8_EN........................................................................................................ 289.1.28

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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SDMMC3_PWR_EN_B.................................................................................................. 289.1.29
MODEM_OFF_B............................................................................................................ 289.1.30
SDWN_B........................................................................................................................ 289.1.31
USBRST_B.................................................................................................................... 289.1.32
GPIOs ............................................................................................................................ 289.1.33
Burst Control Unit........................................................................................................... 299.1.34
PWM[2:0] ....................................................................................................................... 299.1.35
DISPLAY........................................................................................................................ 299.1.36
ADC................................................................................................................................ 299.1.37
DA6021 Power States................................................................................................................ 309.2
SoC Power States...................................................................................................................... 32
9.3
SOC_S0 State ............................................................................................................... 329.3.1
SOC S0iX State ............................................................................................................. 339.3.2
SOC S3 State................................................................................................................. 349.3.3
SOC S4 State................................................................................................................. 359.3.4
Truth Table of Sleep Signals and DA6021 Final Power States..................................... 359.3.5
DA6021 Power State Transitions and Sleep Signals .................................................... 369.3.6
Register File and Address Range.............................................................................................. 379.4
Slave ID versus DA6021 Pages .................................................................................... 379.4.1
10. Power Controller State Machine ....................................................................................................... 38
Overview .................................................................................................................................... 3810.1
Power State Transitions............................................................................................................. 3810.2
Sequencing.................................................................................................................... 39
10.2.1
DA6021 Power Sequences........................................................................................................ 4010.3
Cold Boot ....................................................................................................................... 4110.3.1
Warm Reset Sequence.................................................................................................. 4610.3.2
Enter SOC S0iX Mode................................................................................................... 4610.3.3
Exit SOC S0iX Mode...................................................................................................... 4910.3.4
Enter SOC S3 Mode...................................................................................................... 5210.3.5
Exit SOC S3 Mode......................................................................................................... 5410.3.6
Enter SOC S4 Mode...................................................................................................... 5510.3.7
Exit SOC S4 Mode......................................................................................................... 5610.3.8
Cold Off.......................................................................................................................... 5710.3.9
Modem Reset Sequence ............................................................................................... 6410.3.10
PMIC Resets.............................................................................................................................. 6510.4
Wake Events .............................................................................................................................. 6510.5
11. Platform Power Domains................................................................................................................... 66
Power Domains Summary ......................................................................................................... 6611.1
Voltage Rail ON/OFF On Various Power States........................................................................ 6811.2
PMIC Current Consumption in Various States........................................................................... 6811.3
Voltage Rail Control Mechanism................................................................................................ 6911.4
SVID Interface............................................................................................................................ 6911.5
SVID DC Electrical Parameters..................................................................................... 6911.5.1
VCLK Timing Parameters.............................................................................................. 7011.5.2
Data Sampling and Timing............................................................................................. 7111.5.3
SVID Command Set....................................................................................................... 7311.5.4

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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SVID Register Set.......................................................................................................... 7411.5.5
VID DAC Table .............................................................................................................. 7811.5.6
Low Power State Control Signals .................................................................................. 7911.5.7
Power Supplies .......................................................................................................................... 7911.6
DC/DC Buck Regulator VCC ......................................................................................... 7911.6.1
DC/DC Buck Regulator VNN ......................................................................................... 8211.6.2
DC/DC Buck Regulator V1P0A...................................................................................... 8411.6.3
DC/DC Buck Regulator V1P05S.................................................................................... 8911.6.4
DC/DC Buck Regulator V1P8_A.................................................................................... 9211.6.5
DC/DC Buck Regulator VDDQ....................................................................................... 9811.6.6
Power Rail VSYSU ...................................................................................................... 103
11.6.7
Power Rail VSYS_SX .................................................................................................. 10411.6.8
Power Rail VSYS_S..................................................................................................... 10511.6.9
Buck Boost Regulator V2P85S.................................................................................... 10511.6.10
Buck Boost Regulator V3P3A...................................................................................... 10911.6.11
Boost Regulator V5P0S............................................................................................... 11311.6.12
VLP Low Power Regulator........................................................................................... 11711.6.13
Current Monitor ........................................................................................................................ 11811.7
VCC/VNN Current vs ADC data................................................................................... 11911.7.1
V1P0A Current vs ADC data........................................................................................ 12011.7.2
V1P5S Current vs ADC data........................................................................................ 12111.7.3
VDDQ Current vs ADC data ........................................................................................ 12211.7.4
12. I2C Interface...................................................................................................................................... 123
Overview .................................................................................................................................. 12312.1
Slave Addresses ...................................................................................................................... 12312.2
Protocol .................................................................................................................................... 12312.3
Electrical Requirements ........................................................................................................... 12412.4
13. External EEPROM Controller........................................................................................................... 125
Overview .................................................................................................................................. 12513.1
Electrical Characteristics.......................................................................................................... 12513.2
Functions.................................................................................................................................. 12513.3
14. Power Source Detection.................................................................................................................. 126
Overview .................................................................................................................................. 12614.1
VBAT Power Source Detection................................................................................................ 12614.2
Battery Voltage Monitor & Removal / Insertion Detection ........................................... 126
14.2.1
Battery Pack Interface.................................................................................................. 12714.2.2
Battery Presence Detection......................................................................................... 12814.2.3
BSI Sensing ................................................................................................................. 12814.2.4
Digital Battery Communications................................................................................... 12814.2.5
System Voltage Monitor............................................................................................... 12914.2.6
VBUS Power Source Detection................................................................................................ 12914.3
VDCIN Power Source Detection Comparators ........................................................................ 13014.4
BATLOW Definition.................................................................................................................. 13114.5
Power Source Detection Events .............................................................................................. 13214.6
Wake-Up Logic......................................................................................................................... 13214.7

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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www.dialog-semiconductor.com
DA6021 Catastrophic and Critical Events................................................................................ 13314.8
Power Source Registers .......................................................................................................... 13414.9
15. Analog–to–Digital Converter........................................................................................................... 139
Electrical Characteristics.......................................................................................................... 13915.1
Analog Overview...................................................................................................................... 14015.2
ADC Measurement Support......................................................................................... 14115.2.1
Preamplifier.................................................................................................................. 14115.2.2
ADC Sequencer ....................................................................................................................... 14215.3
Manual Measurements ................................................................................................ 14215.3.1
Reference Source........................................................................................................ 14515.3.2
Event and Status Generation....................................................................................... 14515.3.3
Result register.............................................................................................................. 14615.3.4
CH0: Battery Pack Voltage.......................................................................................... 14615.3.5
CH1: Battery ID resistance .......................................................................................... 14615.3.6
CH2: Die Temperature................................................................................................. 14615.3.7
CH3-4: Battery Pack Temperature .............................................................................. 14615.3.8
CH5-7: System Temperature Thermistor..................................................................... 14715.3.9
CH8-12: VR Current Measurement ............................................................................. 14715.3.10
CH8: VSYS Voltage Measurements............................................................................ 14715.3.11
ADC Registers.......................................................................................................................... 14815.4
16. System Voltage & Temperature Monitoring................................................................................... 153
Overview .................................................................................................................................. 15316.1
SVTM Block Diagram............................................................................................................... 15816.2
Functional Description.............................................................................................................. 15816.3
VSYS Input Trip Points for ADC Measurement ........................................................... 15816.3.1
VSYS Related Output Control...................................................................................... 16016.3.2
Under- & Over- Voltage Condition............................................................................... 16516.3.3
Permanent Temperature Monitoring............................................................................ 16516.3.4
Temperature Monitoring via ADC ................................................................................ 16616.3.5
Critical Thermal Events............................................................................................................ 17516.4
System Temperature ................................................................................................... 17516.4.1
Battery Critical Temperature........................................................................................ 17616.4.2
DA6021 die Temperature............................................................................................. 17616.4.3
Thermal Monitoring Event Table.................................................................................. 17716.4.4
Backup Battery Management................................................................................................... 177
16.5
Backup Battery Charger............................................................................................... 17816.5.1
Power Consumption..................................................................................................... 17816.5.2
17. General Purpose IOs........................................................................................................................ 179
Overview .................................................................................................................................. 17917.1
Analog Block, Control & Data Signals...................................................................................... 17917.2
GPIO Digital Features.............................................................................................................. 18017.3
De-Bouncing ................................................................................................................ 18017.3.1
Status Register ............................................................................................................ 18017.3.2
Interrupt Functionality .................................................................................................. 18017.3.3
Analogue Mode........................................................................................................................ 18017.4

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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www.dialog-semiconductor.com
Alternative Functions................................................................................................................ 18017.5
Defining an Output Value......................................................................................................... 18117.6
Supported Alternate Functions................................................................................................. 18117.7
GPIO0P0 –BATIDIN ................................................................................................... 18117.7.1
GPIO0P1 –BATIDOUT ............................................................................................... 18117.7.2
GPIO0P2 –GPIO0P7-PCSMCNT............................................................................... 18117.7.3
GPIO1P0 –UIBTN_B .................................................................................................. 18117.7.4
GPIO1P1 –CLK32OUT............................................................................................... 18117.7.5
GPIO1P2 –TRIG1....................................................................................................... 18117.7.6
GPIO1P3 –TRIG2....................................................................................................... 18117.7.7
GPIO1P4 –WAKE1..................................................................................................... 181
17.7.8
GPIO1P5 –WAKE2..................................................................................................... 18117.7.9
Electrical Characteristics.......................................................................................................... 18217.8
GPIO Registers........................................................................................................................ 18217.9
18. External Battery Charger Control ................................................................................................... 188
Overview .................................................................................................................................. 18818.1
Charger Current Limit............................................................................................................... 18818.2
External Charger Control Signals............................................................................................. 18818.3
Battery Charger Registers........................................................................................................ 18918.4
19. Interrupt Controller........................................................................................................................... 190
Overview .................................................................................................................................. 19019.1
First Level Interrupt .................................................................................................................. 19019.2
Second Level Interrupt............................................................................................................. 19019.3
Critical Race Condition (set vs. clear)...................................................................................... 19319.4
Interrupt Controller Registers................................................................................................... 19319.5
20. Power Button & Utility Button......................................................................................................... 195
Overview .................................................................................................................................. 19520.1
Power/Utility Button Block Diagram ......................................................................................... 19520.2
PWRBTNIN_B Electrical Parameters ...................................................................................... 19520.3
Power Button............................................................................................................................ 19620.4
Power Button Cold Boot Flow Diagram.................................................................................... 19620.5
Force a Cold Off Sequence...................................................................................................... 19720.6
Force Cold Off Flow Diagram................................................................................................... 19720.7
UIBTN_B .................................................................................................................................. 19720.8
Power Button Registers............................................................................................................ 198
20.9
21. Pulse Width Modulation Generation............................................................................................... 200
Overview .................................................................................................................................. 20021.1
Functional Description.............................................................................................................. 20021.2
PWM Output Signals................................................................................................................ 20021.3
PWM Registers ........................................................................................................................ 20021.4
22. Panel Control .................................................................................................................................... 203
Overview .................................................................................................................................. 20322.1
Functional Description.............................................................................................................. 20322.2
23. Debug Ports ...................................................................................................................................... 204
SVID Debug port ...................................................................................................................... 20423.1

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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I2C Debug port......................................................................................................................... 20523.2
24. Register Map..................................................................................................................................... 207
25. Package Information ........................................................................................................................ 210
DA6021 Package Details ......................................................................................................... 21025.1
Pin Description, Pin Out............................................................................................... 21025.1.1
Ball Order..................................................................................................................... 21025.1.2
DA6021 325 Pin FCBGA Package........................................................................................... 21825.2
Component Marking................................................................................................................. 21925.3
Package Outline....................................................................................................................... 21925.4
Soldering Profile....................................................................................................................... 22025.5

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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www.dialog-semiconductor.com
Figures
Figure 1: Overview Diagram....................................................................................................................... 17
Figure 2: Detailed Block Diagram............................................................................................................... 18
Figure 3: Maximum Allowed Peak Power................................................................................................... 20
Figure 4: DA6021 Power States................................................................................................................. 30
Figure 5: VSYS Areas................................................................................................................................. 31
Figure 6: SoC Power States....................................................................................................................... 32
Figure 7: Address Range and Pages ......................................................................................................... 37
Figure 8: State Transitions.......................................................................................................................... 38
Figure 9: Cold Boot Power Sequencing Diagram, Valid Battery Insertion ................................................. 43
Figure 10: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=1)........................................................ 47
Figure 11: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=0)........................................................ 48
Figure 12: Exit S0iX Sequencing Diagram (VCCAPWROKCFG=1) .......................................................... 50
Figure 13: Exit S0iX Sequencing Diagram (VCCAPWROKCFG=0) .......................................................... 51
Figure 14: Enter S3 Sequencing Diagram.................................................................................................. 53
Figure 15: Exit S3 Sequencing Diagram .................................................................................................... 54
Figure 16: Enter S4 Sequencing Diagram.................................................................................................. 55
Figure 17: Exit S4 Sequencing Diagram .................................................................................................... 56
Figure 18: Cold Off Power Sequencing Diagram (SUSPWRDNACKCFG=1) ........................................... 58
Figure 19: Power Button forced Cold Off.................................................................................................... 62
Figure 20: Catastrophic Event (except VSYSOVP) Shutdown Sequence ................................................. 63
Figure 21: VSYSOVP Shutdown Sequence............................................................................................... 63
Figure 22: Modem Reset Sequencing Diagram ......................................................................................... 64
Figure 23: Definition of VHYS..................................................................................................................... 70
Figure 24: Measurement Points for VCLK.................................................................................................. 71
Figure 25: SoC Driving Timing Definition ................................................................................................... 72
Figure 26: DA6021 Driving Timing Definition ............................................................................................. 72
Figure 27: VCC Block Diagram .................................................................................................................. 79
Figure 28: VCC Timings ............................................................................................................................. 80
Figure 29: VCC Efficiency........................................................................................................................... 81
Figure 30: Buck VNN Block Diagram ......................................................................................................... 82
Figure 31: VNN Efficiency........................................................................................................................... 83
Figure 32: V1P0A Power Rail Block Diagram ............................................................................................ 84
Figure 33: V1P0A Efficiency....................................................................................................................... 86
Figure 34: Buck V1P05S Block Diagram.................................................................................................... 89
Figure 35: V1P05S Efficiency..................................................................................................................... 91
Figure 36: Buck V1P8A Power Rail Block Diagram................................................................................... 92
Figure 37: V1P8A Efficiency....................................................................................................................... 93
Figure 38: VDDQ Power Domain Block Diagram....................................................................................... 98
Figure 39: VDDQ Efficiency...................................................................................................................... 100
Figure 40: Buck Boost V2P85S Power Domain Block Diagram............................................................... 105
Figure 41: V2P85S Efficiency................................................................................................................... 107
Figure 42:V3P3A Power Domain Block Diagram..................................................................................... 109
Figure 43:V3P3A Efficiency...................................................................................................................... 110
Figure 44:V5P0S Power Domain Block Diagram..................................................................................... 113
Figure 45:V5P0S Efficiency...................................................................................................................... 114
Figure 46: Current Measurement Tolerance Boundary............................................................................ 118
Figure 47: VCC/VNN ADC Current Coding.............................................................................................. 119
Figure 48: Typical VCC Current Sensing Error ........................................................................................ 119
Figure 49: Typical VNN Current Sensing Error ........................................................................................ 119
Figure 50: V1P0A ADC Current Coding ................................................................................................... 120
Figure 51: Typical V1P0A Current Sensing Error..................................................................................... 120
Figure 52: V1P05S ADC Current Coding................................................................................................. 121
Figure 53: Typical V1P05S Current Sensing Error................................................................................... 121
Figure 54: VDDQ ADC Current Coding.................................................................................................... 122
Figure 55: Typical VDDQ Current Sensing Error ..................................................................................... 122
Figure 56: I2C Fast Speed Write.............................................................................................................. 123

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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www.dialog-semiconductor.com
Figure 57: I2C Fast Speed Read.............................................................................................................. 124
Figure 58: High Speed Write .................................................................................................................... 124
Figure 59: High Speed Read.................................................................................................................... 124
Figure 60: VBAT Input Detection.............................................................................................................. 126
Figure 61: Battery Single Wire Block Diagram for Analog sensing, Digital communication..................... 127
Figure 62: VSYS Valid Input Power Detection ......................................................................................... 129
Figure 63: USB Detection......................................................................................................................... 129
Figure 64: DCIN Detection........................................................................................................................ 130
Figure 65: Valid Battery Thresholds ......................................................................................................... 131
Figure 66: SVTM Block Diagram.............................................................................................................. 158
Figure 67: BCU Warning Flag Generation................................................................................................ 161
Figure 68: VSYS Trip Points Flag Logic................................................................................................... 164
Figure 69 : GPIO Block Diagram.............................................................................................................. 179
Figure 70: 1st Level Interrupts.................................................................................................................. 190
Figure 71 : Power/Utility Button Detection Logic...................................................................................... 195
Figure 72: Power Button Boot Flow Diagram........................................................................................... 196
Figure 73: Power Button Cold Off Flow Diagram ..................................................................................... 197
Figure 74: SVID Debug Port Bus Diagram............................................................................................... 204
Figure 75: I2C Debug Port Bus Diagram.................................................................................................. 205
Figure 76: Package Outline Drawing and Dimensions............................................................................. 220

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
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www.dialog-semiconductor.com
Tables
Table 1: DA6021 Absolute Maximum Ratings............................................................................................ 19
Table 2: DA6021 Recommended Operating Conditions............................................................................ 19
Table 3: Abbreviations of Validation Status................................................................................................ 20
Table 4: Pin Description.............................................................................................................................. 25
Table 5: Pin Type Definition........................................................................................................................ 25
Table 6 : G3 State Transition...................................................................................................................... 31
Table 7: SOC_G3 State Transition............................................................................................................. 31
Table 8:SOC S0 State Transition ............................................................................................................... 33
Table 9: SOC S0iX State Transition........................................................................................................... 34
Table 10: SOC S3 State Transition ............................................................................................................ 34
Table 11: SOC S4 State Transition ............................................................................................................ 35
Table 12: Truth Table of Sleep Signals and DA6021 Final Power States.................................................. 35
Table 13: DA6021 State Transition and Sleep Signals .............................................................................. 36
Table 14: Slave ID versus DA6021 Storage Page ..................................................................................... 37
Table 15:U2 & D2 Event Generation Table................................................................................................ 39
Table 16: Cold Boot Triggers...................................................................................................................... 42
Table 17: Truth Table of Cold Boot Triggers.............................................................................................. 42
Table 18: Cold Boot Timings...................................................................................................................... 45
Table 19: Enter S0iX timing........................................................................................................................ 49
Table 20: Exit S0iX timing........................................................................................................................... 52
Table 21: Cold Off Triggers ........................................................................................................................ 57
Table 22: Cold Off Sequencing Timing....................................................................................................... 61
Table 23: Catastrophic Event (except VSYSOVP) Shutdown Sequence .................................................. 63
Table 24: VSYSOVP Shutdown Timing...................................................................................................... 63
Table 25: Modem Reset Timing Intervals................................................................................................... 64
Table 26 : PMIC Reset Sources................................................................................................................. 65
Table 27: Power Domains .......................................................................................................................... 67
Table 28: Status Power Domains............................................................................................................... 68
Table 29: PMIC Current Consumption ....................................................................................................... 68
Table 30: VCC & VNN Addresses.............................................................................................................. 69
Table 31: SVID DC Electrical Characteristics............................................................................................. 69
Table 32: SVID buffer AC Electrical Parameters........................................................................................ 70
Table 33: VCLK AC Timing Parameters..................................................................................................... 70
Table 34: SVID Supported Commands...................................................................................................... 73
Table 35: SVID Supported Registers ......................................................................................................... 75
Table 36: VID Values.................................................................................................................................. 78
Table 37: Electrical Parameters for BUCK_VCC ....................................................................................... 81
Table 38: Electrical Parameters for BUCK_VNN ....................................................................................... 83
Table 39: Electrical Parameter for BUCK_V1P0A...................................................................................... 85
Table 40: V1P0A Truth Table..................................................................................................................... 87
Table 41: V1P0S_EN Truth Table.............................................................................................................. 87
Table 42: V1P0SX_EN Truth Table............................................................................................................ 88
Table 43: VDDQ_VTT Truth Table............................................................................................................. 89
Table 44: Electrical Parameter for VDDQ_VTT.......................................................................................... 89
Table 45: Electrical Parameter for BUCK_V1P05S.................................................................................... 90
Table 46: V1P05S Truth Table................................................................................................................... 92
Table 47: Electrical Parameter for BUCK_V1P8A...................................................................................... 93
Table 48: V1P8A Truth Table..................................................................................................................... 94
Table 49: V1P8U_EN_B Truth Table ......................................................................................................... 95
Table 50: V1P8S Power Switch Specification............................................................................................ 95
Table 51: V1P8S Truth Table..................................................................................................................... 95
Table 52: V1P8S Power Switch Specification............................................................................................ 96
Table 53: V1P8SX Truth Table................................................................................................................... 96
Table 54: Electrical Parameter for V1P2A.................................................................................................. 97
Table 55: Electrical Parameter for VREFDQ1/2......................................................................................... 98
Table 56: Electrical Parameter for BUCK_VDDQ ...................................................................................... 99

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
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Table 57: VDDQ Truth Table.................................................................................................................... 101
Table 58: V1P2S Power Switch Specification.......................................................................................... 101
Table 59: Electrical Parameter for V1P2S LDO ....................................................................................... 101
Table 60: V1P2S Truth Table................................................................................................................... 102
Table 61: V1P2SX Power Switch Specification........................................................................................ 102
Table 62: V1P2SX Truth Table................................................................................................................. 103
Table 63: VSYSU_EN_B Truth Table....................................................................................................... 103
Table 64: VSYSSX_EN_B Truth Table .................................................................................................... 104
Table 65: VSYS_S Power Switch Specification ....................................................................................... 105
Table 66: VSYS_S Truth Table................................................................................................................ 105
Table 67: Electrical Parameter for BUCKBOOST_V2P85S..................................................................... 106
Table 68: V2P85S Truth Table................................................................................................................. 107
Table 69: V2P85SX Power Switch Specification...................................................................................... 108
Table 70: V2P85SX Truth Table............................................................................................................... 108
Table 71: Electrical Parameter for BUCKBOOST_V3P3A....................................................................... 110
Table 72: V3P3A Truth Table................................................................................................................... 111
Table 73: V3P3U_EN_B Truth Table ....................................................................................................... 111
Table 74: V3P3S_EN_B Truth Table........................................................................................................ 112
Table 75: VUSBPHY Power Switch Specification.................................................................................... 112
Table 76: VSDIO Power Switch Specification.......................................................................................... 113
Table 77: VSDIO Output Voltage Selection.............................................................................................. 113
Table 78: Electrical Parameter for BOOST_V5P0S................................................................................. 114
Table 79: V5P0S Truth Table................................................................................................................... 115
Table 80: VHOST_EN Truth Table........................................................................................................... 116
Table 81: VHOST External Power Switch Driver Capability..................................................................... 116
Table 82: VBUS_EN Truth Table ............................................................................................................. 116
Table 83: VBUS External Switch Driver Capability .................................................................................. 116
Table 84: VHDMI Power Switch Specification.......................................................................................... 117
Table 85: VHDMI Truth Table................................................................................................................... 117
Table 86: Electrical Parameter for LDO_LP............................................................................................. 118
Table 87: Current Measurement Resolution............................................................................................. 118
Table 88: I2C Slave Addresses................................................................................................................ 123
Table 89: I2C Signal Electrical Specification............................................................................................ 124
Table 90: EEPROM Signal Electrical Specifications................................................................................ 125
Table 91: BATID Comparator Threshold.................................................................................................. 127
Table 92: VBAT Removal Comparator Threshold.................................................................................... 127
Table 93: BATID Electrical Specification.................................................................................................. 128
Table 94: Digital Battery Interface Specification....................................................................................... 128
Table 95: VSYSREF Definition................................................................................................................. 129
Table 96: VBUS Detection, Analog Electrical Parameters....................................................................... 130
Table 97: VDCIN Detection, Analog Electrical Parameters...................................................................... 131
Table 98: System Wake-Up Condition ..................................................................................................... 132
Table 99: ADC Electrical Charakteristics.................................................................................................. 140
Table 100: ADC Channel Overview.......................................................................................................... 141
Table 101: ADC Channel Data Format..................................................................................................... 142
Table 102: VSYS Event Table.................................................................................................................. 165
Table 103: Thermal Monitoring Events..................................................................................................... 177
Table 104: GPIO Direction Configuration................................................................................................. 180
Table 105: GPIO Pull-up/Pull-down Configuration................................................................................... 180
Table 106: GPIO 1.8V Electrical Specification......................................................................................... 182
Table 107: GPIO 3.3V Electrical Specification......................................................................................... 182
Table 108: External Charger Current Limits............................................................................................. 188
Table 109: Charger Control Pins.............................................................................................................. 188
Table 110: Second Level Interrupts.......................................................................................................... 193
Table 111: PWM Output Signals .............................................................................................................. 200
Table 112: SVID Debug Port Truth Table................................................................................................. 204
Table 113: I2C Debug Port Truth Table ................................................................................................... 206
Table 114: DA6021 Register Map ............................................................................................................ 209

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
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Table 115: DA6021 Ball Order ................................................................................................................. 217
Table 116: Soldering Profile ..................................................................................................................... 221
Table 117: DA6021 BOM Proposal .......................................................................................................... 223

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
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3. Revision History
Version
Date
Description
2.A
2012.09.08
First preliminary datasheet
2.B
2012.09.26
Updated ordering information
Updated package outline drawing
2.C
2013.05.03
Corrected VSYSU pin types table 4: Pin Description
Updated figure 16: Buck VNN Block Diagram
Corrected IMAX value in chapter 11.5.2.1
Updated electrical parameters for buck VCC
Updated electrical parameters for buck VNN
Updated electrical parameters for buck V1P0A
Updated electrical parameters for buck V1P05S
Updated electrical parameters for buck V1P8A
Updated electrical parameters for buck VDDQ
Updated electrical parameters for buck boost V2P85S
Updated electrical parameters for buck boost V3P3A
Updated electrical parameters for boost V5P0S
Corrected table 51 naming
VDCIN replaced by VDCIN_SENSE
VBUS replaced by VBUS_SENSE
Updated SVID Status1 registers
Included chapter 23 “Debug Ports”
Updated ICCMAX alert in Status1 SVID register
Included chapter 11.6 “Current Monitor” including typical current sensing
errors on the 5 power rails
Removed SVID registers 0x07 and 0x0A
Added SVID registers 0x14, 0x15, 0x1D, 0x1E, 0x1F, 0x20, 0x2D, 0x2E
and 0x2F
Updated chapter 10.3 “DA6021 Power Sequences”, included timing
diagrams and tables
Added efficiency curves for all DC/DC regulators
Updated descriptions of internal and external switches
Updated PBCONFIG register with new feature of programmable power
button debounce time
Updated PBSTATUS register with new feature disabling the power
button detection for a programmable time
Updated register map chapter 24
Updated the content of the following registers:
IRQLVL1, MIRQLVL1, VCRIT_CFG, EVENTMAN1, MEVENTMAN1,

DA6021
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Version
Date
Description
MANCONV1, TSENABLE,TS_CRIT_ENABLE, A0_ST, A1_ST and
CRIT_ST,
2.D
2013.05.28
Added information how electrical parameters are validated
Included SVID Buffer AC parameters
Platform SVID bus timing requirements
Included maximum power path routing DC resistance requirement on
several rails
Added further electrical parameters for Vref
Included electrical parameters for VHOST & VBUS output signal
Updated ADC channel allocation
Updated several register names and dedicated bits
Included state transitions tables and conditions
Added detailed information on critical events including timings
Included current monitor function details
Added charger control pin details
Several editorial updates
2.E
2013.07.15
Updated MPWRSRCIRQS0 register content
Corrected MPWRSRCIRQSX register content
Updated reset value of register LOWBATDET0
Corrected reset value of register LOWBATDET1
Updated and corrected the description of the reset source register
RESETSCR1
Added register PWRSEQCFG into register map chapter 24
Corrected reset value of register MADCIRQ1
Added S0iX_SVID register in table 34 SVID Supported Registers
Corrected number of output caps for VDDQ, V3P3A & V5P0S
Corrected table 76 SDIO voltage selection
Updated bit naming of SPWRSRC register
Renamed MSYS3ALRTx by MSYS2ALRTx in MTHERMIRQ0/1 register
Updated reset value of VWARNA_CFG register
Corrected description of MBCUIRQ register
2.F
2013.12.13
Changed “new Intel Atom processor” into “Intel Atom processor Z3000”
Updated the BOM
Updated figure 11: Enter S0iX Sequencing Diagram
(VCCAPWROKCFG=0)
2.G
2013.12.17
Added note regarding behaviour V2P85S chapter 11.6.10

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
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Data Sheet
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Version
Date
Description
3.A
2013.01.27
Version after receiving Intel’s PRQ statement
Editorial changes in the register descriptions
Corrected typo in VHDMI_CTRL register
Updated BOM, cost and size optimized

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
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Data Sheet
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4. Overview
DA6021 features:
Power sequencer & System control: DA6021 includes an ultra-flexible power sequencer
programmable via OTP during manufacturing process and modifiable via external EEPROM data. It
controls the DA6021 blocks, the power sequences, the programmed ADC sequence, interacts with
the SoC and the peripherals
Supply Sources
6 Buck Regulators
2 Buck-Boost Regulators
1 Boost Regulator
6 LDO Regulators
11 internal power rail switches
9 external power rail switches
2 Power mux switches where the supply source can be selected
Communication Interfaces
I2C (slave device) mastered from the SoC
Handshake/control signals from/towards the SoC and peripherals
SVID (slave device) mastered from the SoC, but capable of interrupt from the PMIC
I2C (master device) or EEPROM Interface, used to read EEPROM during first power up.
Input Source Power Detection: DA6021 will detect connected power sources and provide such
information towards the SoC and/or charger. VBAT, VBUS_SENSE, VDCIN_SENSE and VSYS
nodes will be permanently monitored via comparators for insertion, removal events. Furthermore
they will be measured via the GPADC in order to take decision on the boot process.
System Voltage and Temperature Measurement: it monitors the DA6021 input voltage at VSYS,
the on-die temperature as well as the battery and platform sensor temperatures. It detects over- and
under-voltage conditions. If activated, it can issue critical events.
GPADC: The GPADC is primarily for temperature and voltage measurements. It can run predefined
sequences or a single programmable one. It supports automatic and manual measurement
methods and can also run also in a standby mode at programmable long intervals.
Digital Battery Interface: 1-wire protocol agnostic digital communication between battery and SoC.
It introduces a level shifting between the SoC and the main battery
OTP & EEPROM Interface: DA6021 will read its parameters from integrated OTP during power on
reset. Optionally those OTP parameter settings can be overwritten by an external EEPROM for
back-up solution, debugging or development. Note, The OTP can’t be overwritten and the EEPROM
can’t be programmed via the DA6021
Platform Back-up Battery Charger: DA6021 includes an autonomous charger for platform backup
batteries such as coin cells or “supercaps”.
Display control:
BCU: Battery controller unit, supervising peripherals based on system voltage
PWM: to accommodate some external functionality, DA6021 can generate up to 3 PWM signals
with programmable duty-cycle and frequency.
GPIOs: 16 general purpose I/O with alternate functions.

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
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Data Sheet
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5. Block Diagram
Overview Diagram5.1
Figure 1: Overview Diagram
buck
converters
VCC
VNN
V1P0A
V1P05SX
V1P8A
VDDQ
buck/boost
converters
V3P3A
V2P85S
boost
converter V5P0S
LDOs
VLP
VREF
VDDQ_VTT
V1P2A
VREFDQ0
Internal
power
switches
VSDIO
VUSBPHY
VSYS_S
V1P2S
V1P2SX
V1P8S
V1P8SX
V2P85SX
VHDMI
External
power
switches
VSYSU
V3P3U
V1P8U
V1P0S
V1P0SX
V3P3S
VHOST
VBUS
VSYSSX
SVID
3
EEPROM
IF
HOST IF
Misc/Debug
Input power
detection
PWM
GPADC
GPIOs
8
8
GPIO0
GPIO1
PWM 3
BATID
VBATSENSE
BPHERM
SYSTHERM 3
2
BCU
BCU 3
3
ILIM
VDCIN_SENSE
VBUS_SENSE
CHGDET_B
CHGINT_B
2
2
I2CM
I2C
21
VBATBKUP
3
2
DEBUG_SVID
DEBUG_CS
DEBUG_CS
2
Display
control
BACKLIGHT_EN
PANEL_EN
Power
sequencer
&
System
control
DEBUG_I2C
SVID
VREFDQ1

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
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Detailed Block Diagram5.2
Figure 2: Detailed Block Diagram
VCC_GND
BUCK_VCC
VCC_VIN
0.5V –1.2V
8 A
VCC_SENSEP
VCC_SENSEN
LX1
4 Φ
8
2
2
2
2
8
0.47µH
0.47µH
0.47µH
0.47µH
LX2
LX3
LX4
C
C
VNN_SENSEP
BUCK_VNN
4 Φ
VNN_VIN
8C
VNN_GND
2
2
2
8
0.47µH
0.47µH
0.47µH
LX1
LX2
LX3
BOOST_V5P0S
5.048V
1A
V5P0S_SENSEP
V5P0S_SENSEN
V5P0S_LX C
V5P0S_GND
2
2
0.47µH
2V5P0S
VHDMI_VIN
VHDMI
INT_SW_VHDMI
VBUS_EN
EXT_SW_VBUS
VHOST_EN
EXT_SW_VHOST
C
C
BUBO_V2P85S
2.9V
0.55A
V2P85S_SENSEP
V2P85S_SENSEN
V2P85S_VIN
2C
V2P85S_GND
2
2
0.47µH
LX1
2LX2
2V2P85S
V2P85SX_VIN
V2P85SX
INT_SW_V2P85SX C
C
BUCK_VDDQ
1.24V
2.8A
VDDQ_SENSEP
VDDQ_SENSEN
VDDQ_VIN
4C
VDDQ_GND
2
2
4
0.47µH
0.47µH
LX1
LX2
2 ΦC
V1P2S_VIN
V1P2S
INT_SW_V1P2S/
LDO_V1P2S C
V1P2SX
INT_SW_V1P2SX C
BUCK_V1P05S
1.05V
0.9A
V1P05S_SENSEP
V1P05S_SENSEN
V1P05S_VIN
C
V1P05S_GND
0.47µHLX
BUCK_V1P0A
1.01V
1.9A
V1P0A_SENSEP
V1P0A_SENSEN
V1P0A_VIN
2C
V1P0A_GND
2
2
0.47µH
LX
C
V1P0S_EN
V1P0S_SENSE
EXT_SW_V1P0S
V1P0SX_EN
V1P0SX_SENSE
EXT_SW_V1P0SX
VDDQ_VTT_VIN
VDDQ_VTT_R
LDO_VDDQ_VTT
VDDQ_VTT_GND
VDDQ_VTT C
C
BUCK_V1P8A 1.817V 1.7A
V1P8A_SENSEP
V1P8A_SENSEN
V1P8A_VIN
2C
V1P8A_GND
2
2
0.47µH
LX
V1P8U_EN V1P8U_SENSE
EXT_SW_V1P8U
V1P8SX
INT_SW_V1P8SX C
V1P8S_VIN V1P8S
INT_SW_V1P8S C
V1P2A
LDO_V1P2A C
VREFDQ1
LDO_VREFDQ1 C
BUBO_V3P3A 3.332V 1.6A
V3P3A_SENSEP
V3P3A_SENSEN
V3P3A_VIN
3C
V1P8A_GND
3
3
0.47µH
LX1
3LX2
3V3P3A
V3P3S_EN_B V3P3S_SENSE
EXT_SW_V3P3S
V3P3U_EN_B V3P3U_SENSE
EXT_SW_V3P3U
VSDIO_VIN VSDIO
INT_SW_VSDIO C
VUSBPHY
INT_SW_VUSBPHY C
VSYS_U_EN_B
VSYS_U_SENSE EXT_SW_VSYS_U
VSYS_SX_EN_B
VSYS_SX_SENSE
EXT_SW_VSYS_SX
VSYS_3
VSYS_S
INT_SW_VSYS_S
2
VREF12
IREF12 Bandgap
VREF12_GND
VLP
VLP_GND LDO_VLP (VREF)
SVID_DIO
SVID_CLK
SVID_ALERT_B SVID INTERFACE
I2C_CLK
I2C_DATA I2C INTERFACE
I2CM_CLK
I2CM_DATA EEPROM IF
IRQ
PWRBTN_B
PLTRST_B
PWRBTNIN_B
SLP_S3_B
SLP_S4_B SLP_S0IX_B
DRAMPWROK
VCCAPWROK
RSMRST_B
SUSPWRDNACK
THERMTRIP_B
COREPWROK
ACPRESENT
BATLOW_B
PROCHOT_B
MODEM_OFF_B
SDWN_B
RTC_POR_B
SDMMC3_1P8_EN
SDMMC3_PWR_EN_B
System Control,
Reset, Power
and Control
Signals
VBUS_SENSE
CHGDET_B
VDCIN_SENSE
CHGINT_B
ILIM[1:0] 2
Power source
detection and
charger control
GPIO0P0_BATIDIN
GPIO0P1_BATIDOUT
Low voltage
General Purpose
IO
GPIO0P[7:2]
GPIO0VDD
GPIO0GND
GPIO1P0_UIBTN_B
High voltage
General Purpose
IO
GPIO1P[7:1]
GPIO1VDD
GPIO1GND
6
7
BCUDISA Burst Control Unit
BCUDISB
BCUDISCRIT
PWM[2:0]
PULSE WIDTH
MODULATION
PWMVDD
PWMGND
3
BACKLIGHT_EN Display Pandel
Control
PANEL_EN
SYSTHERM[2:0]
BPTHERM[1:0] ADC
BATID
VBATSENSE
3
2
VREFB
MISC
VREFT
PMICTEST
DEBUG_CS
DEBUG_SVID_DATA
DEBUG_SVID_CLK
DEBUG_SVID_ALERT_B
DEBUG_I2C_DATA
DEBUG_I2C_CLK
SUBGND
0.5V –1.2V
8 A
System Control
Power Sequencer
DA6021
LBUS
LBUS
LBUS
LBUS
VREFDQ0
LDO_VREFDQ0 C
20.47µH
LX4
ULPI_VBUS_EN
Backup Battery
Charger
VBATBKUP
C
C
C C

DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
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31-Jan-14
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6. Operating Conditions
All Voltages are referenced to VSS unless otherwise stated. Currents flowing into DA6021 are deemed positive,
currents flowing out are deemed negative.
All parameters are valid over the full operating temperature range and power supply range unless otherwise
noted. Please note that the power dissipation must be limited to avoid overheating of DA6021. The maximum
power dissipation should not be reached with maximum ambient temperature.
Absolute Maximum Ratings6.1
Parameter
Conditions
Min
Max
Unit
Val
Storage Temperature
TSTOR
-65
+150
°C
Q
Operating Temperature free-air
TAMB
-30
+85
°C
E
Power Supply Input
VSUP
-0.3
+5.5
V
E/Q
IO Input
(All unless otherwise stated)
-0.3
VSUP+0.3
V
Q
Maximum power dissipation
60°C ambient temperature
55mmx100mmx0.75mm PCB
2.0
W
D,E
Package thermal resistance
TBD
K/W
D,E
ESD CDM
(Charge Device Model)
All pins unless otherwise stated.
±500
V
Q
ESD HBM
(Human Body Model)
All pins unless otherwise stated.
±2
kV
Q
Table 1: DA6021 Absolute Maximum Ratings
Recommended Operating Conditions
6.2
Parameter
Conditions
Min
Max
Unit
Val
Operating Temperature free-air
TAMB
-30
+85
°C
E,Q
Power Supply Input
VSUP
2.7
4.5
V
E,Q
Table 2: DA6021 Recommended Operating Conditions
The maximum allowed operational die temperature is defined to 125°C. Below you can find the time constraints
in relation to the peak power dissipation. The simulation results are based on
10 layer board, 70x170x0.8mm3
Natural convection, air velocity 0m/s
Surface-to –surface radiation
Package initializes at 0.25W with initial temperature of 38°C
Surrounding ambient temperature in immediate vicinity at 31°C
Maximum power burst exposure of 100s
Various power burst scenarios at: 0.76, 0.96, 1.20, 2.90, 3.72, 4.52 and 7.0W

DA6021
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Figure 3: Maximum Allowed Peak Power
VAL status
Description of Abbreviation
D
Parameter is guaranteed by design
E
Parameter is confirmed by silicon evaluation
Q
Parameter is verified by silicon qualification
A
Parameter is screened during final ATE test
A*
Parameter is screened during final ATE test by indirect
measurement or with a special test set-up
Table 3: Abbreviations of Validation Status
7. Ordering Information
The order number consists of the part number followed by a suffix indicating a.o. the packing method. For
details, please consult the Dialog customer portal on our web site or your local sales representative.
Part
Number
Package Name
Package description
Package Outline
DA6021
FCBGA
325 pin, FCBGA 11x6mm, 0.4mm pitch
Figure 76
Current OTP variant: -08 (Intel approved)