Digi ConnectCore 6UL Instruction Manual

ConnectCore 6UL
Hardware Design Guidelines and Checklist

Revision history—90002341
Revision Date Description
A June 2019 Initial release
B April 2020 Corrected minor power rail name errors and typos
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ConnectCore 6UL Hardware Design Guidelines 2

ConnectCore 6UL Hardware Design Guidelines 3
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Contents
About this document
Overview 5
Naming and signal conventions 5
Schematics design checklist
RF guidelines
RF matching network for the external antenna 13
Regulations 14
Bring-up guidelines
Power-up 15
Power rails 15
Verify system boot 15
ConnectCore 6UL Hardware Design Guidelines 4

About this document
Overview
The purpose of this document is to ease and drive the hardware design process of
ConnectCore 6UL SOM-based products. Schematics milestones keep bring-up of your designs
on track for success, and layout recommendations help achieve optimal electrical behavior.
This document, together with the ConnectCore 6UL System-on-Module Hardware Reference Manual,
provide information key to ensuring a functional, quality design featuring the ConnectCore 6UL
module.
Naming and signal conventions
This document is written assuming the reader has a good working knowledge of common electronics
terminology. You may also encounter the following specific conventions:
Convention Definition
signal_name# A hash sign at the end of a signal name denotes that it is an active low signal.
_B An alternate way to indicate a signal is active low.
x Indicates an alphanumeric value.
Register/signal
[a:b]
Brackets after a name refer to the bits or signals contained in a register, or in a
set of related signals.
ConnectCore 6UL Hardware Design Guidelines 5

Schematics design checklist
The microprocessor used on this module, like all CMOS devices, can be driven into a latch-
up condition if any I/O pin is driven outside of its associated power rail. Care must be taken
to:
nNever drive an I/O pin beyond its positive rail or below ground.
nNever drive an I/O pin from an external power source during the power-on or reset
sequences.
nNever hot-swap the module or interrupt its ground connection to external circuitry.
Latch-up is a condition that can cause excessive current draw and result in excessive
heating of the microprocessor or its power supplies. This excessive heating can
permanently damage the microprocessor and/or its supporting components.
☑Item Description
Power supply
1.Input power
of the SOM
Make sure the input power supply of the module follows one of the two
available configurations:
VSYS LDOG VPWR
With front-
end LDO
Connected to
Mosfet drain
Connected to
Mosfet gate
Input power line:
4.6V - 5.5V
Without
front-end
LDO
Input power line:
3.7V - 4.5V
Floating Grounded
Note For detailed information about the input power circuitry, see the
ConnectCore 6UL System-on-Module Hardware Reference Manual.
ConnectCore 6UL Hardware Design Guidelines 6

Schematics design checklist Naming and signal conventions
ConnectCore 6UL Hardware Design Guidelines 7
☑Item Description
2. Minimum
decoupling
capacitors on
VSYS/VSYS2
2 x 47uF + 1 x 4.7uF + 1 x 100nF
3. VCC_MCA
power line
This power line is the input power supply of the on-module MCA. It must
be powered from a dedicated 3.3V regulator connected to the main input
power supply of the board, since it is an always-on power supply. Connect
a Schottky diode (low forward voltage drop) between the output of the
regulator and the VCC_MCA pin. VIN_PRESENT must be tied to the output
of this 3.3V regulator. To allow coin-cell (low-power mode) applications,
the coin-cell/supercap must be connected to VCC_MCA again through a
Schottky diode. See Schematic: coin-cell/supercap connected to VCC_
MCA through Schottky diode.
Note In the ConnectCore 6UL reference designs (SBC PRO and SBC
Express) there's a 100 Ωseries resistor between the coin-cell/supercap
and VCC_LICELL signal in the circuit above. Please remove this resistor. It
introduces a voltage drop in the transitory from normal operation to RTC
mode operation which could cause undesirable RTC behavior.
4. 3V3_EXT
power rail
3V3_EXT is a dedicated 3.3V output power rail for powering external
circuitry of the carrier board. Do not connect any external power supply
to this line.
5. VCC_ENET
power rail
VCC_ENET is a 3.3V input power rail for supplying the ENET module of the
CPU. Digi recommends you feed this power domain directly from the
3V3_EXT power rail.
6. Unconnected
power rails
By default, leave the following power rails unconnected:
lVCC_NAND (pad C12)
lVDDA_ADC_3P3 (pad L3)
lVDD_SNVS_3V3 (pad D12)
lVCC_LICELL (pad B1)
l3V3_INT (pad E3)
Although these signals are not used externally, it may be helpful to leave
them accessible for debugging (test points).

Schematics design checklist Naming and signal conventions
ConnectCore 6UL Hardware Design Guidelines 8
☑Item Description
BOOT
1. BOOT_MODE
[1:0]
These lines select the boot mode of the SOM:
BOOT_MODE1 BOOT_MODE0 Description
0 0 Boot from fuses
0 1 Serial downloader
1 0 Boot from board settings
1 1 Reserved
By default, select the Boot from board settings option to boot from the
internal NAND memory. Use 10K resistors for pulling these line up or
down. When pulled-high, refer these lines to VDD_SNVS_IN. When this is
not possible (castellated pad configuration), use the 3V3_EXT power line.
Note BOOT_MODE0 is internally pulled-low. In the castellated version,
only BOOT_MODE1 is available externally.
2.
Recover/Debug
mode (USB)
To allow the system to boot from USB as a recovery/debug method, add
a jumper for shorting BOOT_MODE1 line to GND. This will force the
system to boot from fuses, and as long as they are not burned, the
system will fall into serial mode and boot from USB. This method is faster
than changing both BOOT_MODE[1:0] lines resistors to set up the Serial
Downloader, and can be helpful during the development phase when you
do not want to burn fuses.
The CPU can only boot from the USB_OTG1 bus. (USB_OTG2 is not
bootable.)
3. Boot
configuration
lines
Make sure the BOOT_CFG1[7:0] lines are properly setup for booting from
the on-module NAND memory:
lLCD_DATA0 (BOOT_CFG1[0]): pull-down
lLCD_DATA1 (BOOT_CFG1[1]): pull-down
lLCD_DATA2 (BOOT_CFG1[2]): pull-down
lLCD_DATA3 (BOOT_CFG1[3]): pull-down
lLCD_DATA4 (BOOT_CFG1[4]): pull-up
lLCD_DATA5 (BOOT_CFG1[5]): pull-down
lLCD_DATA6 (BOOT_CFG1[6]): pull-down
lLCD_DATA7 (BOOT_CFG1[7]): pull-up
Use 10K resistors to pull these line up or down. When pulled-high, refer
these lines to 3V3_EXT.

Schematics design checklist Naming and signal conventions
ConnectCore 6UL Hardware Design Guidelines 9
☑Item Description
4. Boot
configuration
lines buffer
Boot configuration lines are latched during booting for configuring the
boot process of the SOM. Digi recommends you add a buffer to protect
these lines during booting. External circuitry and peripherals connected
to these lines can modify the expected value when system is booting, so
that the process can fail. See the Schematic: boot configuration lines
used on the ConnectCore 6UL SBC PRO reference design.
Eight additional BOOT_CFG lines are configured inside the module. These
lines are LCD_DATA[9:15]. Place another buffer for these lines if you
expect to have external circuitry/peripherals modifying their values.
5. LCD_DATA23
line
configuration
This line is one of the GPIOs latched during booting and is used to
configure one of the Boot Configuration bits (BOOT_CFG4[7]). It enables
an infinite loop debug mode. For proper operation, make sure this line is
not pulled-high during booting.
MCA
1.MCA_RESET Input reset line of the system. Connect a 100K pull-up to VCC_MCA.
2. SWD_
CLK/PWR_IO
Input power on/off - suspend line of the system. Connect a 100K pull-up
to VCC_MCA.
3. Isolate VCC_
MCA power
domains
As much as possible, try not to mix the VCC_MCA power domain with the
rest of the power domains of the system. The ConnectCore 6UL SBC
Express/PRO designs use an MCA GPIO to manage the reset line of the
LAN8720Ai PHY (powered from 3V3_EXT). This configuration resulted in
some unexpected backdrive currents.
Console debug port
1.UART5 The default U-Boot loaded in the modules from manufacturing configures
the UART5 as the console debug port. This console port can be changed
to any other UART in the system, but Digi recommends you use this
UART5 as the console port so no additional effort (such as compiling a
new U-Boot, loading it through USB, etc.) are required.
I2C
1.I2C1 bus Do not use the I2C1 bus to communicate with external peripherals. This
bus is used internally in the module for interconnecting critical devices
(CPU, MCA, PMIC).
2.I2C pull-ups Add external pull-ups to the clock and data lines of the I2C buses. You will
typically use 4.7K resistors.
GPIOs
1.GPIO5 ring GPIO5_x I/Os are supplied from VDD_SNVS_IN (3.0V). Do not overdrive
them with 3.3V.

Schematics design checklist Naming and signal conventions
ConnectCore 6UL Hardware Design Guidelines 10
☑Item Description
2. GPIO5_03 GPIO5_03 (pad V15) is not supported.
NAND
1.NAND signals The following pads, which areused internally, must be left unconnected if
you want to use the on-module NAND flash memory:
lB10 (NAND_CE#)
lB8 (NAND_CLE)
lB9 (NAND_ALE)
lB11 (NAND_WE#)
lC9 (NAND_RE#)
lC10 (NAND_WP#)
lD11 (NAND_READY#)
lC6 (NAND_DATA0)
lC7 (NAND_DATA1)
lC8 (NAND_DATA2)
lM3 (NAND_DATA3)
lD6 (NAND_DATA4)
lN2 (NAND_DATA5)
lR2 (NAND_DATA6)
lC15 (NAND_DATA7)
Wireless and Bluetooth
1.Wireless
SDIO
The SDIO1 interface of the CPU is used internally in the SOM for the
wireless connectivity. The following pads must be left unconnected to
preserve this wireless functionality:
lK19 (WLAN_SD1_CLK)
lL19 (WLAN_SD1_CMD)
lM19 (WLAN_SD1_DATA0)
lL20 (WLAN_SD1_DATA1)
lK20 (WLAN_SD1_DATA2)
lM20 (WLAN_SD1_DATA3)
This applies only to Wireless variants of the SOM. In non-wireless variants,
the SDIO1 bus is available.