Digi NS7520B-1-C36 Application guide

Part number/version: 90000353_G
Release date: September 2007
www.digiembedded.com
NS7520 Hardware Reference

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Using This Guide
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This guide provides information about the NS7520 32-bit networked
microprocessor. The NS7520 is part of the NET+ARM line of SoC (System-on-
Chip) products, and supports high-bandwidth applications for intelligent
networked devices.
The NET+ARM family is part of the NET+Works integrated product family, which
includes the NET+OS network software suite.
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Using This Guide

iv NS7520 Hardware Reference, Rev G 9/2007
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Contents
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Chapter 1: About the NS7520 .................................................................................... 1
NS7520 Features ......................................................................... 2
Key features and operating modes of the major NS7520 modules ........ 2
NS7520 module block diagram......................................................... 5
Operating frequency .................................................................... 6
Chapter 2: Pinout and Packaging ......................................................................... 7
Packaging ................................................................................. 8
Pinout detail tables and signal descriptions........................................ 11
System bus interface ............................................................ 12
Chip select controller ........................................................... 16
Ethernet interface MAC ......................................................... 18
“No connect” pins ............................................................... 21
General-purpose I/O ............................................................ 21
System clock and reset ......................................................... 24
System mode (test support).................................................... 25
JTAG test (ARM debugger) ..................................................... 26
Power supply ..................................................................... 28
Chapter 3: Working with the CPU ..................................................................... 29
ARM Thumb concept ................................................................... 30
CPU performance ....................................................................... 30
Working with ARM exceptions ........................................................ 31
Summary of ARM exceptions ................................................... 32
Exception priorities.............................................................. 32

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Exception vector table.......................................................... 33
Detail of ARM exceptions ....................................................... 34
Entering and exiting an exception (software action) ...................... 37
Hardware Interrupts.................................................................... 39
FIRQ and IRQ lines ............................................................... 39
Interrupt controller.............................................................. 39
Interrupt sources................................................................. 40
Chapter 4: BBus Module ................................................................................................43
BBus masters and slaves ............................................................... 44
Cycles and BBus arbitration ........................................................... 44
Address decoding ....................................................................... 45
Chapter 5: SYS Module ...................................................................................................47
Signal description....................................................................... 48
JTAG support ............................................................................ 48
ARM debug ............................................................................... 48
System clock generation (NS7520 clock module) .................................. 49
External oscillator vs. internal PLL circuit................................... 49
NS7520 clock module block diagram.......................................... 50
Using the external oscillator.......................................................... 50
External oscillator mode hardware configuration .......................... 50
Using the PLL circuit ................................................................... 51
PLL mode hardware configuration ............................................ 52
Setting the PLL frequency............................................................. 54
PLL Settings register: Setting the PLL frequency on bootup .............. 54
PLL Control register: Setting the PLL frequency with the PLL Control
register ............................................................................ 57
Reset circuit sources ................................................................... 59
NS7520 bootstrap initialization....................................................... 59
Chapter 6: GEN Module ..................................................................................................61
Module configuration................................................................... 62
GEN module hardware initialization ................................................. 62
GEN module registers .................................................................. 63

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System Control register......................................................... 63
System Status register .......................................................... 68
Software Service register....................................................... 69
Timer Control registers ......................................................... 70
Timer Status registers........................................................... 73
PORTA Configuration register.................................................. 73
PORTC Configuration register.................................................. 77
Interrupts ................................................................................ 80
Interrupt controller registers .................................................. 81
Chapter 7: Memory Controller Module ........................................................ 85
About the MEM module ................................................................ 86
MEM module hardware initialization................................................. 86
Pin configuration................................................................. 86
MEM module configuration ............................................................ 87
Setting the chip select address range ........................................ 88
Memory Module Configuration register....................................... 89
Chip Select Base Address register ............................................. 92
Chip Select Option Register A ................................................. 97
Chip Select Option Register B.................................................101
Static memory (SRAM) controller ...................................................102
Single cycle read/write ........................................................102
Burst cycles ......................................................................104
NS7520 DRAM address multiplexing .................................................105
Using the internal multiplexer................................................105
Using the external multiplexer ...............................................108
DRAM refresh ...........................................................................109
FP/EDO DRAM controller .............................................................109
Single cycle read/write ........................................................110
FP/EDO DRAM burst cycles ....................................................111
SDRAM ...................................................................................111
NS7520 SDRAM interconnect ..................................................112
SDRAM A10/AP support ........................................................116
Command definitions...........................................................117
Memory timing fields — SDRAM ...............................................118
BSIZE configuration.............................................................118
SDRAM Mode register ...........................................................119

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SDRAM read cycles..............................................................120
SDRAM write cycles.............................................................122
Peripheral page burst size ...........................................................124
Chapter 8: DMA Module ...............................................................................................127
DMA module ............................................................................128
Fly-by operation transfers.....................................................128
Memory-to-memory operation ................................................129
DMA buffer descriptor ................................................................130
DMA channel assignments ............................................................132
DMA channel registers ................................................................133
Address map .....................................................................133
Buffer Descriptor Pointer register ...........................................136
DMA Control register ...........................................................136
DMA Status/Interrupt Enable register .......................................142
Ethernet transfer considerations....................................................144
Ethernet transmitter considerations................................................145
Ethernet receiver considerations ...................................................145
External peripheral DMA support....................................................146
Signal description...............................................................147
External DMA configuration ...................................................147
Memory-to-memory mode .....................................................147
DMA controller reset ..................................................................148
Chapter 9: Ethernet Module ....................................................................................149
Ethernet front-end (EFE) .............................................................150
Transmit and receive FIFOs ...................................................151
EFE transmit processing .......................................................151
EFE receive processing.........................................................151
Receive buffer descriptor selection .........................................152
External CAM filtering ................................................................153
MAC module ............................................................................154
MAC module block diagram ...................................................154
DMA channel assignments ............................................................156
EFE configuration ......................................................................156
Ethernet General Control register (EGCR) bit definitions ................158

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Ethernet General Status register (EGSR) bit definitions..................164
Ethernet FIFO Data register ...................................................167
Ethernet Transmit Status register............................................168
Ethernet Receive Status register .............................................173
MAC Configuration Register 1 .................................................176
MAC Configuration Register 2 .................................................178
Back-to-Back Inter-Packet-Gap register.....................................182
Non-Back-to-Back Inter-Packet-Gap register ...............................183
Collision Window/Collision Retry register ..................................184
Maximum Frame register ......................................................185
PHY Support register ...........................................................186
Test register .....................................................................187
MII Management Configuration register .....................................189
MII Management Command register..........................................191
MII Management Address register ............................................192
MII Management Write Data register ........................................193
MII Management Read Data register .........................................194
MII Management Indicators register..........................................195
SMII Status register .............................................................196
Station Address registers ......................................................196
Station Address Filter register ................................................199
Register hash table .............................................................200
Chapter 10: Serial Controller Module ........................................................ 207
Supported features ....................................................................208
Bit-rate generator .....................................................................209
Serial protocols ........................................................................210
UART mode .............................................................................210
SPI mode ................................................................................211
FIFO management ..............................................................212
General-purpose I/O configurations ................................................220
Serial port performance ..............................................................221
Configuration...........................................................................221
Serial Channel registers ..............................................................223
Serial Channel 1, 2 Control Register A ......................................223
Serial Channel 1, 2 Control Register B ......................................229
Serial Channel 1, 2 Status Register A ........................................233

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Serial Channel 1, 2 Bit-Rate registers .......................................241
Serial Channel 1, 2 FIFO registers............................................250
Serial Channel 1, 2 Receive Buffer Gap Timer .............................250
Serial Channel 1, 2 Receive Character Gap Timer.........................252
Serial Channel 1,2 Receive Match register..................................254
Serial Channel 1, 2 Receive Match MASK register..........................254
Chapter 11: Electrical Characteristics .......................................................257
DC characteristics .....................................................................258
Recommended operating conditions.........................................258
Input/Output characteristics .................................................259
Pad pullup and pulldown characteristics....................................259
Absolute maximum ratings ....................................................261
AC characteristics .....................................................................261
AC electrical specifications ...................................................261
Oscillator Characteristics.............................................................263
Timing Diagrams .......................................................................265
Timing_Specifications ..........................................................265
Reset_timing ....................................................................266
SRAM timing .....................................................................267
SDRAM timing....................................................................277
FP DRAM timing .................................................................283
Ethernet timing .................................................................290
JTAG timing......................................................................292
External DMA timing............................................................294
Serial internal/external timing ...............................................297
GPIO timing ......................................................................299
Chapter 12: NS7520 Errata .......................................................................................301
How to identify the NS7520 ..........................................................302
NS7520 errata ..........................................................................303
Clock speed errata using PLL in boundary scan mode ....................303
UART CTS-related transmit data errors .....................................303
EDO burst errata ................................................................304
NS7520 clock speed erratum ..................................................306
SPI slave mode errata ..........................................................308