Digi NS7520B-1-C36 Application guide

Part number/version: 90000353_G
Release date: September 2007
www.digiembedded.com
NS7520 Hardware Reference

ii
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Using This Guide
iii
This guide provides information about the NS7520 32-bit networked
microprocessor. The NS7520 is part of the NET+ARM line of SoC (System-on-
Chip) products, and supports high-bandwidth applications for intelligent
networked devices.
The NET+ARM family is part of the NET+Works integrated product family, which
includes the NET+OS network software suite.
Conventions used in this guide
This table describes the typographic conventions used in this guide:
This convention Is used for
italic type Emphasis, new terms, variables, and document titles.
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‘b Indicates that the number following this indicator is in binary radix
‘d Indicates that the number following this indicator is in decimal radix
‘h Indicates that the number following this indicator is in hexadecimal
radix
Using This Guide

iv NS7520 Hardware Reference, Rev G 9/2007
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Contents
v
Chapter 1: About the NS7520 .................................................................................... 1
NS7520 Features ......................................................................... 2
Key features and operating modes of the major NS7520 modules ........ 2
NS7520 module block diagram......................................................... 5
Operating frequency .................................................................... 6
Chapter 2: Pinout and Packaging ......................................................................... 7
Packaging ................................................................................. 8
Pinout detail tables and signal descriptions........................................ 11
System bus interface ............................................................ 12
Chip select controller ........................................................... 16
Ethernet interface MAC ......................................................... 18
“No connect” pins ............................................................... 21
General-purpose I/O ............................................................ 21
System clock and reset ......................................................... 24
System mode (test support).................................................... 25
JTAG test (ARM debugger) ..................................................... 26
Power supply ..................................................................... 28
Chapter 3: Working with the CPU ..................................................................... 29
ARM Thumb concept ................................................................... 30
CPU performance ....................................................................... 30
Working with ARM exceptions ........................................................ 31
Summary of ARM exceptions ................................................... 32
Exception priorities.............................................................. 32

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Exception vector table.......................................................... 33
Detail of ARM exceptions ....................................................... 34
Entering and exiting an exception (software action) ...................... 37
Hardware Interrupts.................................................................... 39
FIRQ and IRQ lines ............................................................... 39
Interrupt controller.............................................................. 39
Interrupt sources................................................................. 40
Chapter 4: BBus Module ................................................................................................43
BBus masters and slaves ............................................................... 44
Cycles and BBus arbitration ........................................................... 44
Address decoding ....................................................................... 45
Chapter 5: SYS Module ...................................................................................................47
Signal description....................................................................... 48
JTAG support ............................................................................ 48
ARM debug ............................................................................... 48
System clock generation (NS7520 clock module) .................................. 49
External oscillator vs. internal PLL circuit................................... 49
NS7520 clock module block diagram.......................................... 50
Using the external oscillator.......................................................... 50
External oscillator mode hardware configuration .......................... 50
Using the PLL circuit ................................................................... 51
PLL mode hardware configuration ............................................ 52
Setting the PLL frequency............................................................. 54
PLL Settings register: Setting the PLL frequency on bootup .............. 54
PLL Control register: Setting the PLL frequency with the PLL Control
register ............................................................................ 57
Reset circuit sources ................................................................... 59
NS7520 bootstrap initialization....................................................... 59
Chapter 6: GEN Module ..................................................................................................61
Module configuration................................................................... 62
GEN module hardware initialization ................................................. 62
GEN module registers .................................................................. 63

vii
System Control register......................................................... 63
System Status register .......................................................... 68
Software Service register....................................................... 69
Timer Control registers ......................................................... 70
Timer Status registers........................................................... 73
PORTA Configuration register.................................................. 73
PORTC Configuration register.................................................. 77
Interrupts ................................................................................ 80
Interrupt controller registers .................................................. 81
Chapter 7: Memory Controller Module ........................................................ 85
About the MEM module ................................................................ 86
MEM module hardware initialization................................................. 86
Pin configuration................................................................. 86
MEM module configuration ............................................................ 87
Setting the chip select address range ........................................ 88
Memory Module Configuration register....................................... 89
Chip Select Base Address register ............................................. 92
Chip Select Option Register A ................................................. 97
Chip Select Option Register B.................................................101
Static memory (SRAM) controller ...................................................102
Single cycle read/write ........................................................102
Burst cycles ......................................................................104
NS7520 DRAM address multiplexing .................................................105
Using the internal multiplexer................................................105
Using the external multiplexer ...............................................108
DRAM refresh ...........................................................................109
FP/EDO DRAM controller .............................................................109
Single cycle read/write ........................................................110
FP/EDO DRAM burst cycles ....................................................111
SDRAM ...................................................................................111
NS7520 SDRAM interconnect ..................................................112
SDRAM A10/AP support ........................................................116
Command definitions...........................................................117
Memory timing fields — SDRAM ...............................................118
BSIZE configuration.............................................................118
SDRAM Mode register ...........................................................119

viii
SDRAM read cycles..............................................................120
SDRAM write cycles.............................................................122
Peripheral page burst size ...........................................................124
Chapter 8: DMA Module ...............................................................................................127
DMA module ............................................................................128
Fly-by operation transfers.....................................................128
Memory-to-memory operation ................................................129
DMA buffer descriptor ................................................................130
DMA channel assignments ............................................................132
DMA channel registers ................................................................133
Address map .....................................................................133
Buffer Descriptor Pointer register ...........................................136
DMA Control register ...........................................................136
DMA Status/Interrupt Enable register .......................................142
Ethernet transfer considerations....................................................144
Ethernet transmitter considerations................................................145
Ethernet receiver considerations ...................................................145
External peripheral DMA support....................................................146
Signal description...............................................................147
External DMA configuration ...................................................147
Memory-to-memory mode .....................................................147
DMA controller reset ..................................................................148
Chapter 9: Ethernet Module ....................................................................................149
Ethernet front-end (EFE) .............................................................150
Transmit and receive FIFOs ...................................................151
EFE transmit processing .......................................................151
EFE receive processing.........................................................151
Receive buffer descriptor selection .........................................152
External CAM filtering ................................................................153
MAC module ............................................................................154
MAC module block diagram ...................................................154
DMA channel assignments ............................................................156
EFE configuration ......................................................................156
Ethernet General Control register (EGCR) bit definitions ................158

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Ethernet General Status register (EGSR) bit definitions..................164
Ethernet FIFO Data register ...................................................167
Ethernet Transmit Status register............................................168
Ethernet Receive Status register .............................................173
MAC Configuration Register 1 .................................................176
MAC Configuration Register 2 .................................................178
Back-to-Back Inter-Packet-Gap register.....................................182
Non-Back-to-Back Inter-Packet-Gap register ...............................183
Collision Window/Collision Retry register ..................................184
Maximum Frame register ......................................................185
PHY Support register ...........................................................186
Test register .....................................................................187
MII Management Configuration register .....................................189
MII Management Command register..........................................191
MII Management Address register ............................................192
MII Management Write Data register ........................................193
MII Management Read Data register .........................................194
MII Management Indicators register..........................................195
SMII Status register .............................................................196
Station Address registers ......................................................196
Station Address Filter register ................................................199
Register hash table .............................................................200
Chapter 10: Serial Controller Module ........................................................ 207
Supported features ....................................................................208
Bit-rate generator .....................................................................209
Serial protocols ........................................................................210
UART mode .............................................................................210
SPI mode ................................................................................211
FIFO management ..............................................................212
General-purpose I/O configurations ................................................220
Serial port performance ..............................................................221
Configuration...........................................................................221
Serial Channel registers ..............................................................223
Serial Channel 1, 2 Control Register A ......................................223
Serial Channel 1, 2 Control Register B ......................................229
Serial Channel 1, 2 Status Register A ........................................233

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Serial Channel 1, 2 Bit-Rate registers .......................................241
Serial Channel 1, 2 FIFO registers............................................250
Serial Channel 1, 2 Receive Buffer Gap Timer .............................250
Serial Channel 1, 2 Receive Character Gap Timer.........................252
Serial Channel 1,2 Receive Match register..................................254
Serial Channel 1, 2 Receive Match MASK register..........................254
Chapter 11: Electrical Characteristics .......................................................257
DC characteristics .....................................................................258
Recommended operating conditions.........................................258
Input/Output characteristics .................................................259
Pad pullup and pulldown characteristics....................................259
Absolute maximum ratings ....................................................261
AC characteristics .....................................................................261
AC electrical specifications ...................................................261
Oscillator Characteristics.............................................................263
Timing Diagrams .......................................................................265
Timing_Specifications ..........................................................265
Reset_timing ....................................................................266
SRAM timing .....................................................................267
SDRAM timing....................................................................277
FP DRAM timing .................................................................283
Ethernet timing .................................................................290
JTAG timing......................................................................292
External DMA timing............................................................294
Serial internal/external timing ...............................................297
GPIO timing ......................................................................299
Chapter 12: NS7520 Errata .......................................................................................301
How to identify the NS7520 ..........................................................302
NS7520 errata ..........................................................................303
Clock speed errata using PLL in boundary scan mode ....................303
UART CTS-related transmit data errors .....................................303
EDO burst errata ................................................................304
NS7520 clock speed erratum ..................................................306
SPI slave mode errata ..........................................................308

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Error in “No Connect” pin terminations.....................................308
Serial port error in 7-bit mode ...............................................309
SDRAM 256 MB mask failure ...................................................309
Erroneous timeouts when loading timer ....................................309
Station Address Logic: Multicast and broadcast packet filtering ........310
Station Address Logic: Unicast packets .....................................310
Corrupt Ethernet receive packets............................................311
Transmit buffer closed bit is not functional ................................312
Transmit FIFO timing issue ....................................................312
External use of TA_ and TEA_ ................................................313

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www.digiembedded.com 1
About the NS7520
About the NS7520
CHAPTER 1
This chapter provides an overview of the NS7520. The NS7520 is a high-
performance, highly integrated, 32-bit system-on-a-chip ASIC designed for use in
intelligent networked devices and Internet appliances. The NS7520 is based on the
standard architecture in the NET+ARM family of devices.
NET+ARM is the hardware foundation of the NET+Works family of integrated hardware
and software solutions for device networking. These comprehensive platforms
include drivers, popular operating systems, networking software, development tools,
APIs, and complete development boards.

NS7520 Features
2 NS7520 Hardware Reference, Rev G 9/2007
NS7520 Features
The NS7520 can support most any networking scenario, and includes a 10/100 BaseT
Ethernet MAC and two independent serial ports (each of which can run in UART or SPI
mode).
The CPU is an ARM7TDMI (ARM7) 32-bit RISC processor core with a rich complement of
support peripherals and memory controllers, including:
Glueless connection to different types of memory; for example, flash,
SDRAM, EEPROM, and others.
Programmable timers
13-channel DMA controller
External bus expansion module
16 general-purpose I/O (GPIO) pins
Key features and operating modes of the major NS7520 modules
CPU core
–ARM7 32-bit RISC processor
–32-bit internal bus
–32-bit ARM mode and 16-bit Thumb mode
–15 general-purpose 32-bit registers
–32-bit program counter (PC) and status register
–Five supervisor modes, one user mode
13-channel DMA controller
–Two channels dedicated to Ethernet transmit and receive
–Four channels dedicated to two serial modules’ transmit and receive
–Four channels for external peripherals (only two channels — either 3 and 5
or 4 and 6 — can be configured at one time)
–Three channels available for memory-to-memory transfers
–Flexible buffer management

www.digiembedded.com 3
About the NS7520
General-purpose I/O pins
–16 programmable GPIO interface pins
–Four pins programmable with level-sensitive interrupt
Serial ports
–Two fully independent serial ports (UART, SPI)
–Digital phase lock loop (DPLL) for receive clock extractions
–32-byte transmit/receive FIFOs
–Internal programmable bit-rate generators
–Bit rates 75–230400 in 16X mode
–Bit rates 1200 bps–4 Mbps in 1X mode
–Flexible baud rate generator, external clock for synchronous operation
–Receive-side character and buffer gap timers
–Four receive-side data match detectors
Power and operating voltages
–500 mW maximum at 55 MHz (all outputs switching)
–418 mW maximum at 46 MHz (all outputs switching)
–291 mW maximum at 36 MHz (all outputs switching)
–3.3 V — I/O
–1.5 V — Core
Integrated 10/100 Ethernet MAC
–10/100 Mbps MII-based PHY interface
–10 Mbps ENDEC interface
–Support for TP-PMD and fiber-PMD devices
–Full-duplex and half-duplex modes
–Optional 4B/5B coding
–Station, broadcast, and multicast address detection filtering
–512-byte transmit FIFO, 2 Kbyte receive FIFO
–Intelligent receive-side buffer size selection

NS7520 Features
4 NS7520 Hardware Reference, Rev G 9/2007
Programmable timers
–Two independent timers (2μs–20.7 hours)
–Watchdog timer (interrupt or reset on expiration)
–Programmable bus monitor or timer
Operating frequency
–36, 46, or 55 MHz internal clock operation from 18.432 MHz quartz crystal
or crystal oscillator
–fMAX = 36, 46, or 55 MHz (grade-dependent)
–System clock source by external quartz crystal or crystal oscillator, or clock
signal
–Programmable PLL, which allows a range of operating frequencies from 10
to fMAX
–Maximum operating frequency from external clock or using PLL
multiplication fMAX
Bus interface
–Five independent programmable chip selects with 256 Mb addressing per
chip select
–All chip selects support SRAM, FP/EDO DRAM, SDRAM, flash, and EEPROM
without external glue
–Supports 8-, 16-, and 32-bit peripherals
–External address decoding and cycle termination
–Dynamic bus sizing
–Internal DRAM/SDRAM controller with address multiplexer and
programmable refresh frequency
–Internal refresh controller (CAS before RAS)
–Burst-mode support
–0–63 wait states per chip select
–Address pins that configure chip operating modes; see "NS7520 bootstrap
initialization" on page 59.

www.digiembedded.com 5
About the NS7520
NS7520 module block diagram
Figure 1 is an overview of the NS7520, including all the modules.
Figure 1: NS7520 overview
Debugger
PLL
System
Clock
JTAG Debug
Interface
ARM7TDMI
FIRQ
IRQ
2 timers
Watchdog
timer
Power
3.3V
1.5V
BBUS
D
M
A
D
M
A
D
M
A
D
M
A
Serial-A
UART
SPI
Serial-B
UART
SPI
4
level
interrupt
inputs
16 GPIO
Ethernet
controller
802.3
compliant
External
memory
controller
NS7520 Reset
Address bus
Serial transceivers and other
devices
MII Memory
devices
Flash
SRAM
FP DRAM
SDRAM
Boot
config

Operating frequency
6 NS7520 Hardware Reference, Rev G 9/2007
Operating frequency
The NS7520 is available in grades operating at three maximum operating frequencies:
36 MHz, 46 MHz, and 55 MHz. The operating frequency is set during bootstrap
initialization, using pins A[8:0]. These address pins load the PLL settings register on
powerup reset. A[8:7] determines IS (charge pump current); A[6:5] determines FS
(output divider), and A[4:0] defines ND (PLL multiplier). Each bit in A[8:0] can be set
individually.
See "Setting the PLL frequency," beginning on page 54, for more detailed
information.

www.digiembedded.com 7
Pinout and Packaging
Pinout and Packaging
CHAPTER 2
The NS7520 can be used in any embedded environment requiring networking
services in an Ethernet LAN. The NS7520 contains an integrated ARM RISC processor,
10/100 Ethernet MAC, serial ports, memory controllers, and parallel I/O. The NS7520
can interface with another processor using a register or shared RAM interface. The
NS7520 provides all the tools required for any embedded networking application.

Packaging
8 NS7520 Hardware Reference, Rev G 9/2007
Packaging
Table 1 provides the NS7520 packaging dimensions. Figure 2 shows the pinout and
NS7520 dimensions. Figure 3 shows the NS7520 BGA layout.
Symbol Min Nom Max
A——1.4
A1 0.35 0.40 0.45
A2——0.95
b 0.45 0.50 0.55
D 13.0 BSC
D1 11.2 BSC
E 13.0 BSC
E1 11.2 BSC
e 0.8 BSC
aaa 0.1
Table 1: NS7520 packaging dimensions