Digi Rabbit 5000 User manual

Rabbit® 5000 Microprocessor
User’s Manual
019-0168_E

Rabbit 5000 Microprocessor User’s Manual
Part Number 019-0168 • Printed in the U.S.A.
Digi International Inc. © 2013 • All rights reserved.
Digi International Inc. reserves the right to make changes and
improvements to its products without providing notice.
Trademarks
Rabbit®and Dynamic C®are registered trademarks of Digi International Inc.
Windows®is a registered trademark of Microsoft Corporation.
The latest revision of this manual is available at www.digi.com.

Table of Contents
TABLE OF CONTENTS
Chapter 1. The Rabbit 5000 Processor 13
1.1 Introduction.........................................................................................................................................13
1.2 Features...............................................................................................................................................14
1.3 Block Diagram....................................................................................................................................16
1.4 Basic Specifications............................................................................................................................17
1.5 Comparing Rabbit Microprocessors ...................................................................................................18
Chapter 2. Clocks 21
2.1 Overview.............................................................................................................................................21
2.1.1 Block Diagram ...........................................................................................................................22
2.1.2 Registers .....................................................................................................................................22
2.2 Dependencies ......................................................................................................................................23
2.2.1 I/O Pins ......................................................................................................................................23
2.2.2 Other Registers ...........................................................................................................................23
2.3 Operation ............................................................................................................................................24
2.3.1 Main Clock .................................................................................................................................24
2.3.2 Spectrum Spreader .....................................................................................................................25
2.3.3 Clock Doubler ............................................................................................................................27
2.3.4 32 kHz Clock .............................................................................................................................30
2.4 Register Descriptions..........................................................................................................................32
Chapter 3. Reset and Bootstrap 37
3.1 Overview.............................................................................................................................................37
3.1.1 Block Diagram ...........................................................................................................................38
3.1.2 Registers .....................................................................................................................................38
3.2 Dependencies ......................................................................................................................................39
3.2.1 I/O Pins ......................................................................................................................................39
3.2.2 Clocks .........................................................................................................................................39
3.2.3 Other Registers ...........................................................................................................................39
3.2.4 Interrupts ....................................................................................................................................39
3.3 Operation ............................................................................................................................................40
3.3.1 Asynchronous Serial Bootstrap ..................................................................................................42
3.3.2 Serial Flash Bootstrap ................................................................................................................42
3.3.3 Parallel Bootstrap .......................................................................................................................43
3.4 Register Descriptions..........................................................................................................................44
Chapter 4. System Management 45
4.1 Overview.............................................................................................................................................45
4.1.1 Block Diagram ...........................................................................................................................46
4.1.2 Registers .....................................................................................................................................47
4.2 Dependencies ......................................................................................................................................48
4.2.1 I/O Pins ......................................................................................................................................48
4.2.2 Clocks .........................................................................................................................................48
4.2.3 Interrupts ....................................................................................................................................48

Rabbit 5000 Microprocessor User’s Manual
4.3 Operation............................................................................................................................................ 49
4.3.1 Periodic Interrupt ....................................................................................................................... 49
4.3.2 Real-Time Clock ....................................................................................................................... 49
4.3.3 Watchdog Timer ........................................................................................................................ 50
4.3.4 Secondary Watchdog Timer ...................................................................................................... 50
4.4 Register Descriptions ......................................................................................................................... 51
Chapter 5. Memory Management 57
5.1 Overview ............................................................................................................................................ 57
5.1.1 Block Diagram ........................................................................................................................... 60
5.1.2 Registers .................................................................................................................................... 61
5.2 Dependencies ..................................................................................................................................... 62
5.2.1 I/O Pins ...................................................................................................................................... 62
5.2.2 Clocks ........................................................................................................................................ 62
5.2.3 Other Registers .......................................................................................................................... 62
5.2.4 Interrupts .................................................................................................................................... 62
5.3 Operation............................................................................................................................................ 63
5.3.1 Memory Management Unit (MMU) .......................................................................................... 63
5.3.2 Memory Bank Operation ........................................................................................................... 64
5.3.3 Memory Modes ......................................................................................................................... 66
5.3.4 Separate Instruction and Data Space ......................................................................................... 68
5.3.5 Memory Protection .................................................................................................................... 68
5.3.6 Stack Protection ......................................................................................................................... 69
5.4 Register Descriptions ......................................................................................................................... 70
Chapter 6. Interrupts 81
6.1 Overview ............................................................................................................................................ 81
6.2 Operation............................................................................................................................................ 82
6.3 Interrupt Tables .................................................................................................................................. 82
Chapter 7. External Interrupts 85
7.1 Overview ............................................................................................................................................ 85
7.2 Block Diagram ................................................................................................................................... 85
7.2.1 Registers .................................................................................................................................... 86
7.3 Dependencies ..................................................................................................................................... 86
7.3.1 I/O Pins ...................................................................................................................................... 86
7.3.2 Clocks ........................................................................................................................................ 86
7.3.3 Interrupts .................................................................................................................................... 86
7.4 Operation............................................................................................................................................ 86
7.4.1 Example ISR .............................................................................................................................. 87
7.5 Register Descriptions ......................................................................................................................... 88
Chapter 8. Parallel Port A 89
8.1 Overview ............................................................................................................................................ 89
8.1.1 Block Diagram ........................................................................................................................... 89
8.1.2 Registers .................................................................................................................................... 89
8.2 Dependencies ..................................................................................................................................... 90
8.2.1 I/O Pins ...................................................................................................................................... 90
8.2.2 Clocks ........................................................................................................................................ 90
8.2.3 Other Registers .......................................................................................................................... 90
8.2.4 Interrupts .................................................................................................................................... 90
8.3 Operation............................................................................................................................................ 90
8.4 Register Descriptions ......................................................................................................................... 91

Table of Contents
Chapter 9. Parallel Port B 93
9.1 Overview.............................................................................................................................................93
9.1.1 Block Diagram ...........................................................................................................................94
9.1.2 Registers .....................................................................................................................................94
9.2 Dependencies ......................................................................................................................................94
9.2.1 I/O Pins ......................................................................................................................................94
9.2.2 Clocks .........................................................................................................................................94
9.2.3 Other Registers ...........................................................................................................................94
9.2.4 Interrupts ....................................................................................................................................95
9.3 Operation ............................................................................................................................................95
9.4 Register Descriptions..........................................................................................................................95
Chapter 10. Parallel Port C 97
10.1 Overview...........................................................................................................................................97
10.1.1 Block Diagram .........................................................................................................................98
10.1.2 Registers ...................................................................................................................................98
10.2 Dependencies ....................................................................................................................................99
10.2.1 I/O Pins ....................................................................................................................................99
10.2.2 Clocks .......................................................................................................................................99
10.2.3 Other Registers .........................................................................................................................99
10.2.4 Interrupts ..................................................................................................................................99
10.3 Operation ..........................................................................................................................................99
10.4 Register Descriptions......................................................................................................................100
Chapter 11. Parallel Port D 105
11.1 Overview.........................................................................................................................................105
11.1.1 Block Diagram .......................................................................................................................107
11.1.2 Registers .................................................................................................................................108
11.2 Dependencies ..................................................................................................................................109
11.2.1 I/O Pins ..................................................................................................................................109
11.2.2 Clocks .....................................................................................................................................109
11.2.3 Other Registers .......................................................................................................................109
11.2.4 Interrupts ................................................................................................................................109
11.3 Operation ........................................................................................................................................110
11.4 Register Descriptions......................................................................................................................111
Chapter 12. Parallel Port E 123
12.1 Overview.........................................................................................................................................123
12.1.1 Block Diagram .......................................................................................................................125
12.1.2 Registers .................................................................................................................................126
12.2 Dependencies ..................................................................................................................................126
12.2.1 I/O Pins ..................................................................................................................................126
12.2.2 Clocks .....................................................................................................................................126
12.2.3 Other Registers .......................................................................................................................127
12.2.4 Interrupts ................................................................................................................................127
12.3 Operation ........................................................................................................................................127
12.4 Register Descriptions......................................................................................................................128
Chapter 13. Parallel Port H 143
13.1 Overview.........................................................................................................................................143
13.1.1 Block Diagram .......................................................................................................................144
13.1.2 Registers .................................................................................................................................144
13.2 Dependencies ..................................................................................................................................145
13.2.1 I/O Pins ..................................................................................................................................145
13.2.2 Clocks .....................................................................................................................................145
13.2.3 Other Registers .......................................................................................................................145
13.2.4 Interrupts ................................................................................................................................145
13.3 Operation ........................................................................................................................................145

Rabbit 5000 Microprocessor User’s Manual
13.4 Register Descriptions ..................................................................................................................... 146
Chapter 14. Timer A 149
14.1 Overview ........................................................................................................................................ 149
14.1.1 Block Diagram ....................................................................................................................... 151
14.1.2 Registers ................................................................................................................................ 152
14.2 Dependencies ................................................................................................................................. 152
14.2.1 I/O Pins .................................................................................................................................. 152
14.2.2 Clocks .................................................................................................................................... 152
14.2.3 Other Registers ...................................................................................................................... 152
14.2.4 Interrupts ................................................................................................................................ 153
14.3 Operation........................................................................................................................................ 153
14.3.1 Handling Interrupts ................................................................................................................ 153
14.3.2 Example ISR .......................................................................................................................... 153
14.4 Register Descriptions ..................................................................................................................... 154
Chapter 15. Timer B 157
15.1 Overview ........................................................................................................................................ 157
15.1.1 Block Diagram ....................................................................................................................... 157
15.1.2 Registers ................................................................................................................................ 158
15.2 Dependencies ................................................................................................................................. 158
15.2.1 I/O Pins .................................................................................................................................. 158
15.2.2 Clocks .................................................................................................................................... 158
15.2.3 Other Registers ...................................................................................................................... 158
15.2.4 Interrupts ................................................................................................................................ 158
15.3 Operation........................................................................................................................................ 159
15.3.1 Handling Interrupts ................................................................................................................ 159
15.3.2 Example ISR .......................................................................................................................... 159
15.4 Register Descriptions ..................................................................................................................... 160
Chapter 16. Timer C 163
16.1 Overview ........................................................................................................................................ 163
16.1.1 Block Diagram ....................................................................................................................... 164
16.1.2 Registers ................................................................................................................................ 165
16.2 Dependencies ................................................................................................................................. 166
16.2.1 I/O Pins .................................................................................................................................. 166
16.2.2 Clocks .................................................................................................................................... 166
16.2.3 Other Registers ...................................................................................................................... 166
16.2.4 Interrupts ................................................................................................................................ 166
16.3 Operation........................................................................................................................................ 167
16.3.1 Handling Interrupts ................................................................................................................ 167
16.3.2 Example ISR .......................................................................................................................... 167
16.4 Register Descriptions ..................................................................................................................... 168
Chapter 17. Serial Ports A – D 171
17.1 Overview ........................................................................................................................................ 171
17.1.1 Block Diagram ....................................................................................................................... 173
17.1.2 Registers ................................................................................................................................ 174
17.2 Dependencies ................................................................................................................................. 175
17.2.1 I/O Pins .................................................................................................................................. 175
17.2.2 Clocks .................................................................................................................................... 175
17.2.3 Other Registers ...................................................................................................................... 176
17.2.4 Interrupts ................................................................................................................................ 176
17.3 Operation........................................................................................................................................ 177
17.3.1 Asynchronous Mode .............................................................................................................. 177
17.3.2 Clocked Serial Mode ............................................................................................................. 178

Table of Contents
17.4 Register Descriptions......................................................................................................................180
Chapter 18. Serial Ports E – F 187
18.1 Overview.........................................................................................................................................187
18.1.1 Block Diagram .......................................................................................................................188
18.1.2 Registers .................................................................................................................................189
18.2 Dependencies ..................................................................................................................................190
18.2.1 I/O Pins ..................................................................................................................................190
18.2.2 Clocks .....................................................................................................................................190
18.2.3 Other Registers .......................................................................................................................190
18.2.4 Interrupts ................................................................................................................................191
18.3 Operation ........................................................................................................................................192
18.3.1 Asynchronous Mode ..............................................................................................................192
18.3.2 HDLC Mode ..........................................................................................................................192
18.3.3 More on Clock Synchronization and Data Encoding .............................................................193
18.4 Register Descriptions......................................................................................................................197
Chapter 19. Slave Port 203
19.1 Overview.........................................................................................................................................203
19.1.1 Block Diagram .......................................................................................................................204
19.1.2 Registers .................................................................................................................................204
19.2 Dependencies ..................................................................................................................................205
19.2.1 I/O Pins ..................................................................................................................................205
19.2.2 Clocks .....................................................................................................................................205
19.2.3 Interrupts ................................................................................................................................205
19.3 Operation ........................................................................................................................................206
19.3.1 Master Setup ..........................................................................................................................207
19.3.2 Slave Setup .............................................................................................................................207
19.3.3 Master/Slave Communication ................................................................................................208
19.3.4 Slave/Master Communication ................................................................................................208
19.3.5 Handling Interrupts ................................................................................................................208
19.3.6 Example ISR ..........................................................................................................................208
19.3.7 Other Configurations ..............................................................................................................209
19.3.8 Timing Diagrams ...................................................................................................................210
19.4 Register Descriptions......................................................................................................................212
Chapter 20. Analog Components 215
20.1 Overview.........................................................................................................................................215
20.2 Block Diagram................................................................................................................................218
20.2.1 Registers .................................................................................................................................219
20.3 Dependencies ..................................................................................................................................219
20.3.1 I/O Pins ..................................................................................................................................219
20.3.2 Clocks .....................................................................................................................................219
20.4 Operation ........................................................................................................................................220
20.4.1 Fast A/D Converter ................................................................................................................220
20.4.2 Fast D/A Converter ................................................................................................................220
20.4.3 Slow A/D Converter ...............................................................................................................220
20.5 Sample Circuits...............................................................................................................................221
20.6 Register Descriptions......................................................................................................................223
Chapter 21. DMA Channels 229
21.1 Overview.........................................................................................................................................229
21.1.1 Block Diagram .......................................................................................................................232
21.1.2 Registers .................................................................................................................................233
21.2 Dependencies ..................................................................................................................................234
21.2.1 I/O Pins ..................................................................................................................................234
21.2.2 Clocks .....................................................................................................................................234
21.2.3 Interrupts ................................................................................................................................234
21.3 Operation ........................................................................................................................................235

Rabbit 5000 Microprocessor User’s Manual
21.3.1 Handling Interrupts ................................................................................................................ 236
21.3.2 Example ISR .......................................................................................................................... 236
21.3.3 DMA Priority with the Processor .......................................................................................... 236
21.3.4 DMA Channel Priority .......................................................................................................... 238
21.3.5 Buffer Descriptor Modes ....................................................................................................... 238
21.3.5.1 Single Buffer .................................................................................................................. 239
21.3.5.2 Buffer Array ................................................................................................................... 239
21.3.5.3 Linked List ..................................................................................................................... 240
21.3.5.4 Circular Queue ............................................................................................................... 241
21.3.5.5 Linked Array .................................................................................................................. 241
21.3.6 DMA with Peripherals ........................................................................................................... 242
21.3.6.1 DMA with HDLC Serial Ports ...................................................................................... 242
21.3.6.2 DMA with Ethernet ....................................................................................................... 242
21.3.6.3 DMA with Wi-Fi ........................................................................................................... 242
21.3.6.4 DMA with PWM and Timer C ...................................................................................... 242
21.4 Register Descriptions ..................................................................................................................... 243
Chapter 22. 10/100Base-T Ethernet 257
22.1 Overview ........................................................................................................................................ 257
22.1.1 Block Diagram ....................................................................................................................... 259
22.1.2 Registers ................................................................................................................................ 260
22.2 Dependencies ................................................................................................................................. 262
22.2.1 I/O Pins .................................................................................................................................. 262
22.2.2 Clocks .................................................................................................................................... 262
22.2.3 Other Registers ...................................................................................................................... 262
22.2.4 Interrupts ................................................................................................................................ 263
22.3 Operation........................................................................................................................................ 263
22.3.1 Setup ...................................................................................................................................... 264
22.3.2 Transmit ................................................................................................................................. 264
22.3.3 Receive .................................................................................................................................. 264
22.3.4 Handling Interrupts ................................................................................................................ 265
22.3.5 Multicast Addressing ............................................................................................................. 266
22.4 Register Descriptions ..................................................................................................................... 267
Chapter 23. 802.11b/g Wireless 281
23.1 Overview ........................................................................................................................................ 281
23.1.1 Block Diagram ....................................................................................................................... 282
23.1.2 Registers ................................................................................................................................ 283
23.2 Dependencies ................................................................................................................................. 285
23.2.1 I/O Pins .................................................................................................................................. 285
23.3 Clocks............................................................................................................................................. 286
23.3.1 Other Registers ...................................................................................................................... 286
23.3.2 Interrupts ................................................................................................................................ 286
23.4 Operation........................................................................................................................................ 286
Chapter 24. Input Capture 287
24.1 Overview ........................................................................................................................................ 287
24.1.1 Block Diagram ....................................................................................................................... 288
24.1.2 Registers ................................................................................................................................ 289
24.2 Dependencies ................................................................................................................................. 290
24.2.1 I/O Pins .................................................................................................................................. 290
24.2.2 Clocks .................................................................................................................................... 290
24.2.3 Other Registers ...................................................................................................................... 290
24.2.4 Interrupts ................................................................................................................................ 290
24.3 Operation........................................................................................................................................ 291
24.3.1 Input-Capture Channel .......................................................................................................... 291
24.3.2 Handling Interrupts ................................................................................................................ 291
24.3.3 Example ISR .......................................................................................................................... 291
24.3.4 Capture Mode ........................................................................................................................ 292

Table of Contents
24.3.5 Count Mode ............................................................................................................................292
24.4 Register Descriptions......................................................................................................................293
Chapter 25. Quadrature Decoder 299
25.1 Overview.........................................................................................................................................299
25.1.1 Block Diagram .......................................................................................................................301
25.1.2 Registers .................................................................................................................................301
25.2 Dependencies ..................................................................................................................................302
25.2.1 I/O Pins ..................................................................................................................................302
25.2.2 Clocks .....................................................................................................................................302
25.2.3 Other Registers .......................................................................................................................302
25.2.4 Interrupts ................................................................................................................................302
25.3 Operation ........................................................................................................................................303
25.3.1 Handling Interrupts ................................................................................................................303
25.3.2 Example ISR ..........................................................................................................................303
25.4 Register Descriptions......................................................................................................................304
Chapter 26. Pulse Width Modulator 307
26.1 Overview.........................................................................................................................................307
26.1.1 Block Diagram .......................................................................................................................309
26.1.2 Registers .................................................................................................................................309
26.2 Dependencies ..................................................................................................................................310
26.2.1 I/O Pins ..................................................................................................................................310
26.2.2 Clocks .....................................................................................................................................310
26.2.3 Other Registers .......................................................................................................................310
26.2.4 Interrupts ................................................................................................................................310
26.3 Operation ........................................................................................................................................311
26.3.1 Handling Interrupts ................................................................................................................311
26.3.2 Example ISR ..........................................................................................................................311
26.4 Register Descriptions......................................................................................................................312
Chapter 27. External I/O Control 315
27.1 Overview.........................................................................................................................................315
27.1.1 External I/O Bus .....................................................................................................................315
27.1.2 I/O Strobes .............................................................................................................................316
27.1.3 I/O Handshake ........................................................................................................................317
27.1.4 Block Diagram .......................................................................................................................318
27.1.5 Registers .................................................................................................................................318
27.2 Dependencies ..................................................................................................................................319
27.2.1 I/O Pins ..................................................................................................................................319
27.2.2 Clocks .....................................................................................................................................319
27.2.3 Other Registers .......................................................................................................................319
27.2.4 Interrupts ................................................................................................................................319
27.3 Operation ........................................................................................................................................320
27.3.1 External I/O Bus .....................................................................................................................320
27.3.2 I/O Strobes .............................................................................................................................320
27.3.3 I/O Handshake ........................................................................................................................320
27.4 Register Descriptions......................................................................................................................321
Chapter 28. Breakpoints 331
28.1 Overview.........................................................................................................................................331
28.1.1 Block Diagram .......................................................................................................................332
28.1.2 Registers .................................................................................................................................333
28.2 Dependencies ..................................................................................................................................334
28.2.1 I/O Pins ..................................................................................................................................334
28.2.2 Clocks .....................................................................................................................................334
28.2.3 Other Registers .......................................................................................................................334
28.2.4 Interrupts ................................................................................................................................334
28.3 Operation ........................................................................................................................................334

Rabbit 5000 Microprocessor User’s Manual
28.3.1 Handling Interrupts ................................................................................................................ 334
28.3.2 Example ISR .......................................................................................................................... 335
28.4 Register Descriptions ..................................................................................................................... 336
Chapter 29. Low-Power Operation 339
29.1 Overview ........................................................................................................................................ 339
29.1.1 Registers ................................................................................................................................ 340
29.2 Operation........................................................................................................................................ 341
29.2.1 Unused Pins ........................................................................................................................... 341
29.2.2 Clock Rates ............................................................................................................................ 341
29.2.3 Short Chip Selects ................................................................................................................. 342
29.2.4 Self-Timed Chip Selects ........................................................................................................ 347
29.3 Register Descriptions ..................................................................................................................... 348
Chapter 30. System/User Mode 351
30.1 Overview ........................................................................................................................................ 351
30.1.1 Registers ................................................................................................................................ 352
30.2 Dependencies ................................................................................................................................. 353
30.2.1 I/O Pins .................................................................................................................................. 353
30.2.2 Clocks .................................................................................................................................... 353
30.2.3 Other Registers ...................................................................................................................... 353
30.2.4 Interrupts ................................................................................................................................ 354
30.3 Operation........................................................................................................................................ 355
30.3.1 Memory Protection Only ....................................................................................................... 355
30.3.2 Mixed System/User Mode Operation .................................................................................... 356
30.3.3 Complete Operating System .................................................................................................. 356
30.3.4 Enabling the System/User Mode ........................................................................................... 357
30.3.5 System/User Mode Instructions ............................................................................................ 358
30.3.6 System Mode Violation Interrupt .......................................................................................... 359
30.3.7 Handling Interrupts in the System/User Mode ...................................................................... 360
30.4 Register Descriptions ..................................................................................................................... 362
Chapter 31. Specifications 369
31.1 DC Characteristics.......................................................................................................................... 369
31.2 AC Characteristics.......................................................................................................................... 371
31.3 Memory Access Times................................................................................................................... 372
31.3.1 Memory Reads ....................................................................................................................... 372
31.3.2 Memory Writes ...................................................................................................................... 372
31.3.3 External I/O Reads ................................................................................................................ 375
31.3.4 External I/O Writes ................................................................................................................ 375
31.3.5 Memory Access Times .......................................................................................................... 378
31.4 Clock Speeds .................................................................................................................................. 381
31.4.1 Recommended Clock/Memory Configurations ..................................................................... 381
31.5 Power and Current Consumption ................................................................................................... 385
31.5.1 Sleepy Mode Current Consumption ...................................................................................... 386
31.5.2 Battery-Backed Clock Current Consumption ........................................................................ 387
Chapter 32. Package Specifications and Pinout 389
32.1 Ball Grid Array Packages............................................................................................................... 389
32.1.1 Pinout 17 × 17 Ethernet Option ............................................................................................. 389
32.1.2 Pinout 17 × 17 Wi-Fi Option ................................................................................................. 390
32.1.3 Mechanical Dimensions and Land Pattern ............................................................................ 391
32.2 Rabbit Pin Descriptions.................................................................................................................. 393
Appendix A. Parallel Port Pins with Alternate Functions 397
A.1 Alternate Parallel Port Pin Outputs ................................................................................................. 397
A.2 Alternate Parallel Port Pin Inputs.................................................................................................... 399

Table of Contents
Appendix B. Rabbit 5000 Errata 401
B.1 Errata ................................................................................................................................................401
Index 405

Rabbit 5000 Microprocessor User’s Manual

Chapter 1 The Rabbit 5000 Processor 13
1. THE RABBIT 5000 PROCESSOR
1.1 Introduction
Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in
small- and medium-scale single-board computers. The first microprocessors were the
Rabbit 2000, Rabbit 3000, and the Rabbit 4000. The latest microprocessor is the Rabbit
5000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and
HD64180 microprocessors in small single-board computers. The Rabbit microprocessors
share a similar architecture and a high degree of compatibility with these microprocessors,
but represent a vast improvement.
The Rabbit 5000 is a high-performance microprocessor with low electromagnetic interfer-
ence (EMI), and is designed specifically for embedded control, communications, and net-
work connectivity. Extensive integrated features and glueless architecture facilitate rapid
hardware design, while a C-friendly instruction set promotes efficient development of
even the most complex applications.
The Rabbit 5000 is the first Rabbit microprocessor to have a full 16-bit internal bus archi-
tecture, providing significant performance improvements when used with external 16-bit
memory devices. It also has the ability to support both 8-bit and 16-bit external memory
devices.
The Rabbit 5000 is also the fastest microprocessor from Rabbit, now a Digi International
brand, running at up to 100 MHz, with compact code and support for up to 16 MB of
memory. Operating with a 1.8 V core and 3.3 V I/O, the Rabbit 5000 boasts eight channels
of DMA, six serial ports with IrDA, 48+ digital I/O, quadrature decoder, PWM outputs,
and pulse capture and measurement capabilities. It also features a battery-backable real-
time clock, glueless memory and I/O interfacing, and ultra-low power modes. Four levels
of interrupt priority allow fast response to real-time events. Its compact instruction set and
high clock speeds give the Rabbit 5000 exceptionally fast math, logic, and I/O performance.
The Rabbit 5000 contains 128 KB of internal high-speed 16-bit SRAM, which can be used
for code and/or data. It is capable of booting off of a standard serial flash, so a microcon-
troller application with no external parallel memory is possible.
The Rabbit 5000 provides two options for network connectivity — a full 10/100Base-T
Ethernet MAC with a standard MII PHY interface, and a wireless 802.11b/g MAC
compatible with several standard Wi-Fi transceivers. The two network interfaces share both
internal resources and I/O pins, and so only one can be enabled at a time.

14 Rabbit 5000 Microprocessor User’s Manual
1.2 Features
The Rabbit 5000 has several powerful design features that practically eliminate EMI prob-
lems, which is essential for OEMs who need to pass CE and regulatory radio-frequency
emissions tests. The amplitude of any electromagnetic radiation is reduced by the internal
spectrum spreader, by gated clocks (which prevent unnecessary clocking of unused regis-
ters), and by separate power planes for the processor core and I/O pins (which reduce
noise crosstalk). An external I/O bus can be used by designers to enable separate buses for
I/O and memory, or to limit loading the memory bus to reduce EMI and ground bounce
problems when interfacing external peripherals to the processor. The external I/O bus
accomplishes this by duplicating the Rabbit's data bus on Parallel Port A, and uses Parallel
Port B to provide the processor's six or eight least significant address lines for interfacing
with external peripherals.
The high-performance instruction set offers both greater efficiency and execution speed of
compiler-generated C code. Instructions include numerous single-byte opcodes that execute
in two clock cycles, 16-bit and 32-bit loads and stores, 16-bit and 32-bit logical and arith-
metic operations, 16 × 16 multiply (executes in 12 clocks), long jumps and returns for
accessing a full 16 MB of memory, and one-byte prefixes to turn memory-access instruc-
tions into internal and external I/O instructions. Hardware-supported breakpoints ease
debugging by trapping on code execution or data reads and writes.
The Rabbit 5000 requires no external memory driver or interface-logic. Its 24-bit address
bus, 8-bit or 16-bit data bus, three chip-select lines, two output-enable lines, and two
write-enable lines can be interfaced directly with up to six memory devices. Up to 1 MB
of memory can be accessed directly via the Dynamic C development software, and up to
16 MB can be interfaced with additional software development. The Rabbit 5000 also
contains 128 KB of internal high-speed 16-bit SRAM, which can be used in addition to
any external memory devices.
A built-in slave port allows the Rabbit 5000 to be used as master or slave in multi-processor
systems, permitting separate tasks to be assigned to dedicated processors. An 8-line data
port and five control signals simplify the exchange of data between devices. A remote cold
boot enables startup and programming via a serial port, a slave port, or from a standard
external serial flash device.
The Rabbit 5000 features six 8-bit parallel ports, yielding a total of 48 digital I/O. Six
CMOS-compatible serial ports are available. All six are configurable as asynchronous
(including output pulses in IrDA format), while four are configurable as clocked serial
(SPI) and two are configurable as SDLC/HDLC. The various internal peripherals share the
parallel port’s I/O pins.
The Rabbit 5000 also offers many specialized peripherals. Two input-capture channels
each have a 16-bit counter, clocked by the output of an internal timer, that can be used to
capture and measure pulses. These measurements can be extended to a variety of functions
such as measuring pulse widths or for baud-rate autodetection. Two Quadrature Decoder
channels each have two inputs, as well as an 8- or 10-bit up/down counter. Each quadrature

Chapter 1 The Rabbit 5000 Processor 15
decoder channel provides a direct interface to optical encoder units. Four independent pulse-
width modulator (PWM) outputs, each based on a 1024-pulse frame, are driven by the out-
put of a programmable internal timer. The PWM outputs can be filtered to create a 10-bit
D/A converter or they can be used directly to drive devices such as motors or solenoids.
Two external interrupt vectors can multiplex inputs from up to six external pins.
The Rabbit 5000 has three timer systems. Timer A consists of ten 8-bit counters, each of
which has a programmed time constant. Six of them can be cascaded from the primary
Timer A counter. Timer B contains a 10-bit counter, two match registers, and two step
registers. An interrupt can be generated or the output pin can be updated when the counter
reaches a match value, and the match value can then be incremented automatically by the
step value. Timer C is a 16-bit counter that counts up to a programmable limit. It contains
eight match registers so that up to four PWM (both synchronous and variable-phase) or
quadrature decoder signals can be created.
The Rabbit 5000 also provides support for protected operating systems. Support for two
levels of operation, known as system and user modes, allow application-critical code to
operate in safety while user code is prevented from inadvertently disturbing the setup of
the processor. Memory blocks as small as 4 KB can be write-protected against accidental
writes by user code, and stack over/underflows can be trapped by high-priority interrupts.
Security features are also available in the Rabbit 5000. Portions of the new instruction set
were introduced to increase encryption algorithm speeds dramatically, and 32 bytes of
battery-backed RAM can store an encryption key away from prying eyes.
The Rabbit 5000 supports eight channels of DMA access to internal or external memory,
internal I/O addresses, and the external I/O bus. Directing a DMA channel to or from an
internal peripheral such as a serial port or the Ethernet port automatically connects DMA
enable signals. Burst size, priority, and guaranteed cycles for the processor are all under
program control.
The Rabbit 5000 contains an 802.11b/g wireless MAC peripheral, also designed to operate
with the DMA peripheral. It includes support for all standard Wi-Fi features, including infra-
structure and ad-hoc modes. The high-speed internal A/D converter and D/A converter
and clocked-serial control port provide a generic interface to several common Wi-Fi
transceivers. A low-speed A/D converter is also available to monitor the transmit signal
strength if desired. The two A/D converters and single D/A converter are available for
customer use when the Wi-Fi peripheral is disabled.
The Rabbit 5000 also contains a full-featured 10/100Base-T Ethernet MAC peripheral.
Designed to operate with the DMA peripheral, the Ethernet peripheral is fully compliant
with the 802.3 Ethernet standard, including support for auto-negotiation, link detection,
multicast filtering, and broadcast addresses. An industry-standard MII interface is used to
connect to an external PHY device.

16 Rabbit 5000 Microprocessor User’s Manual
1.3 Block Diagram
/RESET
/IOWR
/IORD /BUFEN
SMODE0
SMODE1
STATUS
/WDTOUT
CLK
RESOUT
Data
Buffer
Memory
Management/
Control
Address
Buffer Memory Chip
Interface
Parallel Ports
Port A
Port B
Port C
Port D
Port E
Port H
Glo al Power
Save & Clock
Distri ution
Fast
Clock
Timer A
Timer C
Real-Time
Clock
32.768 kHz
Clock Input
Watchdog
Timer
Periodic
Interrupt
External I/O
Chip Interface
External
Interrupts
DATA BUS
(16 its)
D[7:0]
(8-bi mode)
or
D[15:0]
(16-bi mode)
A[23:0]
CLKI
CLKIEN
CLK32K
INT0A, INT1A
INT0B, INT1B
/CS2, /CS1, /CS0
/OE1, /OE0
/WE1, /WE0
PA [7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
TXA, RXA, CLKA,
ATXA, ARXA
TXB, RXB, CLKB,
ATXB, ARXB
TXC, RXC, CLKC
TXD, RXD, CLKD
ADDRESS BUS
(15 its)
Asynch
Serial
Synch
Serial
Asynch
Bootstrap
Synch
Bootstrap
Serial Port A
Asynch Serial IrDA
Serial Ports
B,C,D
Asynch Serial IrDA
Asynch
Serial
Synch
Serial
Serial Ports
E, F
Asynch Serial IrDA
Asynch
Serial
HDLC
SDLC
HDLC/SDLC IrDA
TXE, RXE
TCLKE, RCLKE
Slave Port
Slave Interface
SD[7:0]
SA[1:0],
/SCS, /SRD, /SWR,
/SLAVEATTN
Bootstrap Interface
TXF, RXF
TCLKF, RCLKF
Spectrum
Spreader
Clock
Dou ler
Pulse Width
Modulation
PWM[3:0]
Quadrature
Decoder
QD1A, QD1B
QD2A, QD2B
AQD1A, AQD1B
AQD2A, AQD2B
Input
Capture
PC[7,5,3,1]
PD[7,5,3,1]
PE[7,5,3,1]
IrDA Bootstrap
Timer B
DMA
(8 channels)
25 MHz
DREQ0[B:A]
DREQ1[B:A]
TIMER C[3:0]
Secondary
Watchdog
VBAT RAM
(32 ytes)
battery-
backable
WAIT
ID[7:0]
IA[7:0]
I[7:0]
PH[7:0]
External Interface
CPU
SYSTEM/USER
128K
SRAM
10- it High-Speed
DAC
20 MHz
10- it High-Speed
ADC
10- it slow ADC
802.11a/ /g
Wi-Fi
10/100Base-T
Ethernet
25
shared I/O
{

Chapter 1 The Rabbit 5000 Processor 17
1.4 Basic Specifications
Two versions of the Rabbit 5000 are available—the standard 289-ball BGA and a compact
196-ball BGA for specialty Wi-Fi applications. The larger package is intended for most
Rabbit applications; the smaller package has specific features and limitations, and is not
presently offered for sale. If you need further information, please contact your Rabbit sales
representative.
Table 1-1. Rabbit 5000 Specifications and Features
Package 289-ball BGA 196-ball BGA
Package Size 15 mm × 15 mm × 1.4 mm 12 mm × 12 mm × 1.2 mm
Operating Voltage 1.8 V DC core, 3.3 V DC I/O ring
Operating Current 0.57 mA/MHz @ 1.8 V/3.3 V
(Wi-Fi and Ethernet diabled)
Operating Temp. -40°C to +85°C
Maximum Clock Speed 100 MHz
Digital I/O 48+ (arranged in
six 8-bit ports) 19
Network Interfaces 10/100Base-T
802.11b/g Wi-Fi 802.11b/g Wi-Fi
Serial Ports 6 CMOS-compatible 2 CMOS-compatible
Baud Rate Clock speed/8 max. asynchronous
Address Bus 20/24-bit 8-bit
Data Bus 8/16-bit 8/16-bit
Timers Ten 8-bit, one 10-bit with 2 match registers,
and one 16-bit with 8 match registers
Real-Time Clock Yes, battery-backable
RTC Oscillator Circuitry External
Watchdog Timer/Supervisor Yes
Clock Modes 1×, 2×, /2, /3, /4, /6, /8
Power-Down Modes Sleepy (32 kHz)
Ultra-Sleepy (16, 8, 2 kHz)
External I/O Bus 8 data, 8 address lines No
A/D Converters 10-bit, 2 synchronous channels, up to 40 megasamples/s
10-bit, single channel, up to 300 ksamples/s
D/A Converters 10-bit, 2 synchronous channels, up to 40 megasamples/s

18 Rabbit 5000 Microprocessor User’s Manual
1.5 Comparing Rabbit Microprocessors
The Rabbit 2000, Rabbit 3000, Rabbit 4000, and Rabbit 5000 features are compared
below.
Feature Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000
Maximum Clock Speed, industrial
Maximum Clock Speed,
commercial
100 MHz
100 MHz
60 MHz
60 MHz
55.5 MHz
58.8 MHz
30 MHz
30 MHz
Maximum Crystal Frequency
Main Oscillator (may be doubled
internally up to maximum clock
speed)
100 MHz 60 MHz 30 MHz 30 MHz
32.768 kHz Crystal Oscillator External External External Internal
Operating Voltage, core
Operation Voltage, I/O
1.8 V ± 10%
3.3 V ± 10%
1.8 V ± 10%
3.3 V ± 10% 3.3 V ± 10% 5.0 V ± 10%
Maximum I/O Input Voltage 3.6 V 3.6 V 5.5 V 5.5 V
Current Consumption
0.57 mA/MHz
@ 1.8 V/3.3 V
(Wi-Fi and
Ethernet
disabled)
0.35 mA/MHz
@ 3.3 V
2 mA/MHz
@ 3.3 V
4 mA/MHz
@ 5 V
Number of Package Pins 289/196 128 128 100
Size of Package, LQFP/PQFP
Spacing Between Package Pins N/A 16
× 16 × 1.5 mm
0.4 mm (16 mils)
16 × 16 × 1.5 mm
0.4 mm (16 mils)
24
× 18 × 3 mm
0.65 mm (26 mils)
Size of Package, BGA (mm)
Spacing Between Package Pins
15
× 15 × 1.4
12
× 12 × 1.2
0.8 mm
10
× 10 × 1.2
0.8 mm
10 × 10 × 1.2
0.8 mm
Not available
Separate Power and Ground for
I/O Buffers (EMI reduction) Yes Yes Yes No
Clock Spectrum Spreader Yes Yes Yes Rabbit 2000B/C
Clock Modes 1×, 2×, /2, /3,
/4, /6, /8
1×, 2×, /2, /3,
/4, /6, /8
1x, 2x, /2, /3
/4, /6, /8 1x, 2x, /4, /8
Powerdown Modes, sleepy
Powerdown Modes, ultra sleepy
32 kHz
16, 8, 4, 2 kHz
32 kHz
16, 8, 4, 2 kHz
32 kHz
16, 8, 4, 2 kHz
32 kHz
Low-Power Memory Control
Short and
Self-Timed
Chip Selects
Short and
Self-Timed
Chip Selects
Short and
Self-Timed
Chip Selects
None
Extended Memory Timing for
High-Frequency Operation Ye s Ye s Yes No
Numberof8-bitI/OPorts 6575

Chapter 1 The Rabbit 5000 Processor 19
Auxiliary I/O Data/Address Bus Yes Yes Yes None
NumberofSerialPorts 6664
Serial Ports Capable of SPI/
Clocked Serial 4 (A, B, C, D) 4 (A, B, C, D) 4 (A, B, C, D) 2 (A, B)
Serial Ports Capable of SDLC/
HDLC 2 (E, F) 2 (E, F) 2 (E, F) None
Asynch Serial Ports With Support
for IrDA Communication 666None
Serial Ports with Support for
SDLC/HDLC IrDA
Communication
222None
Maximum Asynchronous Baud
Rate Clock Speed/8 Clock Speed/8 Clock Speed/8 Clock Speed/32
Ethernet Port 10/100Base-T 10Base-T None None
Wi-Fi Yes No No No
PWM Outputs 4 4 4 None
Variable-Phase PWM Outputs
(PPM) 4 4 None None
Input Capture Units 2 2 2 None
Quadrature Decoders 2 channels 2 channels 2 channels None
Feature Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000

20 Rabbit 5000 Microprocessor User’s Manual