Diodes PI6CG18801 Mounting instructions

____________________________________________________________________________________________________________
ORIGINATE DATE: Mar, 2017
EDIT DATE: Mar, 2017
DOCUMENT-REV 1.0
Page 1 of 4
Diodes Incorporated (Milpitas office)
1545 Barber Lane, Milpitas, CA 95035 U.S.A.
PI6CG18801 EVB Use Manual
Timing Application Engineering
1.1 Introduction
PI6CG18801 is 1.8V PCIe clock generator family product. Its low power HCSL output makes the IC has very low power
consumption in high performance to comply with PCIe 1.0, 2.0, and 3.0 PCI_SIG.org reference clock waveform and jitter
specifications. This doc. is to provide the EVB use guide and test example.
1.2 DUT Reference
1. Datasheet
2. EVB PCB and schematic
3. Device application circuit
1.3 EVB Photo and Test Diagram
1) EVB photo and connection guide
2) LP_HCSL test diagram
1.3 Equipment
Agilent DC supply: E3631A
Tektronix real time scope 20G/S: TDS7404
2.1 Summary
i) The EVB has total current Idd= 17[email protected];
ii) The single output waveform Tr/Tf = 363/389ps; Vamp = 806mV
iii) differential output waveform Tr/Tf =406/415ps; Vamp = 1.62V
iv) The EVB meets design spec.

____________________________________________________________________________________________________________
ORIGINATE DATE: Mar, 2017
EDIT DATE: Mar, 2017
DOCUMENT-REV 1.0
Page 2 of 4
Diodes Incorporated (Milpitas office)
1545 Barber Lane, Milpitas, CA 95035 U.S.A.
3.1 Test Reference Waveform
1) Tek scope single end probe waveform
2) Tek scope differential probe waveform

____________________________________________________________________________________________________________
ORIGINATE DATE: Mar, 2017
EDIT DATE: Mar, 2017
DOCUMENT-REV 1.0
Page 3 of 4
Diodes Incorporated (Milpitas office)
1545 Barber Lane, Milpitas, CA 95035 U.S.A.
3.2 EVB PCB Layout
3.3 EVB Schematic
DIF0#
VDDA1.5/1.8
C12
0.1uF
DIF1#
JP2
1 2 3
DIF3#
JP7
1 2
DIF3
SDATA_3.3
GNDREF
DIF2
C25
22pF
R24 0
R19
0
VDD1.5/1.8
DIF5#
R17
0
VDDREF1.5/1.8
JP35
1 2
vOE5#
VDDDIG1.5/1.8
vOE3#
R6
4.7k_0402
1 2
Install 2pF
underneath
JPxx
VDD1.5/1.8
SDATA_3.3
POW_IN
SCLK_3.3
vOE2#
POW_IN
JP5
1 2
JP26
1
2
R20 0
POW_IN
C7
10nF
JP9
1
2
3
POW_IN
R8
4.7k_0402
1 2
C6
0.1uF
vOE5#
XIN/CLK25
DIF5
JP6
1 2
VDDA1.5/1.8
POW_IN
C17
10nF
R25 0
VDDDIG1.5/1.8
JP10
1
2
3
JP1
1 2 3
POW_IN
JP16
1
2
3
VDDIO
vOE6#
DIF4#
R16
0
DIF0#
C14
0.1uF
JP21
1
2
3
C11
10nF
JP34
1 2
GNDXTAL
JP24
1
2
vOE2#
DIF6#
C20
0.1uF
SADR/REF1.8
C4
0.1uF
C5
10nF
R3
33_0402
12
JP11
1 2
JP3
1 2
C16
0.1uF
R30
None_BOM
JP15
1
2
3
GNDDIG
^CKPWRGD_PD#
C9
10nF
GNDA
R15
0
JP12
1
2
3
C22
0.1uF JP30
1 2
DIF5
VDDIO
vSS_EN_tri
R11
4.7k_0402
1 2
R29 0
vOE3#
C19
10nF
DIF2#
C8
0.1uF
DIF0
JP17
1
2
3
JP27
1
2
POW_IN
R31
4.7k_0402
1 2
vOE7#
^CKPWRGD_PD#
SCLK_3.3
DIF7
JP20
1
2
3
R27 0
JP32
1 2
DIF2#
DIF3
JP25
1
2
SADR/REF1.8
R14
0
R4
4.7k_0402
1 2
R23 0
JP33
1 2
DIF4
vOE6#
R26 0
DIF7#
vOE4#
DIF6
C18
0.1uF
JP18
1
2
3
POW_IN
C13
10nF
DIF1
R5
4.7k_0402
1 2
JP13
1
2
3
XIN/CLK25
POW_IN
DIF0
DIF6#
JP19
1
2
3
5 inch tranmission line
DIF7
GND
JP14
1
2
3
POW_IN
GND
C21
10nF
Y1
25M_CL=18pF
R10
4.7k_0402
1 2
POW_IN
VDDREF1.5/1.8
DIF1#
vSS_EN_tri
R21 0
1-2 inch TL
vOE1#
vOE7#
DIF7#
vOE4#
JP23
1
2
vOE0#
R7
4.7k_0402
1 2
POW_IN
DIF6
DIF5#
JP4
1 2
U1
PI6CG18801ZLE@TQFN48
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
37 38 39 40 41 42 43 44 45 46 47 48 49
SS_SEL_TRI
GND_XTAL
XTAL_IN/CLK
XTAL_OUT
VDD_OSC
VDD_REFOUT
SADR/REFOUT
GND_REFOUT
GND_DIG
SCLK
SDATA
VDD_DIG
VDDO OE0# Q0+ Q0- OE1# Q1+ Q1- VDD VDDO GND Q2+ Q2-
OE2#
Q3+
Q3-
OE3#
GNDA
VDDA
VDDO
Q4+
Q4-
OE4#
Q5+
Q5-
OE5#
VDD
VDDO
GND
Q6+
Q6-
OE6#
Q7+
Q7-
OE7#
VDDO
PD#
HGND
JP36
1 2
5 inch tranmission line
DIF4#
Install 2pF
underneath
JPxx
VDD1.5/1.8
DIF4
R28 0
R18
0
JP8
1 2 C23
10nF
C24
0.1uF
VDDXTAL
VDDIO
R9
4.7k_0402
1 2
C3
10nF
R22 0
X2
JP22
1
2
3
JP38
1 2
DIF3#
C2
0.1uF
+
EC1
1000u
vOE1#
DIF2
DIF1
R2
4.7k_0402
1 2
R13
4.7k_0402
1 2
VDDIO
JP29
1 2
VDDIO
JP39_None_BOM
1
2
VDDIO
C1
10u_0805
C26
22pF
C15
10nF
JP28
1
2
JP37
1 2
X2
C10
0.1uF
POW_IN
vOE0#
R1
4.7k_0402
1 2
VDDXTAL
POW_IN
R12
4.7k_0402
1 2
JP31
1 2

____________________________________________________________________________________________________________
ORIGINATE DATE: Mar, 2017
EDIT DATE: Mar, 2017
DOCUMENT-REV 1.0
Page 4 of 4
Diodes Incorporated (Milpitas office)
1545 Barber Lane, Milpitas, CA 95035 U.S.A.
3.4 PI6CG18801 Application Circuit
Document History
Revision
Date
Description
Author
1.0
Mar, 2017
1st rev. doc
Timing AE
Q1-
None for
SSC off
* C1=C2=8pF for CL=8pF
crystal , other CL value
crystal use C1=C2=2xCL-8
Q7+
R20 0
None for
SSC on
OE4#
PCIE_100M_3_P
+
10u
R2 1k
R25 0
CLK3_P
PCIE_100M_2_N
C7
1u
Q6-
U1
PI6CG18801
1
2
3
4
5
6
7
8
9
10
25
35
36
37
43
42
41
40
39
38
11
12
13
14
15
16
17
18
19
20
21
22
23
24 26
27
28
29
30
31
32
33
34
44
45
46
47
48
SS_SEL
GND_XTAL
XTAL_IN
XTAL_OUT
VDD_OSC
VDD_REFOUT
SADR/REFOUT
GND_REFOUT
GND_DIG
SCLK
OE2#
Q5+
Q5-
OE5#
OE6#
Q6-
Q6+
GND
VDDO
VDD
SDATA
VDD_DIG
VDDO
OE0#
Q0+
Q0-
OE1#
Q1+
Q1-
VDD
VDDO
GND
Q2+
Q2- Q3+
Q3-
OE3#
GNDA
VDDA
VDDO
Q4+
Q4-
OE4#
Q7+
Q7-
OE7#
VDDO
PD#
R1 1k
REFOUT
Q7-
App Note:
XIN
C6
0.1u
OE2#
CLK5_P
CLK7_P
1.8V
Q3-
PD#
Q6+
R29 0
PCIE_100M_7_P
SMBUS_CLK
VDDA
VDD_OSC_DIG
CLK5_N
C9
1u
1.8V
SDATA
CLK2_P
Q4+
Q6-
R5
1k
SCLK
4. Since OSC pin cap.=5pF so select CL=8pF crystal can C1=C2=8pF,
other CL value crystal C1=C2=2xCL-5-3, 3 is C_stray pF
C8
0.1u
C13
1u
Q1+
Q1+
25M CMOS for LAN
Ref. CLK
Q2+
3. This is LP-HCSL type output: serial 0 ohm is optional, but it can be
replace in 5 to 15 ohm for the optimal fine tune the board RX end wavefrom
for different trace length if needed
25M CL=8pF
+
10u
Q2+
CLK0_P
PCIE_100M_3_N
R23 0
CLK7_N
1.8V
Q7+
PD#
R3
33
R35 0
PCIE_100M_1_N
CLK2_N
R4
1k
R31 0
Q5-
R34 0C12
0.1u
Q0+
Q3+
R21 0
R17 1
CLK6_N
Q5+
R33 0
R24 0OE7#
Q1-
R30 0
Q2-
VDDO
SS_SEL
R32 0
1.8V
C10
0.1u
R18 1.5
+
10u
7. OEx# pins have internal pull-up, can be left open
Put
closepin
<300mil
R22 0
OE5#
C11
1u
1. All VDD pin needs 0.1u +1uF decoupling cloase to pin
XOUT
C3
1u
PCIE_100M_4_P
OE3#
CLK4_P
PCIE_100M_5_P
Q2-
CLK1_P
C1
*8p
6. Make LVDS clock, it needs AC coupling and then RX side use pull-up/down Rs
to bias LVDS level, refer to datasheet;
PCIE_100M_0_N
Q5-
PCIE_100M_0_P
PCIE_100M_6_N
8 Low Power
HCSL Output
Or FB
Put close to pin
<300mil
PCIE_100M_4_N
2. VDDA, VDDOSC use small R+C filtering for better DC/DC ripple noise rejection
OE1#
CLK3_N
Q0+
PCIE_100M_1_P
OE0#
Q3-
SMBUS_DATA
Q4+
Q0-
CLK1_N
CLK0_N
CLK4_N
SS_SEL
1.8V
R26 0
5. Note SSC_EN and SMBUS address pins are power on latch once set;
Q3+
OE6#
R27 0
PCIE_100M_6_P
Q0-
PCIE_100M_2_P
C2
*8p
R6
1k
Q5+
X1
1
23
4
CLK6_P
PCIE_100M_7_N
R28 0
Q6+
C5
0.1u
Or FB
Q4-
Q7-
C4
0.1u
PCIE_100M_5_N
Q4-