e2v AT84CS001-EB User manual

AT84CS001-EB Evaluation Board
..............................................................................................
User Guide

AT84CS001-EB Evaluation Board User Guide i
0904C–BDC–09/07
Table of Contents
Section 1
Introduction ............................................................................................. 1
1.1 Scope ..............................................................................................................1
1.2 Description ......................................................................................................1
Section 2
Hardware Description ............................................................................. 1
2.1 Board Structure 1
2.2 Data and Clock Input Accesses ......................................................................2
2.3 Digital Output 2
2.4 ASYNCRST .................................................................................................... 3
2.5 Standalone Delay Cell .................................................................................... 3
2.6 DMUX Functions............................................................................................. 3
2.7 Power Supplies ...............................................................................................3
Section 3
Operating Characteristics ....................................................................... 1
3.1 Introduction .....................................................................................................1
3.2 Operating Procedure ......................................................................................1
3.3 Electrical Characteristics ................................................................................2
Section 4
Application Information ........................................................................... 1
4.1 Introduction ..................................................................................................... 1
4.2 Input Data .......................................................................................................1
4.3 Digital Outputs ................................................................................................ 1
4.4 DMUX Functions .............................................................................................2
4.4.1 ASYNCRST ..............................................................................................2
4.4.2 CLKDACTRL ............................................................................................2
4.4.3 DACTRL ...................................................................................................3
4.4.4 RS, DRTYPE, DAEN, BIST, CLKTYPE, SLEEP, STAGG .......................4
4.5 Test bench Description ...................................................................................6
Section 5
Package Information ............................................................................... 1
5.1 AT84CS001 Pinout .........................................................................................1
5.2 Package Outline .............................................................................................5
Section 6

ii AT84CS001-EB Evaluation Board User Guide
0904C–BDC–09/07
Ordering Information ............................................................................... 1
Section 7
Appendix ................................................................................................. 1
7.1 AT84CS001-EB Electrical Schematics ...........................................................1
7.2 AT84CS001-EB Board Layers ........................................................................5

AT84CS001-EB Evaluation Kit User Guide 1-1
0904C–BDC–09/07
Section 1
Introduction
1.1 Scope The AT84CS001-EB Evaluation Kit is designed to facilitate the evaluation and charac-
terization of the AT84CS001 1:2/4 10-bit 2.2 GHz DMUX up to 2.2 GHz.
The AT84CS001-EB Evaluation Kit includes
The 1:2/4 10-bit 2.2 GHz DMUX Evaluation Board
Five SMA caps for DAI, DAIN, DAO, DAON and ASYNCRST signals
Seven jumpers for the DMUX function settings (RS, BIST, CLKTYPE, DRTYPE,
SLEEP, STAGG, DAEN)
This user guide uses the AT84CS001-EB evaluation Kit as an evaluation and demon-
stration platform and provides guidelines for its correct use.
1.2 Description The AT84CS001-EB evaluation board is very straightforward as it only implements the
AT84CS001 1:2/4 10-bit 2.2 GHz DMUX device, SMA connectors for the standalone
delay cell inputs and outputs and for the reset input accesses and 2.54 mm pitch con-
nectors compatible with high-speed acquisition system probes.
This evaluation board is fully compatible with e2v high-speed ADC boards
(TSEV830500GL, TSEV8388BGL/GLZA2/F/FZA2, TSEV83102G0BGL and
AT84AS008GL-EB).
To achieve optimal performance, the AT84CS001-EB evaluation board was designed in
a 4-metal-layer board with RO4003 200 and FR4 HTG dielectric layers. The board
implements the following devices:
The 1:2/4 10-bit 2.2 GHz DMUX Evaluation board
Five SMA caps for DAI, DAIN, DAO, DAON and ASYNCRST signals
Seven jumpers for the DMUX function settings (RS, BIST, CLKTYPE, DRTYPE,
SLEEP, STAGG, DAEN)
2.54 mm pitch connectors for the digital inputs and outputs, compatible with high-
speed acquisition system probes
Banana jacks for the power supply accesses
Potentiometers for the DMUX control functions

Introduction
1-2 AT84CS001-EB Evaluation Kit User Guide
0904C–BDC–09/07
The board is comprised of four metal layers for signal traces, ground and power supply
layers, and three dielectric layers featuring low insertion loss and enhanced thermal
characteristics for operation in the high frequency domain.
The board dimensions are 220 mm x 230 mm.
The board comes fully assembled and tested, with the AT84CS001 installed.
Figure 1-1. Simplified Schematics of the AT84CS001-EB Evaluation Board
As shown in Figure 1-1, different power supplies are required:
V
CCD
= 3.3V digital positive power supply
V
PLUSD
= 2.5V digital output power supply
3.3V used for the DMUX functions
PIN 1
Port D
Port C
Port B
Port A
DMUX functions
ASYNCRST
3.3V GND
DAO/DAON
G
N
D
DR
DAI/DAIN
AT84CS001
V-GND
I-GND
Data and Clock
Inputs
CLKDACTRL
DACTRL
V
+
D
V
C
C
D
VCCD
3.3V
G
N
D

AT84CS001-EB Evaluation Kit User Guide 2-1
0904C–BDC–09/07
Section 2
Hardware Description
2.1 Board Structure In order to achieve optimum full-speed operation of the AT84CS001 1:2/4 10-bit 2.2
GHz DMUX, a multi-layer board structure was retained for the evaluation board. Four
copper layers are used, respectively dedicated to the signal traces, ground planes and
power supply planes.
The board is made in RO4003 200 µm and FR4 HTG epoxy dielectric materials.
The following table gives a detailed description of the board's structure.
Table 2-1. Board Structure
Layer Characteristics
Layer 1
Copper layer
Copper thickness = 40 µm
Input and output signals traces = 50Ω
microstrip lines
Layer 2
RO4003 dielectric layer
(Hydrocarbon/wovenglass)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
- 0.044 dB/inch insertion loss at 2.5 GHz
- 0.318 dB/inch insertion loss at 18 GHz
Layer 3
Copper layer
Copper thickness = 35 µm
Upper ground plane = reference plane
Layer 4
FR4 HTG/dielectric layer Layer thickness = 1050 µm
Layer 5
Copper layer
Copper thickness = 35 µm
Power planes = 3.3V, V
CCD
and V
PLUSD
Layer 6
FR4 HTG/dielectric layer Layer thickness = 200 µm
Layer 7
Copper layer
Copper thickness = 40 µm
Lower ground plane = reference plane

Hardware Description
2-2 AT84CS001-EB Evaluation Kit User Guide
0904C–BDC–09/07
The board is 1.6 mm thick.
The digital data input, output and reset signals are located on the top metal layer.
The function signals are located on the top metal layer and layer 7.
The ground planes are located on layer 3 and 7.
Layer 5 is dedicated to the power supplies (3.3V, V
CCD
and V
PLUSD
).
2.2 Data and Clock
Input Accesses
Access to the digital data and clock inputs is provided by one female 2.54 mm pitch con-
nector (points) via 50Ωmicrostrip lines.
The connector is made of two rows:
The upper row is dedicated to the data and clock signals
The lower row is connected to ground
Each differential signal pair is separated by a connection to ground, as illustrated in
Figure 2-1
Figure 2-1. Input Data Connector
The input lines are matched (in length) within ±1 mm.
Note: 100Ωtermination is provided on-chip.
2.3 Digital Output Access to the digital data and clock outputs is provided by four male 2.54 mm pitch con-
nectors (points) via 50Ωmicrostrip lines.
The connector is made of two rows:
The upper row is dedicated to the data and clock signals
The lower row is connected to ground
Each output port is separated by a connection to ground, as illustrated in Figure 2-2 on
page 2-3.
GND I9 I9N GND GND I0 I0N GND
GND GND GND GND GND GND GND GND
IOR IORN GND
GND GND GND

Hardware Description
AT84CS001-EB Evaluation Kit User Guide 2-3
0904C–BDC–09/07
Figure 2-2. Output Data Connector
The digital outputs are compatible with LVDS standard. They are on-board 100Ωdiffer-
entially terminated as described in Figure 2-3.
Figure 2-3. Differential Digital Outputs Implementation
The output lines are matched (in length) within ± 5 mm.
2.4 ASYNCRST Access to the asynchronous reset is provided by both an SMA connector and a push
button.
2.5 Standalone
Delay Cell
Access to the standalone delay cell inputs (DAI/DAIN) and outputs (DAO/DAON) is pro-
vided by SMA connectors via 50Ωmicrostrip lines.
Note: The 100Ωtermination for the DAI/DAIN inputs is provided on-chip, the
DAO/DAON outputs are floating (must be terminated by 100Ωtermination).
2.6 DMUX Functions Two potentiometers are provided for the DMUX input clock delay control (CLKDACTRL)
and the standalone delay cell control (DACTRL).
Seven jumpers are provided for the RS, BIST, DAEN, SLEEP, STAGG, CLKTYPE and
DRTYPE functions (jumper on board = logic 0).
2.7 Power Supplies Layer 5 is dedicated to power supply planes (3.3V, V
CCD
and V
PLUSD
).
The supply traces are low impedance and are surrounded by two ground planes (layers
3 and 7).
V
CCD
and 3.3V have separated planes but can be short-circuited on the board. The 3.3V
supply was separated from V
CCD
for device power consumption testing purposes.
Each incoming power supply is bypassed at the banana jack by a 1 µF Tantalum capac-
itor in parallel with a 100 nF chip capacitor.
GND A0N A0 A1N
AORN/
DRA
AOR/
DRAN
GND B0
GND GND GND GND GND GND GND GND
Data
DataN
100Ω
50Ωline
50Ωline

Hardware Description
2-4 AT84CS001-EB Evaluation Kit User Guide
0904C–BDC–09/07
Each power supply is decoupled as close as possible to the AT84CS001 device by
10 nF in parallel with 100 pF surface mount chip capacitors.
Note: The decoupling capacitors are superimposed with the 100 pF capacitor
mounted first.