e2v TSEV8388B User manual

ADC 8-bit 1 Gsps TSEV8388B
Evaluation Board
..............................................................................................
User Guide

TSEV8388B - Evaluation Board User Guide i
0973D–BDC–02/09
e2v semiconductors SAS 2009
Table of Contents
Section 1
Overview............................................................................................... 1-1
1.1 Description ................................................................................................1-1
1.2 TSEV8388B Evaluation Board ..................................................................1-2
1.3 Board Mechanical Characteristics.............................................................1-3
1.4 Analog Input, Clock Input and De-embedding Fixture Accesses ..............1-4
1.5 Digital Outputs Accesses ..........................................................................1-4
1.6 Power Supplies and Ground Accesses.....................................................1-4
1.7 ADC Functions Settings Accesses............................................................1-4
Section 2
Layout Information ................................................................................ 2-1
2.1 Board ........................................................................................................2-1
2.2 AC Inputs/Digital Outputs..........................................................................2-1
2.3 DC Functions Settings ..............................................................................2-1
2.4 Power Supplies .........................................................................................2-2
2.5 TS8388B On-board Implementation .........................................................2-2
Section 3
Operating Procedures and
Characteristics ...................................................................................... 3-1
3.1 Introduction ...............................................................................................3-1
3.2 Operating Procedure.................................................................................3-1
3.3 Electrical Characteristics...........................................................................3-2
3.4 Operating Charcteristics............................................................................3-3
Section 4
Application Information ......................................................................... 4-1
4.1 Introduction ...............................................................................................4-1
4.2 Analog Inputs ............................................................................................4-1
4.3 Clock Inputs ..............................................................................................4-1
4.4 Setting the Digital Output Data Format .....................................................4-1
4.5 ADC Gain Adjust .......................................................................................4-2
4.6 SMA Connectors and Microstrip Lines De-embedding Fixture .................4-2
4.7 Temperature Monitoring and Data Ready Reset Function........................4-3
4.7.1 TS8388B ADC Diode Junction Temperature Measurement Setup ....4-3
4.8 Data Ready Output Signal Reset ..............................................................4-4
4.9 Test Bench Description .............................................................................4-5

Table of Contents
ii TSEV8388B - Evaluation Board User Guide
0973D–BDC–02/09
e2v semiconductors SAS 2009
Section 5
Package Description............................................................................. 5-1
5.1 TS8388BGL Pinout ...................................................................................5-1
5.2 TS8388BF/TS8388BFS Pinout .................................................................5-3
5.3 CBGA68 Thermal Characteristics .............................................................5-5
5.3.1 Thermal Resistance from Junction to Ambient: Rthja ........................5-5
5.3.2 Thermal Resistance from Junction to Case: Rthjc .............................5-5
5.3.3 CBGA68 Board Assembly with External Heatsink..............................5-5
5.4 Nominal CQFP68 Thermal Characteristics ...............................................5-6
5.4.1 Thermal Resistance from Junction to Ambient: Rthja ........................5-6
5.4.2 Thermal Resistance from Junction to Case: Rthjc .............................5-6
5.4.3 CBGA68 Board Assembly with External Heatsink..............................5-7
5.5 Enhanced CQFP68 Thermal Characteristics ............................................5-8
5.5.1 Enhanced CQFP68 ............................................................................5-8
5.5.2 Thermal Resistance from Junction to Case: Rthjc .............................5-8
5.5.3 Heatsink..............................................................................................5-8
5.6 Ordering Information .................................................................................5-9
Section 6
Schematics ........................................................................................... 6-1
6.1 TSEV8388B Electrical Schematics ...........................................................6-1
6.2 Evaluation Board Schematics ...................................................................6-4
6.2.1 CBGA68 Option..................................................................................6-4
6.2.2 CQFP68 Option ........................................................................................6-6

TSEV8388B - Evaluation Board User Guide 1-1
0973D–BDC–02/09
e2v semiconductors SAS 2009
Section 1
Overview
1.1 Description The TSEV8388B Evaluation Board (EB) is a prototype board which has been designed
in order to facilitate the evaluation and the characterization of the TS8388B device up to
its 1.8 GHz full power bandwidth at up to 1 Gsps in the extended temperature range.
The high speed of the TS8388B requires careful attention to circuit design and layout to
achieve optimal performance. This four metal layer board with internal ground plane has
the adequate functions in order to allow a quick and simple evaluation of the TS8388B
ADC performances over the temperature range.
The TS8388B Evaluation Board (EB) is very straightforward as it only implements the
TS8388B ADC device, SMA connectors for input/output accesses and a 2.54 mm pitch
connector compatible with high frequency acquisition system probes.
The board also implements a de-embedding fixture in order to facilitate the evaluation of
the high frequency insertion loss of the inputs microstrip lines, and a die junction tem-
perature measurement setting.
The board is constituted by a sandwich of two dielectric layers, featuring low insertion
loss and enhanced thermal characteristics for operation in the high frequency domain
and extended temperature range.
The board dimensions are 130 mm x 130 mm.
The board set comes fully assembled and tested, with the TS8388B installed and
heatsink.
The 8-bit 1 Gsps ADC evaluation board is fully compatible with its companion device
evaluation board (TSEV81102G0 DMUX).

Overview
1-2 TSEV8388B - Evaluation Board User Guide
0973D–BDC–02/09
e2v semiconductors SAS 2009
1.2 TSEV8388B
Evaluation Board
Figure 1-1. TSEV8388B Block Diagram
CLK
CLKB
Differential
Clock inputs
Z0 = 50Ω
Z0 = 50Ω
CLK
CLKB
TS8388B
VIN
VINB
Differential
Clock inputs
Gray or Binary
Output Data Select
Z0 = 50Ω
Z0 = 50Ω
VIN
VINB
ADC Gain Adjust
GAIN/GND
VCC
GORB GORB
DR/DRB
D0/D0B
Z0 = 50Ω
MC100EL16
Differential Receivers
(optional)
Digital Output
Data
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
D7/D7B
OR/ORB
VCC VCC = +5V
GND
VPLUSD
GND = 0V
VPLUSD = 0V (ECL)
VPLUSD = 2.4V (LVDS)
AVEE
DVEE
DIOD/DRRB
VEEA = -5V
VEED = -5V
J - diode
V - diode
DRRB V-GND
V-GND
(Deembedding fixture)
CAL1
CAL2
CAL3
CAL4
L = 65 mm typ = LVIN/VINb
= LCLK/CLKb
L = 18 mm typ
+5V
VCC
-5V
VEET
-2V
VDD
-5V
VEEA
GND -5V
VEED
Short-circuit
possibility
here MC100EL16 SUPPLIES

Overview
TSEV8388B - Evaluation Board User Guide 1-3
0973D–BDC–02/09
1.3 Board
Mechanical
Characteristics
The board layer’s number, thickness, and functions are given below, from top to bottom.
The TSEV8388B is a seven-layer PCB constituted by four copper layers and three
dielectric layers.
The four metal layers correspond respectively from top to bottom to the AC and DC sig-
nals layer (layer 1), two ground layers (layers 3 and 5), and one supply layer (layer 7).
The upper inner ground plane (layer 3) constitutes the reference plane for the 50Ω
impedance signal traces. The lower inner ground plane (layer 5) is used for dielectric
substrate rigidity and is a replica of the upper ground plane.
The backside metal layer is dedicated to the power supplies planes, surrounded by a
ground plane.
The three dielectric layers are respectively (from top to bottom) constituted by a low
insertion loss dielectric layer (RO4003) (layer 2) and two parallel BT/Epoxy dielectric
layers (layers 4 and 6).
Considering the severe mechanical constraints due to the wide temperature range and
the high frequency domain in which the board is to operate, it is necessary to use a
sandwich of two different dielectric materials, with specific characteristics:
A low insertion loss RO4003 Hydrocarbon/wovenglass dielectric layer of 200 µm
thickness, chosen for its low loss (–0.318 dB/inch) and enhanced dielectric
consistency in the high frequency domain. The RO4003 dielectric layer is dedicated to
the routing of the 50Ωimpedance signal traces (the RO4003 typical dielectric
constant is 3.4 at 10 GHz). The RO4003 dielectric layer characteristics are very close
to PTFE in terms of insertion loss characteristics.
A BT/Epoxy dielectric layer of 2 mm total thickness which is sandwiched between the
upper ground plane and the back-side supply layer.
Table 1-1. Board Layers Thickness Profile
Layer Characteristics
Layer 1
Copper layer
Copper thickness = 35 µm
AC signals traces = 50Ωmicrostrip lines
DC signals traces (GORB, GAIN, DIODE)
Layer 2
RO4003 dielectric layer
(Hydrocarbon/Wovenglass)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
–0.044 dB/inch insertion loss at 2.5 GHz
–0.318 dB/inch insertion loss at 18 GHz
Layer 3
Copper layer
Copper thickness = 35 µm
Upper ground plane = reference plane 50Ωmicrostrip return
Layer 4
BT/Epoxy dielectric layer
Layer thickness = 630 µm
Layer 5
Copper layer
Copper thickness = 35 µm
Lower ground plane (board mechanical rigidity)
Layer 6
BT/Epoxy dielectric layer
Layer thickness = 630 µm
Layer 7
Copper layer
Copper thickness = 35 µm
Power planes = VEEA, VEED, VEET , VDD, VCC, VPLUSD ground plane

Overview
1-4 TSEV8388B - Evaluation Board User Guide
0973D–BDC–02/09
e2v semiconductors SAS 2009
The BT/Epoxy layer has been chosen because of its enhanced mechanical characteris-
tics for elevated temperature operation. The typical dielectric constant is 4.5 at 1 MHz.
More precisely, the BT/Epoxy dielectric layer offers enhanced characteristics compared
to FR4 Epoxy, namely:
Higher operating temperature value: 170°C (125°C for FR4).
Better with standing of thermal shocks (–65°C up to 170°C).
The total board thickness is 2.6 mm. The previously described mechanical and fre-
quency characteristics makes the board particularly suitable for the device evaluation
and characterization in the high frequency domain and in the military temperature range.
1.4 Analog Input,
Clock Input and
De-embedding
Fixture Accesses
The differential active inputs (Analog, Clock, De-embedding fixture) are provided by
SMA connectors.
Reference: VITELEC 142-0701-851.
1.5 Digital Outputs
Accesses
Access to the differential output data port is provided by a 2.54 mm pitch connector,
compatible with the High Speed Digital Acquisition System. It enables access to the
converter output data, as well as proper 50Ωdifferential termination.
1.6 Power Supplies
and Ground
Accesses
The power supplies accesses are provided by five 4 mm section banana jacks respec-
tively for VEEA, VEED, VEET, VDD, VPLUSD and VCC.
The Ground accesses are provided by 4 mm and two 2 mm banana jacks.
1.7 ADC Functions
Settings
Accesses
For ADC functions settings accesses (GORB, Die junction temp., ADC gain adjust),
smaller 2 mm section banana jacks are provided.
A potentiometer is provided for ADC gain adjust.

TSEV8388B - Evaluation Board User Guide 2-1
0973D–BDC–02/09
e2v semiconductors SAS 2009
Section 2
Layout Information
2.1 Board The TS8388B requires proper board layout for optimum full speed operation.
The following explains the board layout recommendations and demonstrates how the
Evaluation Board fulfills these implementation constraints.
A single low impedance ground plane is recommended, since it allows the user to lay
out signal traces and power planes without interrupting the ground plane.
Therefore a multi-layer board structure has been retained for the TSEV8388B.
Four copper metal layers are used, dedicated respectively (from top to bottom) to the
signal traces, ground planes and power supplies.
The input/output signal traces occupy the top metal layer.
The ground planes occupy the second and third copper metal layers.
The bottom metal layer is dedicated to the power supplies.
2.2 AC Inputs/Digital
Outputs
The board uses 50Ωimpedance microstrip lines for the differential analog inputs, clock
inputs, and differential digital outputs (including the out-of-range bit and the data ready
output signal).
The input signals and clock signals must be routed on one layer only, without using any
through-hole vias. The line lengths are matched to within 2 mm.
The digital output lines are 50Ωdifferentially terminated.
The output data traces lengths are matched to within 0.25 inch (6 mm) to minimize the
data output delay skew.
For the TSEV8388B the propagation delay is approximately 6.1 ps/mm (155 ps/inch).
The RO4003 typical dielectric constant is 3.4 at 10 GHz.
For more informations about different output termination options, refer to the specifica-
tion application notes.
2.3 DC Functions
Settings
The DC signals traces are low impedance.
They have been routed with 50Ωimpedance near the device because of room
restriction.

Layout Information
2-2 TSEV8388B - Evaluation Board User Guide
0973D–BDC–02/09
e2v semiconductors SAS 2009
2.4 Power Supplies The bottom metal layer 7 is dedicated to the power supply traces (VEEA, VEED, VEET, VCC,
VDD, VPLUSD).
The supply traces are approximately 6 mm wide in order to present low impedance, and
are surrounded by a ground plane connected to the two inner ground planes.
The Analog and Digital negative power supply traces are independent, but the possibil-
ity exists to short-circuit both supplies on the top metal layer.
No difference in ADC high speed performance is observed when connecting both nega-
tive supply planes together. Obviously one single negative supply plane could be used
for the circuit.
Each power supply incoming is bypassed by a 1 µF Tantalum capacitor in parallel with
1 nF chip capacitor.
Each power supply access is decoupled very close to the device by a 10 nF and 100 pF
surface mount chip capacitors in parallel.
Note: The decoupling capacitors are superposed. In this configuration, the 100 pF capacitors
must be mounted first.
2.5 TS8388B On-
board
Implementation
Surface-mount resistors and chip capacitors allow the closest possible connections to
the device pins, for microstrip line back termination and bypassing.
Connecting the positive supply pads:
– The positive supply pads denoted VCC:
The corresponding VCC pad numbers are 19, 21, 23, 30, 39, 40.
Each VCC power supply pad is decoupled as closely to the device as possible
by a 1 nF chip capacitor.
The VCC supply pads are connected to the back side VCC plane of the CEB.
– The positive digital supply pads are denoted VPLUSD (0V or 2.4V).
The corresponding VPLUSD pad numbers are 1, 11.
Each VPLUSD power supply pad is decoupled very close to the device by a 1 nF
chip capacitor.
The VPLUSD supply pads are connected to the back side VPLUSD plane of the
evaluation board.
Connecting the negative supply pads:
– The TS8388BGL has separate analog and digital –5V supplies:
The negative analog supply pads are denoted VEE.
The VEE corresponding pad numbers are 22, 29, 31.
The negative digital supply pad is denoted DVEE.
The DVEE corresponding pad number is pad 6.
The DVEE supply pad is dedicated to the digital output buffers only.
Each VEE and DVEE power supply pad is decoupled as closely as possible
near the device by a 1 nF chip capacitor.
–TheV
EE and DVEE supply pads are respectively connected to the backside
layer 7 VEE and VEED supply planes.
Ground pads connections:
– The analog ground pads are denoted GND.
The corresponding GND pad numbers are 20, 26, 28, 33, 35, 37.