e2v EV10AQ190-EB User manual

EV10AQ190-EB Evaluation Board
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User Guide

EV10AQ190-EB - User Guide 1-1
0964B–BDC–07/09
e2v semiconductors SAS 2009
Section 1
Introduction
1.1 Scope The EV10AQ190-EB Evaluation Kit is designed to facilitate the evaluation and charac-
terization of the EV10AQ190 Quad 10-bit 1.25 Gsps ADC in AC coupled mode.
The EV10AQ190-EB Evaluation Kit includes:
The Quad 10-bit 1.25 Gsps ADC Evaluation Board including EV10AQ190 ADC and
Atmel ATMEGA128 AVR soldered
A cable for connection to the RS-232 port
Software tools necessary to use the SPI
The user guide uses the EV10AQ190-EB Evaluation Kit as an evaluation and demon-
stration platform and provides guidelines for its proper use.
1.2 Description The EV10AQ190-EB Evaluation Board is very straightforward as it implements e2v
EV10AQ190 Quad 10-bit 1.25 Gsps ADC device, Atmel ATMEGA128 AVR, SMA con-
nectors for the sampling clock, analog inputs and reset inputs accesses and 2.54 mm
pitch connectors compatible with high-speed acquisition system probes.
Thanks to its user-friendly interface, the EV10AQ190-EB Kit enables to test all the func-
tions of the EV10AQ190 Quad 10-bit 1.25 Gsps ADC using the SPI connected to a PC.
To achieve optimal performance, the EV10AQ190-EB Evaluation Board was designed
in a 6-metal-layer board using FR4 HTG epoxy dielectric material (200 µm, ISOLA
IS410 featuring a resin content of 45%). The board implements the following devices:
The Quad 10-bit 1.25 Gsps ADC Evaluation Board with the EV10AQ190 ADC
soldered
SMA connectors for CLK, CLKN, AAI, AAIN, BAI, BAIN, CAI, CAIN, DAI, DAIN,
SYNCP, SYNCN, CAL, CALN signals
2.54 mm pitch connectors for the digital outputs, compatible with high-speed
acquisition system probes
Banana jacks for the power supply accesses, the die junction temperature monitoring
functions, reference resistor, analog input common mode voltage (2 mm)
An RS-232 connector for PC interface

Introduction
1-2 EV10AQ190-EB - User Guide
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e2v semiconductors SAS 2009
The board dimensions are 170 mm x 185 mm. The board comes fully assembled and
tested, with the EV10AQ190 installed.
Figure 1-1. EV10AQ190-EB Evaluation Board Simplified Schematic
As shown in Figure 1-1, different power supplies are required:
VCC = 3.3V analog positive power supply (includes the SPI pads)
VCCD = 1.8V digital positive power supply
VCCO = 1.8V output power supply
3.3V digital interface primary power supply for the microcontroller
C
H
P
O
R
T
D
H
P
O
R
T
D
L
P
O
R
T
C
L
P
O
R
T
A
H
P
O
R
T
B
H
P
O
R
T
B
L
P
O
R
T
A
L
P
O
R
T
RS232
AAIAAINBAI
BAIN
CAICAINDAIDAIN
GND
VCC
CMIREFAB
CMIREFCD GND
VCCO
VCCD
GND
CALN CAL
DiodA
DiodC
SYNCP SYNCN
CLKN CLK
Res50
Res62
3.3V GND
CAL
CALN
EV10AQ190

EV10AQ190-EB - User Guide 2-1
0964B–BDC–07/09
e2v semiconductors SAS 2009
Section 2
Hardware Description
2.1 Board Structure In order to achieve optimum full-speed operation of the EV10AQ190 Quad 10-bit 1.25
Gsps ADC, a multilayer board structure was retained for the evaluation board. Six cop-
per layers are used, dedicated to the signal traces, ground planes and power supply
planes.
The board is made in FR4 HTG epoxy dielectric material (ISOLA IS410). Table 2-1
gives a detailed description of the board's structure.
Table 2-1. Board Layer Thickness Profile
Layer Characteristics
Layer 1
Copper layer
Copper thickness = 40 µm (with NiAu finish)
AC signals traces = 50Ωmicrostrip lines
DC signals traces
FR4 HTG/dielectric layer Layer thickness = 200 µm
Layer 2
Copper layer
Copper thickness = 18 µm
Upper ground plane = reference plane
FR4 HTG/dielectric layer Layer thickness = 349 µm
Layer 3
Copper layer
Copper thickness = 18 µm
Power plane = VCC
FR4 HTG/dielectric layer Layer thickness = 350 µm
Layer 4
Copper layer
Copper thickness = 18 µm
Power planes = VCCD’ VCCO and 3V3
FR4 HTG/dielectric layer Layer thickness = 350 µm
Layer 5
Copper layer
Copper thickness = 18 µm
Power planes = reference plane (identical to layer 3)
FR4 HTG/dielectric layer Layer thickness = 200 µm
Layer 6
Copper layer
Copper thickness = 40 µm (with NiAu finish)
AC signals traces = 50Ωmicrostrip lines
DC signals traces

Hardware Description
2-2 EV10AQ190-EB - User Guide
0964B–BDC–07/09
e2v semiconductors SAS 2009
The board is 1.6 mm thick. The clock, analog inputs, resets, digital data output signals
and ADC functions occupy the top metal layer while the SPI signals and circuitry occupy
the bottom layer.
The ground planes occupy layer 2 and 5. Layer 3 and 4 are dedicated to the power
supplies.
2.2 Analog
Inputs/Clock
Input
The differential clock and analog inputs are provided by SMA connectors (reference:
VITELEC 142-0701-8511). Both pairs are AC coupled using 10 nF capacitors.
Special care was taken for the routing of the analog and clock input signals for optimum
performance in the high-frequency domain:
50Ωlines matched to ±0.1 mm (in length) between XAI and XAIN (X = A, B, C or D) or
CLK and CLKN
909 µm pitch between the differential traces
1270 µm between two differential pairs
361 µm line width
40 µm thickness
850 µm diameter hole in the ground layer below the XAI and XAIN or CLK and CLKN
ball footprints
Figure 2-1. Board Layout for the Differential Analog and Clock Inputs
Note: The analog inputs and clock inputs are AC coupled with 10 nF very close to the SMA
connectors.
2.3 Digital Output The digital output lines were designed with the following recommendations:
50Ωlines matched to ±2.5 mm (in length) between signal of the same differential pair
±1mm line length difference between signals of two differential pairs
635 µm pitch between the differential traces
650 µm between two differential pairs
310 µm line width
40 µm thickness
FR4 HTG
909 µm
1270 µm
e = 40 µm
361 µm 361 µm
200 µm

Hardware Description
EV10AQ190-EB - User Guide 2-3
0964B–BDC–07/09
e2v semiconductors SAS 2009
Figure 2-2. Board Layout for the Differential Digital Outputs
The digital outputs are compatible with LVDS standard. They are on-board 100Ωdiffer-
entially terminated as described in Figure 2-3.
Figure 2-3. Differential Digital Outputs Implementation
Double row 2.54 mm pitch connectors are used for the digital output data. The upper
row is connected to the signal while the lower row is connected to ground, as illustrated
in Figure 2-4.
Figure 2-4. Differential Digital Outputs 2.54 mm Pitch Connector (X = A, B, C or D)
2.4 Reset Inputs Two hardware reset signals are provided:
– SYNCP, SYNCN corresponds to the reset of the output clock of the ADC
(analog reset).
– RSTN corresponds to the reset of the SPI (makes the SPI registers go to their
default value).
The differential reset inputs SYNC, SYNCN are provided by SMA connectors (refer-
ence: VITELEC 142-0701-8511).The signals are AC coupled using 10 nF capacitors
and pulled up and down via 200Ωresistors. A variable resistor of 500Ωis implemented
on SYNC: by adjusting this resistor value one can activate and deactivate easily the
reset signal.
FR4 HTG
325 µm
635 µm
e = 40 µm
310 µm 310 µm
200 µm
650 µm
100Ω
Connector ADC
XDR XDRN XD0 XD0N XD7 XD7N XORN
N
XOR
GND GND GND GND GND GND GND GND

Hardware Description
2-4 EV10AQ190-EB - User Guide
0964B–BDC–07/09
e2v semiconductors SAS 2009
50Ωlines matched to ±0.1 mm (in length) between SYNCP and SYNCN
909 µm pitch between the differential traces
1270 µm between two differential pairs
361 µm line width
40 µm thickness
Figure 2-5. Board Layout for the SYNC Signal
Figure 2-6. SYNC, SYNCN Inputs Implementation
A push button is provided for the RSTN reset, as described in Figure 2-7.
This reset can also be generated through the AVR (via the User Interface).
FR4 HTG
909 µm
1270 µm
e = 40 µm
361 µm 361 µm
200 µm
SYNC (AC11)
SYNCN (AD11)
500
3.3V
200
SYNC
SYNCN
10 nF
10 nF
3.3V
200
Ω
GND
200
GND
Ω
Ω
Ω
EV10AQ190

Hardware Description
EV10AQ190-EB - User Guide 2-5
0964B–BDC–07/09
e2v semiconductors SAS 2009
Figure 2-7. RSTN Input Implementation
2.5 Power Supplies Layers 3 and 4 are dedicated to power supply planes (VCC, VCCD, VCCO and 3.3V).
The supply traces are low impedance and are surrounded by two ground planes (layer 2
and 5).
Each incoming power supply is bypassed at the banana jack by a 1 µF Tantalum capac-
itor in parallel with a 100 nF chip capacitor.
Each power supply is decoupled as close as possible to the EV10AQ190 device by 10
nF in parallel with 100 pF surface mount chip capacitors.
Note: The decoupling capacitors are superimposed with the 100 pF capacitor mounted first.
RSTN (AC15)
10KΩ
3.3V
0
GND
0To AVR
Ω
Ω
EV10AQ190

Hardware Description
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0964B–BDC–07/09
e2v semiconductors SAS 2009