e2v EV8AQ160 User manual

EV8AQ160TPY-DK
1
BDC- 1-Sep-10
e2v semiconductors SAS 2010
EV8AQ160
VITA 57 FMC Quad 8-bit ADC Demo Kit
Preliminary Datasheet
This document provides an overview of e2v’s VITA 57 FMC Quad 8-bit ADC Demo Kit.
Main Features
•Sampling of analog signals using EV8AQ160 Quad 8-bit ADC
•4 analog inputs with different configurations
oDifferential driver (2 types of amplifier provided)
oBalun RF transformer.
oDirect input.
•Clock Input:
oExternal clock
oor/ programmable clock generated by a PLL (2.4G to 2.7 Gsps)
•Interfacing ADC Digital outputs with an external acquisition system either with
oA logic analyzer
oAn FPGA development board using the VITA57 FMC standard
http://www.vita.com/fmc.html
•100% compatible with XILINX VIRTEX 6 evaluation kit ML605
ohttp://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm
•FFT computation (PC software provided)
•Flexible and easy to operate via USB2 control (PC software provided without any license)
•Programming of ADC settings
•Programming of ADC environment
•Monitoring of ADC currents and junction temperature
•Universal 12V power Adapter
Operating conditions
 Temperature range: 10°C < Tamb < 40°C
 Operating with a Microsoft Windows PC environment (Windows 2000, Windows XP, Windows
Vista) via USB interface.

EV8AQ160-DK
2 BDC- 1-Sep-10
e2v semiconductors SAS 2010
1 General overview
The QUAD 8bit Demo Kit enables the easy evaluation of the characteristics and performance of ADC
QUAD 8bit EV8AQ160. The Demo kit is plug_and_play and needs little external equipment.
The Demo kit is delivered with software which allows acquisition of data using the FPGA.
The QUAD 8bit Demo Kit is compatible with VITA57 FMC (FPGA Mezzanine Card) standard.
For more information please see the VITA site web.
http://www.vita.com/fmc.html
The Demo kit QUAD 8bit is 100% compatible with XILINX VIRTEX 6 evaluation kit ML605
This board is designed for use as a reference design.
All front end devices are fitted including: DC-DC regulator, ADC driver, clock generator….
Please see chap Main Functions
The FPGA VHDL data acquisition code for the ML605 board is supplied.
Please see chap FPGA CODE
1.1. Disclaimer
The information in this document is provided in connection with E2V products.
No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by
this document or in connection with the sale of E2V products.
EXCEPT AS SET FORTH IN E2V’S TERMS AND CONDITIONS OF SALE LOCATED ON E2V’S
WEB SITE, E2V ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS,
IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL E2V BE LIABLE FOR ANY DIRECT,
INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING,
WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR
LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT,
EVEN IF E2V HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
E2V makes no representations or warranties with respect to the accuracy or completeness of the
contents of this document and reserves the right to make changes to specifications and product
descriptions at any time without notice. E2V does not make any commitment to update the
information.
This kit must be regarded as a tool, not a finished product. It allows you to evaluate the performance of
the e2v component, design prototypes and debug software. It CANNOT be resold as a finished
product that must be compliant with local relevant regulations.
Its function is as a development system, demonstrating the performance of e2v semiconductors
components and not as a final product available on general release.
Since this Development Kit is intended to be used on an industrial workbench and modified by the
user to build his prototypes, NO WARRANTY OF ANY KIND can apply.
NO LIABILITY will be accepted by e2v, whatsoever may arise as a result of the use of these boards.

EV8AQ160TPY-DK
3
BDC- 1-Sep-10
e2v semiconductors SAS 2010
1.2. Quad 8-bit ADC
The EV8AQ160TPY-DK Demo Kit is based on e2v EV8AQ160 1.25 Gsps Quad 8-bit ADC whose
block diagram is given on Figure 1.
Figure 1. EV8AQ160 Quad 8-bit ADC Block diagram
The EV8AQ160 Quad ADC is built with four 8-bit ADC cores which can be used either independently
(four-channel mode) or group by two cores (two-channel mode with the ADCs interleaved two by two)
or one-channel mode where all four ADCs are all interleaved.
All four ADCs are clocked from the same external input clock signal and controlled via an SPI bus
(Serial Peripheral Interface). An analog multiplexer (cross-point switch) is used to select the analog
input depending on the mode the quad ADC is used.
The clock input is common to all four ADCs. This block receives an external 2.5GHz clock (maximum
frequency) and generates the internal sampling clocks for each ADC core depending on the mode
used. Please refer to datasheet of EV8AQ160 (doc0846) for more information.
http://www.e2v.com/products-and-services/specialist-semiconductors/broadband-data-
converters/datasheets/

EV8AQ160-DK
4 BDC- 1-Sep-10
e2v semiconductors SAS 2010
1.3. Demo Kit
Figure 2 provides an overview of system architecture.
Figure 2. EV8AQ160TPY-DK Demo Kit system architecture (when connected with a VIRTEX6
Evaluation kit)
The complete system is built with the e2v demo kit and an FPGA development kit.
e2v Demo kit contains the following items :
•Quad 8-bit Demo kit with EV8AQ160CTPY
•Cables & Power Supply
oUniversal 12V power Adapter & Cables
oUSB Cables to communicate with a PC (control of ADC settings and settings for data
acquisition)
•4 analog inputs with SMA connectors
•1 clock input with SMA connector (if external clock input is programming)
•2 SAMTEC MC-HPC-8.5L connectors HPC (High Pin Count) compatible with VITA57 standard
for ADC LVDS digital outputs
•CD ROM with GUI Software
Note: The ML605 VIRTEX 6 Evaluation kit with XC6VVLX240T-1FFG1156 FPGA is not
supplied within the e2v kit and should be purchased separately from Xilinx or its authorised
distributors.
RF generator
PC
GUI
control,
acquisition
& analysis
12V supply
adapter
FPGA
(VIRTEX 6)
VITA57 interface
e
2
v
QUAD 8-bit
4 channels
12V supply
adapter
I/O USB control
A
B
C
D
DN
CLK

EV8AQ160TPY-DK
5
BDC- 1-Sep-10
e2v semiconductors SAS 2010
Figure 3. EV8AQ160TPY-DK Demo Kit simplified schematic
Figure 4. EV8AQ160TPY-DK Demo Kit functional architecture
Acquisition and formatting of ADC digital output data are done within the FPGA Eval Kit.
Data is then transmitted again to the ADC Demo Kit.
A USB driver on the ADC Demo kit allows for transmission of the data to the computer that performs
the display and processing of ADC output data (FFT).
Software and Graphical User Interface are provided with the Demo Kit.
The provided software operates using Labview RunTime (no license required).
PCDevice
FPGA
Acquisition &
formatting
Driver USB
USB Transport Layer USB
Contro
l &
Events
Acquisition
Processing
Display
USB cable
FX2
USB Transport Layer
ADC

EV8AQ160-DK
6 BDC- 1-Sep-10
e2v semiconductors SAS 2010
2 Quick start
2.1. Operating procedure
1. Install the Software as describe in section Software Tools.
2. Install the FPGA code into ML605 Xilinx evaluation board FPGA programming
3. Turn OFF the into ML605 Xilinx evaluation board.
4. Connect the demo kit QUAD 8bit on ML605 Xilinx evaluation board.
5. Connect the power supplies of both evaluation boards.
6. Connect the USB cable.
7. Turn ON power supplies of demo kit QUAD 8bit.
8. Turn ON power supplies of ML605 Xilinx evaluation board.
9. Launch the EvalkitQuadAdc8Bits.exe software.
10. Check if current is correct (see chap: Power).
11. Turn the mode test ramp active (see chap: TEST).
12. Launch acquisition and check if sample signal is correct.
13. Return to normal mode (Turn OFF Test mode).
14. Connect a RF generator on Analog input.
15. Turn on the RF generator.
16. Launch acquisition (see chap Acquisition).
2.2. Troubleshooting
2.2.1. Installation
•Check that you own rights to write in the directory (administrator right).
•Check for the available disk space.
•Check that at USB port is free and properly configured.
oQUAD 8bit connected to USB 2 driver
Warning: this installation is done for one USB connector only, if you change the USB
connector you need to re-install this USB driver before used.
2.2.2. Start up procedure
•Check that supplies are properly powered on and properly connected.
•Check if the Xilinx FPGA evaluation board ML605 is properly configured with correct software.
•Check Demo Kit BDC QUAD 8bit is properly plugged into FPGA connector.
•Check if USB connector is properly plugged.

EV8AQ160TPY-DK
7
BDC- 1-Sep-10
e2v semiconductors SAS 2010
2.2.3. Measurement
•Check if ADC QUAD 8bit is properly configured in normal mode without standby and test
mode.
Note: check if current is correct (see chap: Power)
Note: check if test mode is OFF (see chap: TEST)
•Check if acquisition mode is correctly configured.
Warning: FFT with no windowing with no coherent signal: you could have this kind of signal
Warning: if the Fin frequency have value exact like 250 MHz the FTT result is wrong it is why it
is recommend doing measurements with shift of 2MHz like 252 MHz.

EV8AQ160-DK
8 BDC- 1-Sep-10
e2v semiconductors SAS 2010
•With channel A and channel C (with amplificatory) it is needed to add RF attenuator on SMA
connecter to have optimum performance.
•
•Check the temperature of QUAD ADC < 105°C and heatsink is properly connected

EV8AQ160TPY-DK
9
BDC- 1-Sep-10
e2v semiconductors SAS 2010
2.3. External equipment
The QUAD 8bit Demo kit needs very little external hardware.
•RF generator for Analog input signal
oThe QUAD 8bit can convert analog signals up to 620MHz
oFor optimum performance this generator must have a low phase noise
Please see example of signal generator
•Cables & Power Supply (provided by e2v)
oUniversal 12V power Adapter & Cables
oUSB Cables to communicate with a PC (control of ADC settings and settings for data
acquisition)
•PC with Windows
oWindows

2000/98/XP and Windows

NT
Please see chap 4.1 Overview
•FPGA evaluation board compatible with VITA57 FMC standard
oThis Demo Kit board has been specially designed to be plugged with the XILINX
VIRTEX 6 evaluation board EK-V6-ML605-G.
The QUAD 8bit could be used with other FPGA evaluation boards compatible with
VITA57 FMC standard. However, an assessment of available connections should be
made to ensure full compatibility.
Option
•RF generator for clock input signal for clock different to 2.5 GHz
oThe QUAD 8bit Demo kit provide clock signal at 2.5 GHz with PLL
oThe QUAD 8bit Demo kit could be tested with other clock frequency
Please see chap 6.4 Clock selection
Example of signal generator:
Agilent E4424B 250KHz 2GHz (High spectral purity)
SSB phase noise @1GHz (20 kHz offset) <-134dBc/Hz
Agilent E4426B 250KHz 4GHz (High spectral purity)
SSB phase noise @1GHz (20 kHz offset) <-134dBc/Hz
SMA100A 9 KHz 6GHz (High spectral purity)
SSB phase noise @1GHz (20 kHz offset) <-140dBc/Hz

EV8AQ160-DK
10 BDC- 1-Sep-10
e2v semiconductors SAS 2010
3 Main functions
3.1. Analog input signal
The user only needs to provide an analog signal at the input.
This signal is digitized by the ADC depending on the chosen operating mode:
•4 channel mode (1 channel per ADC core),
•2 channel mode (2 interleaved ADC cores),
•1 channel mode (4 interleaved ADC cores).
Each channel input is driven in different ways on the board:
•Single to Differential Amplifier from National Semiconductor (A channel: LMH6555),
•Single to Differential Balun RF transformer (B channel: MACOM)
•Single to Differential Amplifier from Analog Devices (C channel: ADA4939-1)
•Direct input via SMA connector (D channel) (free for customer use)
Figure 5. Analog input SMA configuration
A channel B channel C channel D channel Ext Clock