e2v TSEV81102G0FS User manual

TSEV81102G0FS Evaluation Board
..............................................................................................
User Guide

TSEV81102G0FS Evaluation Board User Guide -i
0974C–BDC–02/09
e2v semiconductors SAS 2009
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 Description ................................................................................................1-1
1.2 Features ....................................................................................................1-1
Section 2
Hardware Description ........................................................................... 2-1
2.1 Evaluation Board Block Diagram ..............................................................2-1
2.2 Board Structure.........................................................................................2-4
2.2.1 Thickness Profile of Board Layers......................................................2-4
2.2.2 Metal Layers .......................................................................................2-4
2.2.3 Dielectric Layers .................................................................................2-4
2.3 Power Supplies and Ground Access ........................................................2-5
2.4 Input Access .............................................................................................2-5
2.4.1 Input Data and Clock Access .............................................................2-5
2.4.2 Synchronous Reset Access................................................................2-5
2.4.3 Asynchronous Reset Access..............................................................2-5
2.4.4 ADC Synchronization Input Signal Access.........................................2-5
2.5 Output Access...........................................................................................2-6
2.5.1 Digital Outputs ....................................................................................2-6
2.5.2 ADC Synchronization Output Signal Access ......................................2-6
2.6 DMUX Function Settings...........................................................................2-6
2.7 Layout Information ....................................................................................2-6
2.7.1 Decoupling of Power Supplies............................................................2-6
2.7.2 Reference Planes ...............................................................................2-6
2.7.3 I/O Transmission Lines.......................................................................2-7
Section 3
Operating Characteristics ..................................................................... 3-1
3.1 Output Characteristics ..............................................................................3-1
3.2 Electrical Characteristics...........................................................................3-2

-ii TSEV81102G0FS Evaluation Board User Guide
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3.3 Operating Characteristics .........................................................................3-3
Section 4
Application Information ......................................................................... 4-1
4.1 Introduction ...............................................................................................4-1
4.2 Quick Start ................................................................................................4-1
4.2.1 Procedure ...........................................................................................4-1
4.3 Adjustments to DMUX Setting ..................................................................4-2
4.4 BIST ..........................................................................................................4-3
4.5 Delay Adjust Function ...............................................................................4-3
4.6 Die Junction Temperature Monitoring.......................................................4-4
4.7 Applying the TSEV81102G0FS DMUX to e2v ADC Evaluation Boards ...4-4
4.8 Miscellaneous ...........................................................................................4-5
Section 5
Package Description............................................................................. 5-1
5.1 Pin Description..........................................................................................5-1
5.2 Enhanced CQFP 196 Pinout.....................................................................5-3
5.3 CQFP 196 Outline Dimensions.................................................................5-4
Section 6
Ordering Information............................................................................. 6-1
6.1 Ordering Information .................................................................................6-1
Section 7
Appendices ........................................................................................... 7-1
.............................................................................................................. 7-1
7.1 Electrical Schematics................................................................................7-2

TSEV81102G0FS Evaluation Board User Guide 1-1
0974C–BDC–02/09
e2v semiconductors SAS 2009
Section 1
Introduction
1.1 Description The TSEV81102G0 DMUX Evaluation Board (EB) is designed to simplify the character-
ization and the evaluation of the TS81102G0 device (1.5 Gsps DMUX). The DMUX EB
enables testing of all the DMUX functions, which are:
Synchronous and asynchronous reset functions
Selection of the DMUX ratio (1:4 or 1:8)
Selection of the number of bits (8 or 10)
Output data common mode and swing adjustment
Die junction temperature measurements over military temperature range
The DMUX EB is designed to enable easy connection to e2v’s ADC Evaluation Boards
(for example, TSEV8388BGL and TSEV83102G0BGL) for an extended functionality
evaluation (ADC and DMUX multi-channel applications).
The DMUX EB is delivered fully assembled and tested, with a TS81102G0 device
implemented on-board and a heat sink assembled on the device.
1.2 Features 50Ωinput clock and data (differential ECL) through 2.54 mm pitch connectors
50Ωdemultiplexed output (single-ended ECL) on up to 8 x 2.54 mm pitch connectors
DMUX functions adjusted by jumpers and potentiometers
Separated ground and supply planes
Suitable for high-frequency evaluation of the TS81102G0FS device (up to 1.5 GHz)
Board dimensions are 200 mm x 190 mm
Fully assembled and tested
For optimal understanding and use of this evaluation board, please refer to the
“TS81102G0FS DMUX” summary specification.

Introduction
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TSEV81102G0FS Evaluation Board User Guide 2-1
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e2v semiconductors SAS 2009
Section 2
Hardware Description
2.1 Evaluation Board
Block Diagram
The evaluation board of the TS81102G0FS DMUX in a CQFP 196 package has been
designed with respect to the TSEV81102G0TPZR3 DMUX evaluation board (in the
TBGA 240 package).
The same board dimensions and same structure have been used.
There is, however, one main difference between the two boards, which is that the top
layer of the TSEV81102G0FS is symmetrical to the one for the TSEV81102G0TPZR3
board. The DMUX in a CQFP 196 package is, in fact, a cavity-up device, while the
DMUX in TBGA 240 is a cavity-down device. Consequently, all signals on the DMUX in
a CQFP package are mirror images of the ones on the DMUX in a TBGA 240 package.
This results in having to flip the DMUX board over to make it compatible with other e2v
ADC boards (such as the TSEV8388Bxx or TSEV83102G0BXX ADC evaluation
boards).
In addition, e2v considered placing a hole inside the board for thermal management pur-
poses (for the heat sink).
Figure 2-1 illustrates the board’s simplified cross section.
Figure 2-1. TSEV81102G0FS Board Simplified Cross-section (Board Mounting for Compatibility with TSEV8388BF/FZA2
ADC Boards)
Heatsink mounted on the bottom
side of the CQFP 196
CQFP 196 DMUX
Signal Layer

Hardware Description
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Figure 2-2. TSEV81102G0FS Board to ADC Board Connection (TSEV8388BF/FZA2) Simplified Diagram
Figure 2-3. TSEV81102G0FS Board Simplified Cross Section (Board Mounting for Compatibility with
TSEV8388GL/GLZA2 and TSEV83102G0BGL ADC Boards)
Figure 2-4. TSEV81102G0FS Board to ADC Board Connection (TSEV8388GL/GLZA2 and TSEV83102G0BGL)
Simplified Diagram
GND
GND
Ix/Ixb
GND DMUX Evaluation Board Component Side
ADC Evaluation Board Component Side
Dx/Dxb
CQFP 196 DMUX
Direct connection
CQFP 68 ADC
Heatsink mounted on the bottom
side of the CQFP 196
CQFP 196 DMUX
Signal Layer
CBGA ADC
GND
GND
Ix/Ixb
GND
Direct connection
CQFP 196 DMUX
DMUX Evaluation Board Component Side
Dx/Dxb
ADC Evaluation Board Component Side

Hardware Description
TSEV81102G0FS Evaluation Board User Guide 2-3
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Figure 2-5. TSEV81102G0FS Evaluation Board Block Diagram
DR
PORT H
PORT G
Potentiometers
Jumpers
38 mm152 mm
200 mm
GND
GND
PITCH CONNECTORS
(2.54 mm)
2DR (Diff.)
10 bits+Ref
(Single)
VCC
Power Supplies
Temperature Measruments
Power Supplies
VEE
VPLUSD
VTT
BANANA
JACKS
(2 mm)
PITCH
CONNECTOR
(2.54 mm)
IGND
VDIODE
VGND
SUBVIS
Connector
SMA
Connectors
Async Reset (Single)
Sync Reset (Diff.)
2
DMUX
DelAdj
ClkInType
RatioSel
NbBit
BIST
2
2
ADCDelAdjIn (Diff.)
ADCDelAdjOut (Diff.)
PORT E
PORT B
PORT D
PORT F
PORT A
PORT C
ADC
DelAdj
SwiAdj
SMA
Connectors
2
ClkIn (Diff.)
Data In (10 bits Diff.)
BANANA JACKS (4 mm)
BANANA JACKS (4mm)
TS81102G0FS
IDIODE

Hardware Description
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2.2 Board Structure
2.2.1 Thickness Profile of
Board Layers
The TSEV81102G0 is a seven-layered PCB constituted of four copper layers and three
dielectric layers.
The board is 1.6 mm thick. The number of layers, thickness and function of each layer,
starting with the top layer, are given in Table 2-1.
2.2.2 Metal Layers The four metal layers respectively correspond to:
The signals’ layer (layer 1)
The two reference layers (layers 3 and 7)
The supply layer (layer 5)
The upper and lower reference planes (layers 3 and 7) are partitioned into GND (the ref-
erence for the input signals) and VPLUSD (the reference for the digital output signals), in
the same way as the DMUX package.
The fifth layer is dedicated to power supplies and to ground.
2.2.3 Dielectric Layers The three dielectric layers are respectively composed of a low insertion loss dielectric
(RO4003) layer (layer 2) and BT/epoxy dielectric layers (layers 4 and 6).
Considering the severe mechanical constraints of the wide temperature range and the
high frequency domain in which the board is meant to operate, two different dielectric
materials are used:
The first is a low insertion loss RO4003 hydrocarbon/wovenglass dielectric (–0.044
dB/inch loss at 2.5 GHz), which has an enhanced dielectric consistency in the high
frequency domain, and is dedicated to the routing of 50Ωand 60Ωtraces. The
RO4003 dielectric constant is typically 3.4 at 10 GHz.
Table 2-1. Board Layer Thickness Profiles
Layer Characteristic
Layer 1
Copper layer
Copper thickness = 35 µm
Input signals: 50Ωmicrostrip lines
Output data signals: 60Ωmicrostrip lines, 50Ωterminated
Layer 2
RO4003 dielectric layer
(Hydrocarbon/wovenglass)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
–0.044 dB/inch loss at 2.5 GHz
–0.018 dB/inch loss at 18 GHz
Layer 3
Copper layer
Copper thickness = 35 µm
Upper reference plane divided into two parts: GND and VPLUSD
Layer 4
BT/epoxy dielectric layer Layer thickness = 0.4 mm
Layer 5
Copper layer
Copper thickness = 35 µm
Power plane: VEE, VCC, VTT , GND
Layer 6
BT/epoxy dielectric layer Layer thickness = 860 µm
Layer 7
Copper layer
Copper thickness = 35 µm
Lower reference plane

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TSEV81102G0FS Evaluation Board User Guide 2-5
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The second is the BT/epoxy layer, chosen for its enhanced mechanical characteristics
at elevated temperature operation. The typical dielectric constant is 4.5 at 1 MHz. The
BT/epoxy dielectric has enhanced characteristics compared to the FR4 epoxy
dielectric, namely:
– a higher operating temperature value: 170°C (125°C for FR4)
– better withstanding of thermal shocks (from –65°C up to 170°C)
The characteristics of these two dielectrics make the board particularly suitable for mea-
surements in the high frequency domain and over extended temperature ranges.
2.3 Power Supplies
and Ground
Access
The power supplies are provided by four 4 mm section red banana jacks for VEE, VCC,
VTT and VPLUSD respectively.
The ground access is provided by two 4 mm black banana jacks.
Note: Two distinct GND ground pads have been implemented on the board because of layout
considerations. For proper usage, they should be connected together to the same
ground.
2.4 Input Access
2.4.1 Input Data and Clock
Access
Access to the differential data and clock inputs (Clkln, Clklnb, I[0..9], I[0..9]b) are pro-
vided by a 2.54 mm female pitch connector via 50Ωmicrostrip lines.
The connector is made up of three rows of pitches. The lower row is connected to GND
and the upper row is used for the data and clock connections. Each differential signal is
separated by a pitch connected to GND, as shown in Figure 2-6.
Figure 2-6. Input Data Pitch Connector
Note: 100Ωdifferential impedance matching is performed on-chip.
2.4.2 Synchronous Reset
Access
Access to the signals Syncreset and Syncresetb is provided by SMA connectors via
50Ωmicrostrip lines.
Note: 100Ωdifferential impedance matching is performed on-chip.
2.4.3 Asynchronous
Reset Access
Access to the signal AsynchReset is provided by one SMA connector. A push button
also allows you to perform a quick asynchronous reset of the board.
2.4.4 ADC
Synchronization
Input Signal Access
Access to the differential signal ADCDelAdjln/ADCDelAdjlnb is provided by two SMA
connectors via 50Ωmicrostrip lines.
Note: 100Ωdifferential impedance matching is performed on-chip.
GND GND GND GND GND GND GND GND
GND In1 In1b GND In2 In2b GND In3
GND GND GND GND GND GND GND GND

Hardware Description
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2.5 Output Access
2.5.1 Digital Outputs Access to the single-ended output data and to the differential output clock (A[0..9] to
H[0..9], RefA to RefH, DR, DRb) is provided by male 2.54 mm pitch connectors, via 60Ω
microstrip lines. The microstrip lines are 50Ωterminated.
The connectors are made up of two rows of pitches. The upper row is used for the signal
connections. The lower row is connected to GND. The output ports are separated from
one another by a column (two pitches) connected to GND, as shown:
Figure 2-7. Output Data Pitch Connector
Note: The characteristic impedance of the data output microstrip lines is 60Ωso as to termi-
nate the lines by either 50Ω(ECL, PECL output format) or 75Ω(TTL output format,
available on request only).
2.5.2 ADC
Synchronization
Output Signal
Access
Access to the differential signal ADCDelAdjOut/ADCDelAdjOutb is provided by two SMA
connectors, via 50Ωmicrostrip lines.
2.6 DMUX Function
Settings
Four 2 mm section banana jacks are provided to perform die temperature measure-
ments (see Section 5.3).
Three potentiometers are provided for the adjustment of SWIADJ, ADCDelAdCtrl and
DMUXDelAdjCtrl respectively.
Four jumpers are provided for the settings of the static control signals NBBIT, RATIO-
SEL, CLKINTYPE and BIST (jumper on = logic '0', jumper off = logic '1').
2.7 Layout
Information
The DMUX processes high-frequency signals and as such particular attention was given
to the board’s layout to achieve full-speed operation efficiency. The length of the trans-
mission lines for both the input and output signals have been matched. In addition,
cross-talk effects for the output data have been reduced by increasing, wherever possi-
ble, the space between the lines.
Note: It is recommended to route the input data with differential lines whenever possible.
2.7.1 Decoupling of Power
Supplies
Each power supply is decoupled by a 1 µF tantalum capacitor in parallel to a 100 nF
chip capacitor.
Each power supply access of the DMUX is bypassed as close as possible to the device
by 10 nF and 100 pF surface mount chip capacitors side by side.
Note: These capacitors are superimposed with the capacitor of lowest value soldered first.
2.7.2 Reference Planes Each reference plane (layers 3 and 7) is physically divided into two parts: one GND
plane and one VPLUSD plane, which is the voltage reference for the output buffers of the
GND GND GND GND GND GND GND GND
X9 GND
RefY Y1 Y2 Y9 GND RefZ

Hardware Description
TSEV81102G0FS Evaluation Board User Guide 2-7
0974C–BDC–02/09
DMUX. VPLUSD can be set to all levels between GND and 3.3V, allowing the DMUX to be
set in various output modes (ECL with VPLUSD = GND, PECL with VPLUSD = 3.3V, etc.).
2.7.3 I/O Transmission
Lines
Table 2-2 summarizes the main properties of the microstrip lines of all the input and out-
put signals.
Note: The transmission delay through a transmission line is approximately 6.1 ps/inch.
Table 2-2. I/O Transmission Lines
Signal Type
Typical
length
Length
Matching
Characteristic
impedance Adaptation Comments
ClkInClkInb Differential 68.2 mm
68.2 mm -- 50ΩOn-chip 100Ω differential
I[0..9], I[0..9]b Differential 68.9 mm ±1 50ΩOn-chip 100Ω
differential
Min. length (I1B): 68.3 mm
Max length (I0B): 69.6 mm
A[0..9], …,
H[0..9]
Single-
ended 120 mm ±8 60Ω50ΩMin. length (F3 & E5):112 mm Max length (C9): 127.9 mm
DRDRb Differential 113.5 mm
113.5 mm -60Ω50Ω
SyncResetSync
Resetb Differential 85.7 mm ±1 50ΩOn-chip 100Ω differential
ADCDelAdjInAD
CDelAdjInb Differential 100 mm ±1 50ΩOn-chip 100Ω differential
ADCDelAdjOut
ADCDelAdjOutb Differential 106 mm ±1 50ΩNone

Hardware Description
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TSEV81102G0FS Evaluation Board User Guide 3-1
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e2v semiconductors SAS 2009
Section 3
Operating Characteristics
3.1 Output
Characteristics
In this section, the typical values of the board’s I/O signals and power sources are listed.
These values refer to a nominal use of the evaluation board, they are purely indicative
and may depend on temperature, frequency of use and other parameters.
The following table gives three examples for the DMUX output level settings: ECL,
PECL and TTL.
Note: One can set the DMUX to several other output formats as long as the buffer output cur-
rent remains below 36 mA and VPLUSD stays below 4V with VPLUSD - VEE < 8.3V. The
output levels are thus given by the following equations:
Note: β = 100 and Vbe = 0.9V at ambient temperature and 0.6V at high temperature.
Table 3-1. Examples of Output Buffer Format Settings
Parameter ECL PECL TTL Unit
VPLUSD 03.3 3.3 V
VTT –2 1.3 0 V
Swing ±0.5 ±0.5 ±1 V
Reference –1.58 1.72 1.28 V
VOH –1.02 2.28 2.28 V
VOL –1.99 1.31 0.28 V
Load 50 50 >75 W
Average output current 14 14 15 mA
Voh βR
βR600+
----------------------- ⎠
⎞VPLUSD Vbe–600
βR
----------Vtt⎠
⎞
Vol βR
βR600+
-----------------------
⎝⎠
⎛⎞
VPLUSD Vbe–600
480
----------Vrefsa VEE–Vbe)–(600
βR
----------Vtt⎠
⎞
Vref βR
βR600+
-----------------------
⎝⎠
⎛⎞
VPLUSD Vbe–600
960
----------Vrefsa VEE–Vbe)–(600 Vtt×
βR
------------------------⎠
⎞
+–
⎝
⎛
=
+–
⎝
⎛
=
+
⎝
⎛
⎝
⎛
=

Operating Characteristics
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3.2 Electrical
Characteristics
Table 3-2 lists the board’s absolute maximum ratings.
Note: Absolute maximum ratings are limiting values, to be applied individualy, while other parameters are within specified operating
conditions. Long exposure to maximum ratings may affect device long-term reliability.
Table 3-2. Absolute Maximum Ratings
Parameter Symbol Comments Value Unit
Positive supply voltage VCC GND to 6 V
Positive output buffer supply
voltage VPLUSD GND to 4 V
Negative supply voltage VEE GND to –4 V
Analog input voltages
ADCDelAdjCtrl
ADCDelAdjCtrlb
DMUXDelAdjCtrl
DMUXDelAdjCtrlb
SwiAdj
Voltage range for each pad
Differential voltage range –1 to 1 V
ECL 50Ωinput voltage
Clkln; ClklnbI[0…9]
I[0…9]bSyncReset
SyncResetbADCDelAdjln
ADCDelAdjlnb
Voltage range for each pad –2.2 to 0.6 V
Maximum difference
between ECL 50Ωinput
voltages
Clkln; ClklnbI
[0…9]; I[0…9]b
SyncReset, Syncresetb
ADCDelAdjln
ADCDelAdjlnb
Minimum differential swing
Maximum differential swing
0.1
2V
Data output current
A[0…9] to H[0…9]
RefA to RefH
DR, DRb
Maximum current 36 mA
TTL input voltages
Clkln Type
RatioSel
NbBit
AsyncReset
BIST
GND to VCC V
Maximum input voltage on
diode for temperature
measurement
DIODE 700 mV
Maximum input current on
diode DIODE 8mA
Maximum junction
temperature TJ135 °C
Storage temperature Tstg –65 to 150 °C

Operating Characteristics
TSEV81102G0FS Evaluation Board User Guide 3-3
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3.3 Operating
Characteristics
Please refer to the “TS81102G0FS DMUX” specification.
Table 3-3. Recommended Operating Conditions
Parameter Symbol Comments Min. Typ. Max. Unit
Positive supply voltage VCC 4.75 55.25 V
Positive output buffer supply
voltage VPLUSD
ECL output
compatibility 0 0 0 V
PECL output
compatibility 3.13 3.3 3.46 V
TTL output
compatibility 3.3 V
Negative supply voltage VEE –5.25 –5 –4.75 V
Operating junction
temperature TJ
Commercial grade “C”
Industrial grade “V”
Military grade “M”
0 < TC; TJ< 90
–40 < TC; TJ< 110
–55 < TC; TJ< 125
°C

Operating Characteristics
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TSEV81102G0FS Evaluation Board User Guide 4-1
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Section 4
Application Information
4.1 Introduction Please refer to the “TS81102G0FS” device datasheet for more information on the
DMUX functions.
4.2 Quick Start The evaluation board is delivered fully assembled and tested. A heat sink, which is man-
datory to keep the device within the recommended junction temperature conditions, is
also delivered and assembled on-board.
Caution: The board’s power supplies must not be turned on until all power connections
to the evaluation board are established.
The aim of the following procedure is to help you start the board for the first time.
It describes the step-by-step process you must follow to accomplish a BIST sequence
(Built-In Self Test, see Section 4.4) in order to verify if the board is functional.
At the end of the procedure, the DMUX will be configured with these settings:
DR mode
10-bit mode
1:8 ratio
BIST active
SWIADJ = 0V
ECL output format
4.2.1 Procedure 1. Connect the board's ground accesses together.
2. Connect VPLUSD to GND (to set the DMUX in ECL output format).
3. Connect a –5V power supply source to VEE. Then connect the supply's ground to
GND.
4. Connect a 5V power supply source to VCC. Then connect the supply's ground to
GND.
5. Connect a –2V power supply source to VTT. Then connect the supply's ground to
GND.
6. Connect a signal generator to the DMUX CLKIN and CLKINB clock input pitches.
The DMUX input clock can be either differential or single-ended.

Application Information
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7. Remove the jumpers labeled NBBIT and CLKINTYPE (in order to set the DMUX
in 10-bit DR mode.) The remaining jumpers are RATIOSEL (1:8 ratio) and BIST
(BIST active).
8. Connect a high-speed logic analyzer to the board’s output connector. We recom-
mend that at least one DMUX output port be fully probed.
9. Turn on the supply and signal sources in the following order:
–V
EE first
–V
CC
–V
PLUSD
–V
TT
– Input clock
10. Set the potentiometer labeled SWIADJ so that the SWIADJ pin of the DMUX is at
0V.
11. Apply the ASYNCRESET by pressing the corresponding button to start the
DMUX (the ASYNCRESET signal is active at high TTL level).
At the output, the demultiplexed BIST sequence should be observed (see Section 4.4).
4.3 Adjustments to
DMUX Setting
Four jumpers are provided to activate the RATIOSEL, BIST, CLKINTYPE and NBBIT
functions. When the jumper is on-board it corresponds to logic “0”. The following table
gives the DMUX settings for the RATIOSEL, NBBIT, BIST and CLKINTYPE jumper
positions.
Table 4-1. DMUX Setting Adjustments
Name Jumper Function
CLKINTYPE ON DR/2 mode
OUT DR mode
BIST ON BIST active
OUT BIST inactive
NBBIT ON 8-bit mode
OUT 10-bit mode
RATIOSEL ON 1:8 ratio
OUT 1:4 ratio