e2v TSEV81102G0FS User manual

TSEV81102G0FS Evaluation Board
..............................................................................................
User Guide

TSEV81102G0FS Evaluation Board User Guide -i
0974C–BDC–02/09
e2v semiconductors SAS 2009
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 Description ................................................................................................1-1
1.2 Features ....................................................................................................1-1
Section 2
Hardware Description ........................................................................... 2-1
2.1 Evaluation Board Block Diagram ..............................................................2-1
2.2 Board Structure.........................................................................................2-4
2.2.1 Thickness Profile of Board Layers......................................................2-4
2.2.2 Metal Layers .......................................................................................2-4
2.2.3 Dielectric Layers .................................................................................2-4
2.3 Power Supplies and Ground Access ........................................................2-5
2.4 Input Access .............................................................................................2-5
2.4.1 Input Data and Clock Access .............................................................2-5
2.4.2 Synchronous Reset Access................................................................2-5
2.4.3 Asynchronous Reset Access..............................................................2-5
2.4.4 ADC Synchronization Input Signal Access.........................................2-5
2.5 Output Access...........................................................................................2-6
2.5.1 Digital Outputs ....................................................................................2-6
2.5.2 ADC Synchronization Output Signal Access ......................................2-6
2.6 DMUX Function Settings...........................................................................2-6
2.7 Layout Information ....................................................................................2-6
2.7.1 Decoupling of Power Supplies............................................................2-6
2.7.2 Reference Planes ...............................................................................2-6
2.7.3 I/O Transmission Lines.......................................................................2-7
Section 3
Operating Characteristics ..................................................................... 3-1
3.1 Output Characteristics ..............................................................................3-1
3.2 Electrical Characteristics...........................................................................3-2

-ii TSEV81102G0FS Evaluation Board User Guide
0974C–BDC–02/09
e2v semiconductors SAS 2009
3.3 Operating Characteristics .........................................................................3-3
Section 4
Application Information ......................................................................... 4-1
4.1 Introduction ...............................................................................................4-1
4.2 Quick Start ................................................................................................4-1
4.2.1 Procedure ...........................................................................................4-1
4.3 Adjustments to DMUX Setting ..................................................................4-2
4.4 BIST ..........................................................................................................4-3
4.5 Delay Adjust Function ...............................................................................4-3
4.6 Die Junction Temperature Monitoring.......................................................4-4
4.7 Applying the TSEV81102G0FS DMUX to e2v ADC Evaluation Boards ...4-4
4.8 Miscellaneous ...........................................................................................4-5
Section 5
Package Description............................................................................. 5-1
5.1 Pin Description..........................................................................................5-1
5.2 Enhanced CQFP 196 Pinout.....................................................................5-3
5.3 CQFP 196 Outline Dimensions.................................................................5-4
Section 6
Ordering Information............................................................................. 6-1
6.1 Ordering Information .................................................................................6-1
Section 7
Appendices ........................................................................................... 7-1
.............................................................................................................. 7-1
7.1 Electrical Schematics................................................................................7-2

TSEV81102G0FS Evaluation Board User Guide 1-1
0974C–BDC–02/09
e2v semiconductors SAS 2009
Section 1
Introduction
1.1 Description The TSEV81102G0 DMUX Evaluation Board (EB) is designed to simplify the character-
ization and the evaluation of the TS81102G0 device (1.5 Gsps DMUX). The DMUX EB
enables testing of all the DMUX functions, which are:
Synchronous and asynchronous reset functions
Selection of the DMUX ratio (1:4 or 1:8)
Selection of the number of bits (8 or 10)
Output data common mode and swing adjustment
Die junction temperature measurements over military temperature range
The DMUX EB is designed to enable easy connection to e2v’s ADC Evaluation Boards
(for example, TSEV8388BGL and TSEV83102G0BGL) for an extended functionality
evaluation (ADC and DMUX multi-channel applications).
The DMUX EB is delivered fully assembled and tested, with a TS81102G0 device
implemented on-board and a heat sink assembled on the device.
1.2 Features 50Ωinput clock and data (differential ECL) through 2.54 mm pitch connectors
50Ωdemultiplexed output (single-ended ECL) on up to 8 x 2.54 mm pitch connectors
DMUX functions adjusted by jumpers and potentiometers
Separated ground and supply planes
Suitable for high-frequency evaluation of the TS81102G0FS device (up to 1.5 GHz)
Board dimensions are 200 mm x 190 mm
Fully assembled and tested
For optimal understanding and use of this evaluation board, please refer to the
“TS81102G0FS DMUX” summary specification.

Introduction
1-2 TSEV81102G0FS Evaluation Board User Guide
0974C–BDC–02/09
e2v semiconductors SAS 2009

TSEV81102G0FS Evaluation Board User Guide 2-1
0974C–BDC–02/09
e2v semiconductors SAS 2009
Section 2
Hardware Description
2.1 Evaluation Board
Block Diagram
The evaluation board of the TS81102G0FS DMUX in a CQFP 196 package has been
designed with respect to the TSEV81102G0TPZR3 DMUX evaluation board (in the
TBGA 240 package).
The same board dimensions and same structure have been used.
There is, however, one main difference between the two boards, which is that the top
layer of the TSEV81102G0FS is symmetrical to the one for the TSEV81102G0TPZR3
board. The DMUX in a CQFP 196 package is, in fact, a cavity-up device, while the
DMUX in TBGA 240 is a cavity-down device. Consequently, all signals on the DMUX in
a CQFP package are mirror images of the ones on the DMUX in a TBGA 240 package.
This results in having to flip the DMUX board over to make it compatible with other e2v
ADC boards (such as the TSEV8388Bxx or TSEV83102G0BXX ADC evaluation
boards).
In addition, e2v considered placing a hole inside the board for thermal management pur-
poses (for the heat sink).
Figure 2-1 illustrates the board’s simplified cross section.
Figure 2-1. TSEV81102G0FS Board Simplified Cross-section (Board Mounting for Compatibility with TSEV8388BF/FZA2
ADC Boards)
Heatsink mounted on the bottom
side of the CQFP 196
CQFP 196 DMUX
Signal Layer

Hardware Description
2-2 TSEV81102G0FS Evaluation Board User Guide
0974C–BDC–02/09
e2v semiconductors SAS 2009
Figure 2-2. TSEV81102G0FS Board to ADC Board Connection (TSEV8388BF/FZA2) Simplified Diagram
Figure 2-3. TSEV81102G0FS Board Simplified Cross Section (Board Mounting for Compatibility with
TSEV8388GL/GLZA2 and TSEV83102G0BGL ADC Boards)
Figure 2-4. TSEV81102G0FS Board to ADC Board Connection (TSEV8388GL/GLZA2 and TSEV83102G0BGL)
Simplified Diagram
GND
GND
Ix/Ixb
GND DMUX Evaluation Board Component Side
ADC Evaluation Board Component Side
Dx/Dxb
CQFP 196 DMUX
Direct connection
CQFP 68 ADC
Heatsink mounted on the bottom
side of the CQFP 196
CQFP 196 DMUX
Signal Layer
CBGA ADC
GND
GND
Ix/Ixb
GND
Direct connection
CQFP 196 DMUX
DMUX Evaluation Board Component Side
Dx/Dxb
ADC Evaluation Board Component Side

Hardware Description
TSEV81102G0FS Evaluation Board User Guide 2-3
0974C–BDC–02/09
Figure 2-5. TSEV81102G0FS Evaluation Board Block Diagram
DR
PORT H
PORT G
Potentiometers
Jumpers
38 mm152 mm
200 mm
GND
GND
PITCH CONNECTORS
(2.54 mm)
2DR (Diff.)
10 bits+Ref
(Single)
VCC
Power Supplies
Temperature Measruments
Power Supplies
VEE
VPLUSD
VTT
BANANA
JACKS
(2 mm)
PITCH
CONNECTOR
(2.54 mm)
IGND
VDIODE
VGND
SUBVIS
Connector
SMA
Connectors
Async Reset (Single)
Sync Reset (Diff.)
2
DMUX
DelAdj
ClkInType
RatioSel
NbBit
BIST
2
2
ADCDelAdjIn (Diff.)
ADCDelAdjOut (Diff.)
PORT E
PORT B
PORT D
PORT F
PORT A
PORT C
ADC
DelAdj
SwiAdj
SMA
Connectors
2
ClkIn (Diff.)
Data In (10 bits Diff.)
BANANA JACKS (4 mm)
BANANA JACKS (4mm)
TS81102G0FS
IDIODE

Hardware Description
2-4 TSEV81102G0FS Evaluation Board User Guide
0974C–BDC–02/09
e2v semiconductors SAS 2009
2.2 Board Structure
2.2.1 Thickness Profile of
Board Layers
The TSEV81102G0 is a seven-layered PCB constituted of four copper layers and three
dielectric layers.
The board is 1.6 mm thick. The number of layers, thickness and function of each layer,
starting with the top layer, are given in Table 2-1.
2.2.2 Metal Layers The four metal layers respectively correspond to:
The signals’ layer (layer 1)
The two reference layers (layers 3 and 7)
The supply layer (layer 5)
The upper and lower reference planes (layers 3 and 7) are partitioned into GND (the ref-
erence for the input signals) and VPLUSD (the reference for the digital output signals), in
the same way as the DMUX package.
The fifth layer is dedicated to power supplies and to ground.
2.2.3 Dielectric Layers The three dielectric layers are respectively composed of a low insertion loss dielectric
(RO4003) layer (layer 2) and BT/epoxy dielectric layers (layers 4 and 6).
Considering the severe mechanical constraints of the wide temperature range and the
high frequency domain in which the board is meant to operate, two different dielectric
materials are used:
The first is a low insertion loss RO4003 hydrocarbon/wovenglass dielectric (–0.044
dB/inch loss at 2.5 GHz), which has an enhanced dielectric consistency in the high
frequency domain, and is dedicated to the routing of 50Ωand 60Ωtraces. The
RO4003 dielectric constant is typically 3.4 at 10 GHz.
Table 2-1. Board Layer Thickness Profiles
Layer Characteristic
Layer 1
Copper layer
Copper thickness = 35 µm
Input signals: 50Ωmicrostrip lines
Output data signals: 60Ωmicrostrip lines, 50Ωterminated
Layer 2
RO4003 dielectric layer
(Hydrocarbon/wovenglass)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
–0.044 dB/inch loss at 2.5 GHz
–0.018 dB/inch loss at 18 GHz
Layer 3
Copper layer
Copper thickness = 35 µm
Upper reference plane divided into two parts: GND and VPLUSD
Layer 4
BT/epoxy dielectric layer Layer thickness = 0.4 mm
Layer 5
Copper layer
Copper thickness = 35 µm
Power plane: VEE, VCC, VTT , GND
Layer 6
BT/epoxy dielectric layer Layer thickness = 860 µm
Layer 7
Copper layer
Copper thickness = 35 µm
Lower reference plane