Endace DAG 7.1S User manual

EDM 01-17 DAG 7.1S Card User Guide
Published by:
Endace Measurement Systems®Ltd
Building 7
17 Lambie Drive
PO Box 76802
Manukau City 1702
New Zealand
Phone: [phone]
Fax: [phone]
[email protected]
EDM01.06-17
p
re1
www.endace.com
International Locations
New Zealand
Endace Technology® Ltd
Level 9
85 Alexandra Street
PO Box 19246
Hamilton 2001
New Zealand
Phone: [phone]
Fax: [phone]
Americas
Endace USA® Ltd
Suite 220
11495 Sunset Hill Road
Reston
Virginia 20190
United States of America
Phone: ++1 703 382 0155
Fax: ++1 703 382 0155
Europe, Middle East & Africa
Endace Europe® Ltd
Sheraton House
Castle Park
Cambridge CB3 0AX
United Kingdom
Phone: ++44 1223 370 176
Fax: ++44 1223 370 040
Copyright 2006 ©All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form or by any means electronic, mechanical, photocopying, recording, or otherwise, without
the prior written permission of the publisher.
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EDM 01-17 DAG 7.1S Card User Guide
Protection Against Harmful Interference
When present on equipment this manual pertains to, the statement "This device complies with part 15 of the FCC rules"
specifies the equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15
of the Federal Communications Commission [FCC] Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a
commercial environment.
This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be
required to correct the interference at his own expense.
Extra Components and Materials
The product that this manual pertains to may include extra components and materials that are not essential to its basic
operation, but are necessary to ensure compliance to the product standards required by the United States Federal
Communications Commission, and the European EMC Directive. Modification or removal of these components and/or
materials, is liable to cause non compliance to these standards, and in doing so invalidate the user’s right to operate this
equipment in a Class A industrial environment.
Disclaimer
Whilst every effort has been made to ensure accuracy, neither Endace Measurement Systems Limited nor any employee of
the company, shall be liable on any ground whatsoever to any party in respect of decisions or actions they may make as a
result of using this information.
Endace Measurement Systems Limited has taken great effort to verify the accuracy of this manual, but assumes no
responsibility for any technical inaccuracies or typographical errors.
In accordance with the Endace Measurement Systems policy of continuing development, design and specifications are
subject to change without notice.
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EDM 01-17 DAG 7.1S Card User Guide
Table of Contents
Chapter 1: Introduction 1
Overview 1
Purpose of this User Guide 1
System Requirements 2
Card Description 3
Card Architecture 4
Extended Functions 5
TCP/IP Filtering and Classification 5
AAL5/AAL3 Reassembly 5
Chapter 2: Installation 7
Introduction 7
DAG Driver Device 7
Inserting the DAG Card 7
Port Connectors 8
Pluggable Optical Transceivers 8
Chapter 3: Configuring the Card 11
Introduction 11
LEDs and Inputs 11
Concatenated Configuration 12
Configuration Options 16
Configuration in WYSYCC Style 18
Inspect Interface Statistics 21
Verify Configuration 23
Chapter 4: Capturing Data 25
Starting a Session 25
Setting Captured Packet Length 25
Enabling/ Disabling Ports 26
High Load Performance 27
Overview 27
Avoiding Packet Loss 27
Detecting Packet Losses 27
Increasing Buffer Size 28
Transmitting 28
Configuring for Transmission. 29
Explicit Packet Transmission 29
Dagflood Tool 29
Convert Trace Files 29
Chapter 5: Synchronizing Clock Time 31
Overview 31
DUCK Configuration 31
Common Synchronization 31
Timestamps 32
Configuration Tools 33
Card with Reference 34
Single Card No Reference 35
Two Cards No Reference 35
Connector Pin-outs 37
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EDM 01-17 DAG 7.1S Card User Guide
Chapter 6: Data Formats 39
Overview 39
Generic Header 39
Generic Header (cont.) 40
Type-5 Record 41
Type-7 Record 42
Type-9 Record 42
Type-12 Record 43
Chapter 7 Troubleshooting 45
Reporting Problems 45
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EDM 01-17 DAG 7.1S Card User Guide
Chapter 1:
Introduction
Overview Endace DAG 7.1S card provides the means to transfer data at the full speed
of the network into the memory of the host PC, with zero packet loss
guaranteed in even worst-case conditions. Further, unlike a NIC, Endace
products actively manage the movement of network data into memory
without consuming any of the host PC's resources. The full attention of the
CPU remains focused on the analysis of incoming data without a constant
stream of interruptions as new packets arrive from the network. For a busy
network link, this feature has a turbo-charging effect similar to that of adding
a second CPU to the system.
The DAG 7.1S is a Network Monitoring Interface card specifically designed
to provide high efficiency monitoring and transmission of ATM or POS
traffic with precision timestamping capability on 4 x STM-1 or 2 x STM-2
interfaces
Purpose of
this User
Guide
Description
The purpose of this User Guide is to provide you with an understanding of
the DAG card architecture and functionality and to guide you through the
following:
•Installing the card and associated software and firmware,
•Configuring the card for your specific network requirements,
•Running a data capture session,
•Synchronising clock time,
•Data formats
You can also find additional information relating to functions and features of
the DAG 7.1S card in the following documents which are available from the
Support section of the Endace website at www.endace.com:
•EDM04-08 Configuration and Status API Programming Guide
•EDM04-13 SAR API Programming Guide
•EDM04-11 IXP Filter API Programming Guide
•EDM04-08 DAG IXP Filter Loader Programming Guide
This User Guide and the Linux and Window Guides are also available in PDF
format on the Installation CD shipped with your DAG 7.1S card.
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EDM 01-17 DAG 7.1S Card User Guide
System
Requirements General
The minimum system requirements for the DAG 7.1S card are :
•PC, at least Intel Xeon 1.8GHz or faster
•Minimum of 256 MB RAM
•At least one free PCI-Express slot supporting at least one lane
•Software distribution requires 30MB free space
•6GB for installation of Endace software, which is optional
Operating System
This User Guide assumes you are installing the DAG card in a PC which
already has an operating system installed.
However for convenience, a copy of Debian Linux 3.1 (Sarge) is provided as
a bootable ISO image on the CDs that is shipped with the DAG card.
To install either the Linux/FreeBSD or Windows operating system please
refer to the following documents which are also included on the CD that is
shipped with the DAG card.
•EDM04-01 Linux FreeBSD Software Installation Guide
•EDM 04-02 Windows Software Installation Guide
Other Systems
For advice on using an operating system that is substantially different from
either of those specified above, please contact Endace Customer Support at
[email protected]
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EDM 01-17 DAG 7.1S Card User Guide
Card
Description The DAG 7.1S SDH/SONET Network Monitoring Card provides either four
STM-1 (OC3) or two STM-2 (OC12) interfaces supporting concatenated or
channelised ATM or Packet Over Sonet (POS) networks.
The DAG 7.1S has four optical transceivers which can be operated
simultaneously.
The key features of the card are:
•Four interfaces allow full line rate capture and processing for 4 x STM-
1/OC-3 or 2 x STM-2/OC-12.
•Fully programmable Intel IXP Network Processor
•PCI Express bus interface.
•1244Mpps raw transmit and receive bandwidth.
•Combined FPGA and network processor architecture.
•Channelised and concatenated support.
•ATM AAL2 and AAL5 segmentation and reassembly.
•PoS IP filtering
Extra Power
Connector
FPGAs
Optical
Trans
i
IXP2350
Network
RJ45
Conn
ector
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Card
Architecture Serial SONET/SDH optical data is received by four optical interfaces, and
passed through deserializers.
The network data feeds immediately into two physical layer FPGAs. The
SONET/SDH payload data is then sent to the main FPGA.
The FPGA contains the packet record processor, PCI Express interface
logic and the DAG Universal Clock Kit (DUCK) timestamp engine. The
DUCK provides high resolution per packet timestamps which can be
accurately synchronised. Time stamped packet records are then stored in
the lower FIFO.
Note: For further information on the DUCK and time synchronising
please refer to Chapter 8: Synchronising Clock Time later in this
User Guide.
An Intel IXP network processor is logically located next to the main
FPGA. The main FPGA can route packets to either the IXP network
processor for additional processing before routing onto the host or directly
to the host via the PCI-Express port.
The following diagram shows the card’s major components and the flow
of data.
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EDM 01-17 DAG 7.1S Card User Guide
Extended
Functions In addition to standard packet capture the DAG 7.1S card also provides
the following additional functionality:
TCP/IP Filtering and Classification
This feature allows you to classify packets into arbitrary categories with
then drop, retransmit or capture a packet to the host based upon the result.
You can also change filter rules “on the fly” with any loss of data
ATM Segmentation and Reassembly
This feature allows you to eliminate the significant CPU load associated
with AAL2/AAL5 and reassembly on a busy ATM link by offloading this
process to the DAG card. It also provides the ability to reduce volume of
captured data to only what is required by filtering on VPI/VCI pairs
TCP/IP Filtering and Classification
The specifications for the IP filtering/packet classification are:
•Packets are classified and filtered by IP header (both IPv4 and IPv6)
and/or UDP/TCP/SCTP port number.
•Up to 1024 IP header classification rules.
•Up 254 UDP/TCP/SCTP port or ICMP type rules can set per IP header
classification.
•Classification rules are assigned a user-defined 14-bit identifier
•Packets matching classification rules are assigned the matching rule's
identifier.
•Programmable actions may be associated with each rule identifier. For
example the packet should either be; dropped, or presented to the host.
•Packets presented to the host include the rule-match identifier in the
record header.
AAL5/AAL3 Reassembly
The ATM AAL5 Reassembler specifications are:
•Supports up to 8192 simultaneously active VCI/VPI/CIDs
•Supports simultaneous reassembly of AAL2 and AAL5 frames up to
8KB long.
•VPI/VCI/CID scanning
•Supports up to full OC-12/STM-4 cell rate on two interfaces
simultaneously [~2.8 million cells/sec], or four full OC-3/STM-1
interfaces for AAL5 reassembly.
•Supports up to 4 x OC-3/STM-1 cell rate on combined four interfaces
[~3.5 thousand cells/sec] for AAL2 reassembly.
•Optional ATM cell filtering prior to reassembly.
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EDM 01-17 DAG 7.1S Card User Guide
Chapter 2:
Installation
Introduction A DAG 7.1S card can be installed in any free PCI-Express slot.
The DAG 7.1S card operates on a single lane PCI-Express, this interface
is capable of providing a maximum throughput of 1.8GB/s for both
receive and transmit.
You can run multiple DAG 7.1S cards on one bus. By default, the DAG
driver supports up to four DAG cards in one system.
DAG Driver
Device The DAG device driver must be installed before you install the DAG card
itself.
If you have not already completed this please follow the instructions in
EDM04-01 Linux FreeBSD Software Installation Guide or EDM 04-02
Windows Software Installation Guide as appropriate, which are included on
the CD shipped with the DAG card.
Inserting the
DAG Card To insert the DAG card in the PC follow the steps described below:
•Turn power to the computer OFF,
•Remove the PCI bus slot screw and cover,
•Insert DAG card into PCI-e bus slot ensuring that it is firmly seated in
the slot,
•Check the free end of the card fits securely into the card-end bracket
that supports the weight of the card,
•Secure the card with the bus slot screw,
•Connect the extra power connector located on the top edge of the card.
Note: Ensure you do this before powering up the computer. Failure
to do so may cause damage to the card.
•
•Turn power to the computer ON.
Extra Power
Connector
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Port
Connectors The DAG 7.1S re has 4 SFP socket connectors. Each connector consists of
an optical fibre transmitter and receiver.
The upper connector of each pair is used for the transmit signal. These can
be connected to daisy-chain systems if you have facility loopback (fcl) set
on the card. You can also connect them if you are using a data generation
programme.
The bottom connector of each pair is used for the received signal.
There is an 8-pin RJ-45 socket located below the optical port connectors
on the car bracket. This is available for connection to an external time
synchronisation source.
Caution: Never connect an Ethernet network or telephone line to the
RJ-45 sockets.
Pluggable
Optical
Transceivers
Overview
The DAG7.1S card uses industry standard Small Form-factor Pluggable
(SFP] optical transceivers.
The transceivers consists of two parts:
•Mechanical chassis attached to the circuit board
•Transceiver unit which may be inserted into the chassis
Note: You must select the correct transceiver type to match the
optical parameters of the network to which you want t connect.
Configuring the card with the wrong transceiver type may damage
the card.
You can connect the transceiver to the network via LC-style optical
connectors.
For further information on Pluggable Optical Transceiver please refer to
the Endace website at www.endace.com/dagpluggable.htm.
Setting Power
The optical power range depends on the particular SFP module that is
fitted to the DAG card.
However Endace recommends the SFP modules described below which
can be supplied with the DAG 7.1S card:
Manufacturer Part number Mode
Finisar FTRJ1322 OC-12, Single Mode
Finisar FTRJ1323 OC-3, Single Mode
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Optical power is measured in dBm. This is decibels relative to 1 mW where
10 dB is equivalent to a factor of 10 in power.
The optical power is always a negative value, indicating power that is less
than 1 mW. The most sensitive devices can work at power levels down as
low as –30dBm or 1µW.
The DAG 7.1S card optical power module configuration for Multi Mode
Fibre (MMF)) and Single Mode Fibre (SMF) is shown below:
Part # Fibre Data Rate Max Pwr
[dBm] Min Pwr [dBm] Nom Pwr [dBm]
FTRJ1322 SMF 622 -8 -28 -
FTRJ1323 SMF 155 -8 -28 -
- MMF 622 - - -
- MMF 155 - - -
Power Input
The optical power input to the DAG card must be within the receiver’s
dynamic range of 0 to -22dBm. If it is slightly outside of this range it will
cause an increased bit error rate. If it is well outside of this range the
system will not be able to lock onto the SONET signal.
When power is above the upper limit the optical receiver saturates and
fails to function. When power is below the lower limit the bit error rate
increases until the device is unable to obtain lock and fails. In extreme
cases, excess power can damage the receiver.
When you set up the DAG card measure the optical power at the receiver
and ensure that it is well within the specified power range.
To adjust the input power:
•Change the splitter ratio if power is too high or too low, or
•Insert an optical attenuator if power is too high.
Splitter Losses
Splitters have the insertion losses either marked on their packaging or
described in their accompanying documentation. General guidelines are:
•A 50:50 splitter will have an insertion loss of between 3 dB and 4 dB
on each output
•90:10 splitter will have losses of about 10 dB in the high loss output,
and <2 dB in the low loss output
Note: A
single mode fibre connected to a multi-mode input has
minimal extra loss. A multi-mode fibre connected to a single mode
input creates large and unpredictable loss.
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Chapter 3:
Configuring the Card
Introduction Configuring the DAG card for data capture involves the following steps:
•Loading an image and programming the FPGA,
•Setting the link,
•Checking the link,
•Configuring the connections,
•Capturing data.
The dagchan tool which is also supplied with the DAG card allows you to
configure channel characteristics. Sample dagthree and dagchan
outputs are shown later in this chapter.
LEDs and
Inputs Before you begin to configure the DAG card it is important to understand
the function of the various LEDs associated with the card, as well as the
sockets on the PCI bracket.
RJ45 socket for time
Synchronisation Input
SFP
Optics
PHY
Main
FPGA
IXP
Network
Processor
Pwr
PHY
SODIMM
Expandable Memory
3
4
75 81
2
6
The LED functions are described below
LED Description
1 IXP Network Processor Status. When the IXP is booted this LED will
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flash at 1 sec intervals. The IXP does not automatically boot when the
card is powered ON.
2 IXP status indication - depends on the extra functionality installed
3 PCI burst manager status – should be on after the card is configured.
4 PCI FPGA status – should be on soon after the computer is started
5 IXP status indication - depends on the extra functionality installed.
6 Unused
7 PP Image loaded
8 PP Image loaded
PPS Out: Pulse Per Second Out – indicates the card is sending a clock
synchronization signal
9
10 PPS In: Pulse Per Second In – indicates the card is receiving an
external clock synchronization signal.
Concatenated
Configuration Overview
The DAG 7.1S card uses four integrated SONET/SDH ATM/PoS physical
layer interface devices to support capturing of ATM cells or HDLC
encoded Packet-over-SONET data frames.
The card supports unchannelized POS/ATM; OC-3c, OC-12c, STM-1c and
STM-4c standards for transmit and receive. Additionally channelized
ATM/HDLC receive is supported on a single port only.
Because of its flexibility, the correct link layer configuration needs to be
supplied to the card for it to function as expected.
A successful DAG card capture session is accomplished by checking the
receiver ports optical signal levels and checking the card is locked to
stream data. This is followed by configuring the DAG card for normal
use. These steps are described next.
Check Receiver Ports Optical Signal Levels
The card supports 1300 nanometreer singlemode and multimode fibre
attachments with optical signal strength between 0 dBm and -22 dBm.
If there is doubt, check card receiver ports light levels are correct using an
optical power meter.
The card receiver ports are the lower of each dual-LC-style connectors, the
closest to the PCI-Express slot.
Cover card transmit ports with LC-style plugs to prevent dust and
mechanical hazards damaging optics if not in use.
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Understand Link Layer Configuration
Become knowledgeable of the link layer configuration in use at the
network link being monitored. Important parameters include OC-3 vs. OC-
12 configuration, Channelized vs. Concatenated, ATM vs. PoS as well as
the specific scrambling options in use.
If the information cannot be obtained reliably, the card can be made to
work by varying the parameters until data is seen at the host system.
Load Latest Available PCI-Express FPGA Image
dag@endace:~$ dagrom -rvp –d dag0 -f xilinx/ dag71spci-conc-terf.bit
Load Latest Available PHY FPGA Images
dag@endace:~$ dagld –x –d dag0
xilinx/dag71pp-erf.bit:xilinx/ dag71spp-conc-terf.bit
Concatenated
Configuration
(cont.)
The table below shows the available configurations.
Note: Not all configurations are available within a single FPGA
image.
Image Number of
Ports Port Type VC Type and Number Demapper
1 4 STM-1c
4 x VC-4
4 x VC-4-4c PoS ATM
ATM
Bit-HDLC
RAW
ATM
Bit-HDLC
RAW
252 x VC-12 (E1)
336 x VC-11 (T1)
504 x VC-12 (E1)
672 x VC-11 (T1)
2
1
1
STM-1
STM-4
The DAG 7.1S card has four optical transceivers which can be operated
simultaneously.
The integrated embedded processor can be used for PoS packet filtering or
AAL2/AAL5 segmentation and reassembly.
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Display Card Configuration
Running the dagconfig tool without arguments displays the card
configuration.
dagconfig -d dag0
SFP A: laser detect nosignal nosfppwr
SFP B: laser detect nosignal nosfppwr
SFP C: laser detect nosignal nosfppwr
SFP D: laser detect nosignal nosfppwr
Port status
Port A: nolock oc12 core_on nofifo_error slave
Port B: nolock oc12 core_on nofifo_error slave
Port C: nolock oc12 core_on nofifo_error slave
Port D: nolock oc12 core_on nofifo_error slave
SONET/SDH status
SONET A: oc3 vc3 scramble tu11 async
SONET B: oc3 vc3 scramble tu11 async
SONET C: oc3 vc3 scramble tu11 async
SONET D: oc3 vc3 scramble tu11 async
E1/T1 status
E1/T1 A: no_payload notxais
E1/T1 B: no_payload notxais
E1/T1 C: no_payload notxais
E1/T1 D: no_payload notxais
Concatenated
Configuration
(cont.)
Display Card Configuration (cont.)
Phy status (AMCC1213):
eql fcl noreset
Concatenated Demapper Status:
pscramble crc32 atm noaidle
pscramble crc32 atm noaidle
pscramble crc32 atm noaidle
pscramble crc32 atm noaidle
Concatenated Mapper Status:
pscramble crc32 atm
pscramble crc32 atm
pscramble crc32 atm
pscramble crc32 atm
GPP:
varlen slen=48 align64
PCI Burst Manager
33Mhz buffer size = 32 rx_streams = 1 tx_streams = 1 mem=0:0
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