Endace DAG 3.8S User manual

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EDM01-09v7 DAG 3.8S Card User Guide
©2005 Version 9: May 2006
Published by:
Endace Measurement Systems
®
Ltd
Building 7
17 Lambie Drive
PO Box 76802
Manukau City 1702
New Zealand
Phone: [phone]
Fax: [phone]
[email protected]m
www.endace.com
International Locations
New Zealand
Endace Technology® Ltd
Level 9
85 Alexandra Street
PO Box 19246
Hamilton 2001
New Zealand
Phone: [phone]
Fax: [phone]
Americas
Endace USA® Ltd
Suite 220
11495 Sunset Hill Road
Reston
Virginia 20190
United States of America
Phone: ++1 703 382 0155
Fax: ++1 703 382 0155
Europe, Middle East & Africa
Endace Europe® Ltd
Sheraton House
Castle Park
Cambridge CB3 0AX
United Kingdom
Phone: ++44 1223 370 176
Fax: ++44 1223 370 040
Copyright 2005 ©All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means electronic, mechanical, photocopying, recording, or otherwise,
without the prior written permission of the publisher.

EDM01-09v7 DAG 3.8S Card User Guide
©2005 Version 9: May 2006
Protection Against Harmful Interference
When present on equipment this manual pertains to, the statement "This device complies with part 15 of the FCC rules"
specifies the equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15
of the Federal Communications Commission [FCC] Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a
commercial environment.
This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be
required to correct the interference at his own expense.
Extra Components and Materials
The product that this manual pertains to may include extra components and materials that are not essential to its basic
operation, but are necessary to ensure compliance to the product standards required by the United States Federal
Communications Commission, and the European EMC Directive. Modification or removal of these components and/or
materials, is liable to cause non compliance to these standards, and in doing so invalidate the user’s right to operate this
equipment in a Class A industrial environment.
Disclaimer
Whilst every effort has been made to ensure accuracy, neither Endace Measurement Systems Limited nor any employee of
the company, shall be liable on any ground whatsoever to any party in respect of decisions or actions they may make as a
result of using this information.
Endace Measurement Systems Limited has taken great effort to verify the accuracy of this manual, but assumes no
responsibility for any technical inaccuracies or typographical errors.
In accordance with the Endace Measurement Systems policy of continuing development, design and specifications are
subject to change without notice.

EDM01-09v7 DAG 3.8S Card User Guide
©2005 i Version 9: May 2006
Table of Contents
Chapter 1: Introduction 1
1.1 User Manual Purpose 1
1.2 DAG 3.8S Card Product Description 2
1.3 DAG 3.8S Card Architecture 3
1.4 DAG 3.8S Card Extended Functions 3
1.5 DAG 3.8S Card System Requirements Error! Bookmark not defined.
Chapter 2: Installation 7
2.1 Installation of Operating System and Endace Software 7
2.2 Insert DAG 3.8S Card into PC 7
2.3 DAG 3.8S Card Port Connectors 8
2.4 DAG 3.8S Card Pluggable Optical Transceivers 8
Chapter 3: Setting Optical Power 11
3.1 DAG 3.8S Card Optical Power Input 11
3.2 Splitter Losses 12
Chapter 4:Confidence Testing 13
4.1 Interpreting DAG 3.8S Card LED Status 13
4.2 DAG 3.8S Card Configuration 15
4.3 Configuration in WYSYCC Style 17
4.4 DAG 3.8S Card Configuration Options 18
4.5 Verify DAG 3.8S Card Configuration 22
4.6 General Purpose Counters 23
4.7 Inspect Links Data and Cells 23
4.8 Reporting Problems 25
Chapter 5 Running Data Capture Software 27
5.1 Starting DAG 3.8S Card Capture Session 27
5.2 High Load Performance 29
5.3 DAG 3.8S Card Packet Transmission Capabilities 30
Chapter 6: Synchronizing Clock Time 33
6.1 Configuration Tool Usage 34
6.2 Time Synchronization Configurations 35
6.2.1 Single Card no Reference Time Synchronization 35
6.2.2 Two Cards no Reference Time Synchronization 36
6.2.3 Card with Reference Time Synchronization 37
6.3 Synchronization Connector Pin-outs 39
Chapter 7: Data Formats Overview 41
7.1 Data Formats 41
7.2 Timestamps 43

EDM01-09v7 DAG 3.8S Card User Guide
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EDM01-09v7 DAG 3.8S Card User Guide
©2005 1 Version 9: May 2006
Chapter 1: Introduction
Introduction
The installation of the Endace DAG 3.8S card on a PC begins with
installing the operating system and the Endace software. This is followed
by fitting the card and connecting the ports.
Viewing this
document
This document, DAG 3.8S Card User Manual is available on the
installation CD.
In this chapter
This chapter covers the following sections of information.
•User Manual Purpose
•DAG 3.8S Card Product Description
•DAG 3.8S Card Architecture
•DAG 3.8S Card Extended Functions
•DAG 3.8S Card System Requiremen t s
1.1 User Manual Purpose
Description
The purpose of this DAG 3.8S Card User Manual is to describe:
•Installing DAG 3.8S Card
•Setting Optical Power
•Confidence Testing
•Running Data Capture Software
•Synchronizing Clock Time
•Data Formats Overview
Pre-requisite
This document presumes the DAG card is being installed in a PC already
configured with an operating system.
A copy of the Debian Linux 3.1 (Sarge) is available as a bootable ISO
image on one of the CD's shipped with the DAG card.
To install on the Linux/FreeBSD operating system, follow the instructions
in the document EDM04.05-01r1 Linux FreeBSD Installation Manual,
packaged in the CD shipped with the DAG card.
To install on a Windows operating system, follow the instructions in the
document EDM04.05-02r1 Windows Installation Manual, packaged in the
CD shipped with the DAG card

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1.2 DAG 3.8S Card Product Description
Description
The DAG 3.8S card standard configuration supports receive-only packet
and cell capture applications for OC3c or OC12c, ATM or Packet-over-
SONET (PoS) networks.
The DAG3.8S card has two transceivers which can be operated
simultaneously allowing a single card to monitor one or both directions of
a full-duplex link.
The DAG 3.8S card is also capable of transmitting packets at 100% line
rate on both ports while simultaneously receiving packets at 100% line
rate on both ports.
Figure 1-1. DAG 3.8S PCI-X Card.

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1.3 DAG 3.8S Card Architecture
Description
Serial SONET/SDH optical data is received by two optical interfaces, and
passed through demultiplexors.
The network data feeds immediately into two physical layer FPGAs. The
SONET/SDH payload data is then sent to the main FPGA.
This FPGA contains the DUCK timestamp engine, packet record
processor, and PCI-X interface logic.
Because of component close association, packets or cells are time-stamped
accurately. Time stamped packet records are stored in an external FIFO
before transmission to the host.
Figure 1-2. DAG 3.8S Card Major Components and Data Flow.
1.4 DAG 3.8S Card Extended Functions
Description
The functionality of the DAG 3.8S can can be extended in many ways.
The framers are normally set up to map STM-1, STS-3c, STM-4c and
STS-12c payloads, but other mappings are possible.
The DAG 3.8S card is equipped with a coprocessor connector which can
be used with the optional Endace DAG Coprocessor as a data processing
tool.

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Coprocessor IP
filtering/packet
classification
The specifications for the coprocessor IP filtering/packet classification
are:
•Packets are classified by TCP/IP header fields and/or payload
content.
•Up to 16,384 TCP/IP header classification rules.
•Classification rules are assigned a user-defined 16-bit identifier
•Packets matching classification rules are assigned the matching
rule's identifier.
•Programmable actions may be associated with each rule identifier.
For example, The packet should either be dropped, or presented to
the host.
•Packets presented to the host include the rule-match identifier in the
record header.
Coprocessor
ATM AAL5
Reassembly
The DAG 3.8S card is equipped with a coprocessor which can be used as
a data processing tool with the optional Endace DAG Coprocessor.
The ATM AAL5 Reassembler specifications are:
•Supports up to 65,535 simultaneously active VCI/VPI's
•Supports simultaneous reassembly of up to 65,536 AAL5 frames
•Selected VPI/VCI discovery, state management, and ageing
•Supports up to full OC-12/STM-4 cell rate on both interfaces
simultaneously [~2.8 Mcells/sec]
•Rich statistics, counters, and timeouts
Contact Endace
support
Contact the Endace customer support team at [email protected] for:
•DAG coprocessor pricing details
•Purchase of a DAG coprocessor
•Information on enabling effective use of extended functions
Description
The DAG 3.8S card and its associated data capture system has the
following minimum system requirements:
•PC, at least Intel Xeon 1.8GHz or faster
•Intel E7500, ServerWorks Grand Champion LE/HE or newer chip set
•Minimum of 256 MB RAM
•At least one free PCI-X 1.0 slot supporting 66MHz operation
•Software distribution requires 30MB free space
•6GB for installation of Endace software, which is optional

EDM01-09v7 DAG 3.8S Card User Guide
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Operating
system
For convenience, a Debian 3.1 [Sarge] Linux system is included on the
Endace Software Install CD. Endace currently supports Windows XP,
Windows Server 2000, Windows Server 2003, FreeBSD, RHEL 3.0, and
Debian Linux operating systems.
Different
system
For advice on using a system substantially different from that specified
above, contact Endace support at [email protected]

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EDM01-09v7 DAG 3.8S Card User Guide
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Chapter 2: Installation
Description
A DAG 3.8S card can be installed in any free PCI-X 1.0 slot.
The DAG 3.8S card operates only in 66MHz PCI-X mode. If placed into
a slot rated for higher speeds the bus will automatically change to 66MHz,
including any other devices sharing the bus.
The DAG 3.8S should be the only device on the PCI-X bus if possible.
The DAG 3.8S will not operate in 32 or 64-bit PCI slots.
In this chapter
This chapter covers the following sections of information.
•Installation of Operating System and Endace Software
•Insert DAG 3.8S Card into PC
•DAG 3.8S Card Port Connectors
2.1 Installation of Operating System and Endace Software
Description
If the DAG device driver is not installed, before proceeding with the next
chapter, install the software by following the instructions in EDM04-01
Endace Software Installation Manual.
Go to the next chapter of information when the DAG device driver is
installed.
2.2 Insert DAG 3.8S Card into PC
Description
Inserting the DAG 3.8S card into a PC involves accessing the bus slot,
fitting the card, and replacing bus slot screw.
Procedure
Follow these steps to insert the DAG 3.8S card.
Step 1. Access bus Slot
Power computer down.
Remove PCI-X bus slot cover.
Step 2. Fit Card
Insert into PCI-X bus slot.
Step 3. Replace bus Slot Screw
Secure card with screw.
Step 4. Power up Computer

EDM01-09v7 DAG 3.8S Card User Guide
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2.3 DAG 3.8S Card Port Connectors
Description
There are two SC-type optical port connectors. One pair for signals
transmitting, the second pair is for receiving signals.
Each port upper connector consists of an optical fibre transmitter and
receiver.
The upper connector of each pair is for transmitting signals. They are
connected only if loop-back facility is used in the DAG card to daisy-
chain the systems. They are also connected if a data generation program
is being used.
The bottom connectors of each pair is used for the received signal.
Part/function
The port functions are described in the following table.
Part Function
8-pin RJ45 socket. Used for time synchronization input.
CAUTION: This socket should never be
connected to an Ethernet network or telepphone
line.
2.4 DAG 3.8S Card Pluggable Optical Transceivers
Description
Some newer versions of the DAG 3.8S cards are available with pluggable
optics. To provide compatibility with the broadest possible range of
optical parameters, Endace offers the industry standard Small Form-factor
Pluggable [SFP] optical transceiver on the DAG 3.8S card.
The SFP transceiver consists of two parts:
•Mechanical chassis attached to the circuit board
•Transceiver unit which may be inserted into the chassis
The correct transceiver is chosen to suit the optical parameters of the
target network installed in the chassis.
The transceiver may then be connected to the network via LC-style optical
connectors.
Further information about the Pluggable Optical Transceiver is available
at the Endace http://www.endace.com/dagPluggable.htm web page.

EDM01-09v7 DAG 3.8S Card User Guide
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Figure 2-1. Pluggable Optical Transceivers.

EDM01-09v7 DAG 3.8S Card User Guide
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EDM01-09v7 DAG 3.8S Card User Guide
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Chapter 3: Setting Optical Power
Description
The optical power range depends on the particular transceiver module
fitted to the DAG 3.8S card.
The power range depends on the particular device installed on the DAG
card. The DAG 3.8S card is shipped fitted with HFBR 5208EM module
by default.
Optical power
measure
Optical power is measured in dBm – decibels relative to 1 mW where 10
dB is equivalent to a factor of 10 in power.
The numbers are all negative, showing powers below 1 mW. The most
sensitive devices can work down to about –30 dBm, or 1 µW.
Configuration
The following table describes the DAG 3.8S card optics power module
configuration. MMF = Multi Mode Fibre. SMF = Single Mode Fibre.
Part # Fibre Data Rate Max Power
[dBm]
Min Power
[dBm]
Nominal Pwr
[dBm]
HFBR 5208EM
MMF 155/622 -14 -26 -20
HFCT 5208EM
SMF 155/622 -7 -28 -20
In this chapter
This chapter covers the following sections of information.
•DAG 3.8S Card Optical Power Input
•Splitter Losses
3.1 DAG 3.8S Card Optical Power Input
Description
The optical power input into the DAG 3.8S card must be within the
receiver’s dynamic range.
When optical power is slightly out of range an increased bit error rate is
experienced. If power is well out of range the system cannot lock onto the
SONET frames. In extreme cases of being out range excess power will
damage a receiver.
When power is above the upper limit the optical receiver saturates and
fails to function. When power is below the lower limit the bit error rate
increases until the device is unable to obtain lock and fails.
Input power
The DAG 3.8S card is set up to measure the optical power at the receiver,
and to make sure that it is well within the specified power range.
Input power is adjusted by:
•Changing splitter ratio if power is too high or too low, or
•Inserting an optical attenuator if power is too high.

EDM01-09v7 DAG 3.8S Card User Guide
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3.2 Splitter Losses
Description
Splitters have the insertion losses marked on packaging or in
accompanying documentation.
•A 50:50 splitter will have an insertion loss of between 3 dB and 4
dB on each output
•90:10 splitter will have losses of about 10 dB in the high loss output,
and <2 dB in the low loss output
Single mode
fibre loss
A single mode fibre connected to a multi-mode input has minimal extra
loss.
Multi-mode
fibre loss
A multi-mode fibre connected to a single mode input creates large and
unpredictable loss.

EDM01-09v7 DAG 3.8S Card User Guide
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Chapter 4:Confidence Testing
Introduction
The confidence testing is a process to determine the DAG 3.8S card is
functioning correctly.
The process also involves a card capture session, and demonstrates
configuration in the style of 'What You See You Can Change', WYSYCC.
Interface statistics are also inspected during this process.
In this chapter
This chapter covers the following sections of information.
•Interpreting DAG 3.8S Card LED Status
•DAG 3.8S Card Configuration
•Configuration in WYSYCC Style
•DAG 3.8S Card Configuration Options
•Verify DAG 3.8S Card Configuration
•General Purpose Counters
•Inspect Links Data and Cells
•Reporting Problems
4.1 Interpreting DAG 3.8S Card LED Status
Description
The DAG 3.8S has a 8 status LEDs, one blue, three green, two orange,
and two red.
When a DAG 3.8S series card is powered up the LED 1 should always
come on indicating the FPGA is successfully programmed.
The LED 4 and LED 6 are on when the Loss of Pointer or Loss of
Framing conditions are true, or if Loss of Cell Delineation is true only in
ATM mode.

EDM01-09v7 DAG 3.8S Card User Guide
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Figure 4-1. DAG 3.8S Card Status LEDs.
LED definitions
The following table describes LED display definitions.
LED Display Function
LED 1 FPGA successfully programmed.
LED 2 Data capture in progress.
LED 3 Port A Signal Detect – valid optical signal seen by the optical
receiver.
LED 4 Port A Link Error.
LED 5 Port B Signal Detect – valid optical signal seen by the optical
receiver.
LED 6 Port B Link Error.
LED 7 PPS Out: Pulse Per Second Out – indicates the card is
sending a clock synchronization signal.
LED 8 PPS In: Pulse Per Second In – indicates the card is receiving
an external clock synchronization signal.
Figure 4-2. LED State for DAG 3.8S Card Without Optical Input.

EDM01-09v7 DAG 3.8S Card User Guide
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4.2 DAG 3.8S Card Configuration
Description
The DAG 3.8S card uses two integrated SONET/SDH ATM/PoS physical
layer interface devices to support capturing of ATM cells and HDLC
encoded Packet-over-SONET data frames.
The card supports both OC3c, OC12c, STM-1 and STM-4c standards.
Because of its flexibility, the correct link layer configuration needs to be
supplied to the card for it to function as expected.
A successful DAG 3.8S card capture session is accomplished by receiver
ports optical signal levels and checking the card is locked to stream data.
This is followed by configuring the DAG card for normal use.
Procedure
Follow these steps for a successful DAG 3.8S card capture session.
Step 1. Check Receiver Ports Optical Signal Levels
The card supports 1300 nanometer singlemode and multimode fibre
attachments with optical signal strength between 0 dBm and -22 dBm.
If there is doubt, check card receiver ports light levels are correct using an
optical power meter.
The card receiver ports are the lower of each dual-SC-style connectors, the
closest to the PCI-X slot.
Cover card transmit ports with SC-style plugs to prevent dust and
mechanical hazards damaging optics if not in use.
Step 2. Understand link layer configuration
Become knowledgeable of the link layer configuration in use at the network
link being monitored.
Important parameters include OC3c vs. OC12c configuration, ATM vs. PoS
as well as the specific scrambling options in use.
If the information cannot be obtained reliably, the card can be made to work
by varying the parameters until data is seen at the host system.