Texas Instruments TMS320*2801 Series User manual

TMS320x280x, 2801x, 2804x Boot ROM
Reference Guide
Literature Number: SPRU722CNovember 2004 – Revised October 2006

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Contents
Preface ............................................................................................................................... 7
1 Boot ROM Overview .................................................................................................. 111.1 Boot ROM Memory Map.......................................................................................... 121.2 On-Chip Boot ROM IQ Math Tables ............................................................................ 131.3 CPU Vector Table ................................................................................................. 14
2 Bootloader Features ................................................................................................. 172.1 Bootloader Functional Operation ................................................................................ 182.2 Bootloader Device Configuration ................................................................................ 192.3 PLL Multiplier Selection .......................................................................................... 192.4 Watchdog Module ................................................................................................. 192.5 Taking an ITRAP Interrupt ....................................................................................... 202.6 Internal Pullup Resisters ......................................................................................... 202.7 PIE Configuration .................................................................................................. 202.8 Reserved Memory ................................................................................................. 202.9 Bootloader Modes ................................................................................................. 212.10 Bootloader Data Stream Structure .............................................................................. 242.11 Basic Transfer Procedure ........................................................................................ 282.12 InitBoot Assembly Routine ....................................................................................... 292.13 SelectBootMode Function ........................................................................................ 302.14 CopyData Function ................................................................................................ 332.15 SCI_Boot Function ................................................................................................ 332.16 Parallel_Boot Function (GPIO) .................................................................................. 352.17 SPI_Boot Function ................................................................................................ 402.18 I
2
C Boot Function .................................................................................................. 422.19 eCAN Boot Function .............................................................................................. 452.20 ExitBoot Assembly Routine ...................................................................................... 47
3 Building the Boot Table ............................................................................................. 493.1 The C2000 Hex Utility ............................................................................................ 503.2 Example: Preparing a COFF File For eCAN Bootloading ................................................... 51
4 Bootloader Code Overview ........................................................................................ 554.1 Boot ROM Version and Checksum Information ............................................................... 564.2 Bootloader Code Revision History .............................................................................. 564.3 Bootloader Code Listing (V3.0) .................................................................................. 574.4 Bootloader Code Listing (V4.0) .................................................................................. 87
A Revision History ....................................................................................................... 93
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List of Figures
1-1 Memory Map of On-Chip ROM ........................................................................................... 121-2 Vector Table Map .......................................................................................................... 142-1 Bootloader Flow Diagram ................................................................................................. 182-2 Boot ROM Function Overview ............................................................................................ 222-3 Jump-to-Flash Flow Diagram ............................................................................................. 222-4 Flow Diagram of Jump to M0 SARAM ................................................................................... 232-5 Flow Diagram of Jump-to-OTP Memory ................................................................................ 232-6 Bootloader Basic Transfer Procedure .................................................................................. 292-7 Overview of InitBoot Assembly Function ................................................................................ 302-8 Overview of the SelectBootMode Function ............................................................................ 322-9 Overview of CopyData Function ......................................................................................... 332-10 Overview of SCI Bootloader Operation .................................................................................. 332-11 Overview of SCI_Boot Function .......................................................................................... 342-12 Overview of SCI_GetWordData Function .............................................................................. 352-13 Overview of Parallel GPIO bootloader Operation ...................................................................... 352-14 Parallel GPIO bootloader Handshake Protocol ........................................................................ 362-15 Parallel GPIO Mode Overview ............................................................................................ 362-16 Parallel GPIO Mode - Host Transfer Flow .............................................................................. 372-17 16-Bit Parallel GetWord Function ........................................................................................ 382-18 8-Bit Parallel GetWord Function .......................................................................................... 392-19 SPI Loader .................................................................................................................. 402-20 Data Transfer From EEPROM Flow ..................................................................................... 412-21 Overview of SPIA_GetWordData Function ............................................................................. 422-22 EEPROM Device at Address 0x50 ....................................................................................... 422-23 Overview of I2C_Boot Function ......................................................................................... 432-24 Random Read .............................................................................................................. 442-25 Sequential Read ............................................................................................................ 452-26 Overview of eCAN-A bootloader Operation ............................................................................. 452-27 ExitBoot Procedure Flow .................................................................................................. 47
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List of Tables
1-1 Vector Locations ............................................................................................................ 152-1 Configuration for Device Modes .......................................................................................... 192-2 Boot Mode Selection ....................................................................................................... 212-3 General Structure Of Source Program Data Stream In 16-Bit Mode ............................................... 252-4 LSB/MSB Loading Sequence in 8-Bit Data Stream ................................................................... 272-5 Boot Mode Selection ...................................................................................................... 302-6 SPI 8-Bit Data Stream .................................................................................................... 402-7 I
2
C 8-Bit Data Stream ..................................................................................................... 442-8 Bit-Rate Values for Different XCLKIN Values .......................................................................... 452-9 eCAN 8-Bit Data Stream .................................................................................................. 462-10 CPU Register Restored Values .......................................................................................... 483-1 Boot-Loader Options ....................................................................................................... 514-1 Bootloader Revision and Checksum Information ...................................................................... 564-2 Bootloader Revision Per Device.......................................................................................... 56A-1 Changes for Revision C ................................................................................................... 93
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PrefaceSPRU722C – November 2004 – Revised October 2006
Read This First
This reference guide is applicable for the code and data stored in the on-chip bootROM on the TMS320x280x, TMS320x2801x and TMS320x2804x processors. Thisincludes all flash-based, ROM-based, and RAM-based devices within these families.
The boot ROM is factory programmed with boot-loading software. Boot-mode signals(general purpose I/Os) are used to tell the bootloader software which mode to use onpower up. The boot ROM also contains standard math tables, such as SIN/COSwaveforms, for use in IQ math related algorithms found in the C28x™ IQMath Library -A Virtual Floating Point Engine (literature number SPRC087).
This guide describes the purpose and features of the bootloader. It also describes othercontents of the device on-chip boot ROM and identifies where all of the information islocated within that memory.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the followingnumber is 40 hexadecimal (decimal 64): 40h or 0x40.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the related devices and related support tools. Copies of thesedocuments are available on the Internet at www.ti.com. Tip: Enter the literature number in the search boxprovided at www.ti.com .
Data Manuals —SPRS230: — TMS320F2809, F2808, F2806, F2802, F2801, F2801x UCD9501, C2802, C2801 DSPsData Manual contains the pinout, signal descriptions, as well as electrical and timing specificationsfor the F280x devices.
SPRS357: — TMS320F28044 Digital Signal Processor Data Manual contains the pinout, signaldescriptions, as well as electrical and timing specifications for the F28044 device.
User's Guides —SPRU051: — TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes theSCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modulessupport digital communications between the CPU and other asynchronous peripherals that use thestandard non-return-to-zero (NRZ) format.
SPRU059: — TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI -a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream ofprogrammed length (one to sixteen bits) to be shifted into and out of the device at a programmedbit-transfer rate.
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Related Documentation From Texas Instruments
SPRU074: — TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guidedescribes the eCAN that uses established protocol to communicate serially with other controllers inelectrically noisy environments.
SPRU430: — TMS320C28x DSP CPU and Instruction Set Reference Guide describes the centralprocessing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-pointdigital signal processors (DSPs). It also describes emulation features available on these DSPs.
SPRU513: — TMS320C28x Assembly Language Tools User's Guide describes the assembly languagetools (assembler and other tools used to develop assembly language code), assembler directives,macros, common object file format, and symbolic debugging directives for the TMS320C28x device.
SPRU514: — TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSPassembly language source code for the TMS320C28x device.
SPRU566: — TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral referenceguides of the 28x digital signal processors (DSPs).
SPRU608: — The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instructionset of the C28x™ core.
SPRU625: — TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guidedescribes development using DSP/BIOS.
SPRU712: — TMS320x28xx, 28xxx System Control and Interrupts Reference Guide describes thevarious interrupts and system control features of the 280x digital signal processors (DSPs).
SPRU716: — TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guidedescribes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
SPRU721: — TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the featuresand operation of the inter-integrated circuit (I
2
C) module that is available on the TMS320x280xdigital signal processor (DSP).
SPRU790: — TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guidedescribes the eQEP module, which is used for interfacing with a linear or rotary incrementalencoder to get position, direction, and speed information from a rotating machine in highperformance motion and position control systems. It includes the module description and registers
SPRU791: — TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guidedescribes the main areas of the enhanced pulse width modulator that include digital motor control,switch mode power supply control, UPS (uninterruptible power supplies), and other forms of powerconversion
SPRU807: — TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes theenhanced capture module. It includes the module description and registers.
SPRU924: — TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes theoperation of the high-resolution extension to the pulse width modulator (HRPWM)
Application Reports —SPRAA58: — TMS320x281x to TMS320x280x Migration Overview describes differences between theTexas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration fromthe 281x to the 280x. While the main focus of this document is migration from 281x to 280x, usersconsidering migrating in the reverse direction (280x to 281x) will also find this document useful.
SPRA550: — 3.3 V DSP for Digital Motor Control describes a scenario of a 3.3-V-only motor controllerindicating that for most applications, no significant issue of interfacing between 3.3 V and 5 Vexists. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also discussed.Guidelines for component layout and printed circuit board (PCB) design that can reduce systemnoise and EMI effects are summarized.
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Related Documentation From Texas Instruments
SPRA820: — Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology foronline stack overflow detection on the TMS320C28x™ DSP. C-source code is provided thatcontains functions for implementing the overflow detection on both DSP/BIOS™ andnon-DSP/BIOS applications.
SPRA861: — RAMDISK: A Sample User-Defined C I/O Driver provides an easy way to use thesophisticated buffering of the high-level CIO functions on an arbitrary device. This application reportpresents a sample implementation of a user-defined device driver.
SPRA873: — Thermo-Electric Cooler Control Using a TMS320F2812 DSP & DRV592 Power Amplifierpresents a thermoelectric cooler system consisting of a Texas Instruments TMS320F2812 digitalsignal processor (DSP) and DRV592 power amplifier. The DSP implements a digitalproportional-integral-derivative feedback controller using an integrated 12-bit analog-to-digitalconverter to read the thermistor, and direct output of pulse-width-modulated waveforms to theH-bridge DRV592 power amplifier. A complete description of the experimental system, along withsoftware and software operating instructions, is provided.
SPRA876: — Programming Examples for the TMS320F281x eCAN contains several programmingexamples to illustrate how the eCAN module is set up for different modes of operation to help youcome up to speed quickly in programming the eCAN. All projects and CANalyzer configuration filesare included in the attached SPRA876.zip file.
SPRA953: — IC Package Thermal Metrics describes the traditional and new thermal metrics and will puttheir application in perspective with respect to system level junction temperature estimation.
SPRA958: — Running an Application from Internal Flash Memory on the TMS320F281x DSP (Rev. B)covers the requirements needed to properly configure application software for execution fromon-chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects arepresented. Example code projects are included.
SPRA963: — Reliability Data for TMS320LF24x and TMS320F281x Devices describes reliability data forTMS320LF24x and TMS320F281x devices.
SPRA989: — F2810, F2811, and F2812 ADC Calibration describes a method for improving the absoluteaccuracy of the 12-bit analog-to-digital converter (ADC) found on the F2810/F2811/F2812 devices.This application note is accompanied by an example program (ADCcalibration.zip) that executesfrom RAM on the F2812 eZdsp.
SPRA991: — Simulation Fulfills its Promise for Enhancing Debug and Analysis - A White Paper describessimulation enhancements that enable developers to speed up the development cycle by allowingthem to evaluate system alternatives more effectively.
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Related Documentation From Texas Instruments
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Chapter 1SPRU722C – November 2004 – Revised October 2006
Boot ROM Overview
The boot ROM is a block of read-only memory that is factory programmed.
Topic .................................................................................................. Page
1.1 Boot ROM Memory Map ............................................................. 121.2 On-Chip Boot ROM IQ Math Tables ............................................. 131.3 CPU Vector Table ...................................................................... 14
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1.1 Boot ROM Memory Map
Sin/Cos
(644 x 16)
Data space Prog space
Normalized inverse
(528 x 16)
Normalized square root
(274 x 16)
Normalized Arctan
(452 x 16)
(360 x 16)
Rounding and saturation
Bootloader functions
ROM version
ROM checksum
Reset vector
CPU vector table
(64 x 16)
On-chip boot ROM Section start
address
0x3F F000
0x3F F502
0x3F F712
0x3F F9E8
0x3F FB50
0x3F F834
0x3F FFC0
0x3F FFFF
Boot ROM Memory Map
The boot ROM is a 4K x 16 block of read-only memory located at addresses 0x3F F000 - 0x3F FFF.
The on-chip boot ROM is factory programmed with boot-load routines and math tables for use with theC28x™ IQMath Library - A Virtual Floating Point Engine (literature number SPRC087). Chapter 4 containsthe code for each of the following items:•Bootloader functions•Version number, release date and checksum•Reset vector•CPU vector table (Used for test purposes only)•IQmath Tables
Figure 1-1 shows the memory map of the on-chip boot ROM. The memory block is 4Kx16 in size and islocated at 0x3F F000 - 0x3F FFFF in both program and data space.
Figure 1-1. Memory Map of On-Chip ROM
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1.2 On-Chip Boot ROM IQ Math Tables
On-Chip Boot ROM IQ Math Tables
3K x 16 words of the boot ROM memory is reserved for IQ math tables. These math tables are providedto help improve performance and save RAM space.
The math tables included in the boot ROM are used by the Texas Instruments™ C28x™ IQMath Library -A Virtual Floating Point Engine (literature number SPRC087). The 28x IQmath Library is a collection ofhighly optimized and high precision mathematical functions for C/C++ programmers to seamlessly port afloating-point algorithm into fixed-point code on TMS320C28x devices.
These routines are typically used in computational-intensive real-time applications where optimalexecution speed and high accuracy is critical. By using these routines you can achieve execution speedsthat are considerably faster than equivalent code written in standard ANSI C language. In addition, byproviding ready-to-use high precision functions, the TI IQmath Library can shorten significantly your DSPapplication development time. The C28x™ IQMath Library - A Virtual Floating Point Engine (literaturenumber SPRC087) can be downloaded from the TI website.
The following math tables are included in the Boot ROM:•Sine/Cosine Table– Table size: 1282 words– Q format: Q30– Contents: 32-bit samples for one and a quarter period sine waveThis is useful for accurate sine wave generation and 32-bit FFTs. This can also be used for 16-bitmath, just skip over every second value.•Normalized Inverse Table– Table size: 528 words– Q format: Q29– Contents: 32-bit normalized inverse samples plus saturation limitsThis table is used as an initial estimate in the Newton-Raphson inverse algorithm. By using a moreaccurate estimate the convergence is quicker and hence cycle time is faster.•Normalized Square Root Table– Table size: 274 words– Q format: Q30– Contents: 32-bit normalized inverse square root samples plus saturationThis table is used as an initial estimate in the Newton-Raphson square-root algorithm. By using a moreaccurate estimate the convergence is quicker and hence cycle time is faster.•Normalized Arctan Table– Table size: 452 words– Q format: Q30– Contents 32-bit second order coefficients for line of best fit plus normalization tableThis table is used as an initial estimate in the Arctan iterative algorithm. By using a more accurateestimate the convergence is quicker and hence cycle time is faster.•Rounding and Saturation Table– Table size: 360 words– Q format: Q30– Contents: 32-bit rounding and saturation limits for various Q values
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1.3 CPU Vector Table
Math tables
and functions
Bootloader
functions
Reset vector
CPU vector table
64 x 16
0x3F F000
0x3F FB50
0x3F FFFF
0x3F FFC0 Reset fetched from here when
VMAP=1
Other vectors fetched from here when
VMAP=1, ENPIE=0
CPU Vector Table
A CPU vector table resides in boot ROM memory from address 0x3F FFC0 - 0x3F FFFF. This vector tableis active after reset when VMAP = 1, ENPIE = 0 (PIE vector table disabled).
Figure 1-2. Vector Table Map
A The VMAP bit is located in Status Register 1 (ST1). VMAP is always 1 on reset. It can be changed after reset bysoftware, however the normal operating mode will be to leave VMAP = 1.B The ENPIE bit is located in the PIECTRL register. The default state of this bit at reset is 0, which disables thePeripheral Interrupt Expansion block (PIE).
The only vector that will normally be handled from the internal boot ROM memory is the reset vectorlocated at 0x3F FFC0. The reset vector is factory programmed to point to the InitBoot function stored inthe boot ROM. This function starts the boot load process. A series of checking operations is performed onGeneral Purpose I/O (GPIO I/O) pins to determine which boot mode to use. This boot mode selection isdescribed in Section 2.9 of this document.
The remaining vectors in the boot ROM are not used during normal operation. After the boot process iscomplete, you should initialize the Peripheral Interrupt Expansion (PIE) vector table and enable the PIEblock. From that point on, all vectors, except reset, will be fetched from the PIE module and not the CPUvector table shown in Table 1-1 .
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CPU Vector Table
For TI silicon debug and test purposes the vectors located in the boot ROM memory point to locations inthe M0 SARAM block as described in Table 1-1 . During silicon debug, you can program the specifiedlocations in M0 with branch instructions to catch any vectors fetched from boot ROM. This is not requiredfor normal device operation.
Table 1-1. Vector Locations
Location in Contents Location in ContentsVector Boot ROM (i.e., points to) Vector Boot ROM (i.e., points to)
RESET 0x3F FFC0 InitBoot (0x3F FB50) RTOSINT 0x3F FFE0 0x00 0060INT1 0x3F FFC2 0x00 0042 Reserved 0x3F FFE2 0x00 0062INT2 0x3F FFC4 0x00 0044 NMI 0x3F FFE4 0x00 0064INT3 0x3F FFC6 0x00 0046 ILLEGAL
(1)
0x3F FFE6 0x00 0066 or ITRAPIsrINT4 0x3F FFC8 0x00 0048 USER1 0x3F FFE8 0x00 0068INT5 0x3F FFCA 0x00 004A USER2 0x3F FFEA 0x00 006AINT6 0x3F FFCC 0x00 004C USER3 0x3F FFEC 0x00 006CINT7 0x3F FFCE 0x00 004E USER4 0x3F FFEE 0x00 006EINT8 0x3F FFD0 0x00 0050 USER5 0x3F FFF0 0x00 0070INT9 0x3F FFD2 0x00 0052 USER6 0x3F FFF2 0x00 0072INT10 0x3F FFD4 0x00 0054 USER7 0x3F FFF4 0x00 0074INT11 0x3F FFD6 0x00 0056 USER8 0x3F FFF6 0x00 0076INT12 0x3F FFD8 0x00 0058 USER9 0x3F FFF8 0x00 0078INT13 0x3F FFDA 0x00 005A USER10 0x3F FFFA 0x00 007AINT14 0x3F FFDC 0x00 005C USER11 0x3F FFFC 0x00 007CDLOGINT 0x3F FFDE 0x00 005E USER12 0x3F FFFE 0x00 007E
(1)
As of version 4 of the boot ROM code, this vector points to a ITRAP interrupt service routine, ITRAPIsr(), within the boot ROM.This ISR attempts to enable the watchdog and loops until the watchdog resets the part. On previous revisions, this vector pointsto location 0x66 in M0 SARAM. Refer to Section 4.1 to determine the version of the boot ROM code on a particular device.
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CPU Vector Table
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Chapter 2SPRU722C – November 2004 – Revised October 2006
Bootloader Features
This section describes in detail the boot mode selection process, as well as thespecifics of the bootloader operation.
Topic .................................................................................................. Page
2.1 Bootloader Functional Operation ................................................ 182.2 Bootloader Device Configuration ................................................ 192.3 PLL Multiplier Selection ............................................................. 192.4 Watchdog Module ..................................................................... 192.5 Taking an ITRAP Interrupt .......................................................... 202.6 Internal Pullup Resisters ............................................................ 202.7 PIE Configuration ...................................................................... 202.8 Reserved Memory ..................................................................... 202.9 Bootloader Modes ..................................................................... 212.10 Bootloader Data Stream Structure ............................................... 242.11 Basic Transfer Procedure .......................................................... 282.12 InitBoot Assembly Routine ......................................................... 292.13 SelectBootMode Function .......................................................... 302.14 CopyData Function.................................................................... 332.15 SCI_Boot Function .................................................................... 332.16 Parallel_Boot Function (GPIO) .................................................... 352.17 SPI_Boot Function .................................................................... 402.18 I
2
C Boot Function ...................................................................... 422.19 eCAN Boot Function .................................................................. 452.20 ExitBoot Assembly Routine ........................................................ 47
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2.1 Bootloader Functional Operation
Boot ROM
Reset vector fetched from boot ROM
address 0x3F FFC0
Jump to InitBoot function to start
boot process
Boot determined by the state of I/O pins
SelectBootMode function
Begin execution at Entry Point as
determined by selected boot mode
PIE disabled (ENPIE−0)
VMAP=1
OBJMODE=0
AMODE=0
MOM1MAP=1
Reset
(power-on reset or warm reset)
Silicon sets the following:
Bootloader Functional Operation
The bootloader is the program located in the on-chip boot ROM that is executed following a reset.
The bootloader is used to transfer code from an external source into internal memory following power up.This allows code to reside in slow non-volatile memory externally, and be transferred to high-speedmemory to be executed.
The bootloader provides a variety of different ways to download code to accommodate different systemrequirements. The bootloader uses various GPIO signals to determine which boot mode to use. The bootmode selection process as well as the specifics of each bootloader are described in the remainder of thisdocument. Figure 2-1 shows the basic bootloader flow.
Figure 2-1. Bootloader Flow Diagram
The reset vector in boot ROM redirects program execution to the InitBoot function. After performing deviceinitialization the bootloader will check the state of GPIO pins to determine which boot mode you want toexecute. Options include: jump to flash, jump to SARAM, jump to OTP, or call one of the on-chip bootloading routines.
After the selection process and if the required boot loading is complete, the processor will continueexecution at an entry point determined by the boot mode selected. If a bootloader was called, then theinput stream loaded by the peripheral determines this entry address. This data stream is described inSection 2.10 . If, instead, you choose to boot directly to flash, OTP, or SARAM, the entry address ispredefined for each of these memory blocks.
The following sections discuss in detail the different boot modes available and the process used forloading data code into the device.
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2.2 Bootloader Device Configuration
2.3 PLL Multiplier Selection
2.4 Watchdog Module
Bootloader Device Configuration
At reset, any 28x™ CPU-based device is in 27x™ object-compatible mode. It is up to the application toplace the device in the proper operating mode before execution proceeds.
On the 28x devices, when booting from the internal boot ROM, the device is configured for 28x operatingmode by the boot ROM software. You are responsible for any additional configuration required.
For example, if your application includes C2xLP™ source, then you are responsible for configuring thedevice for C2xLP source compatibility prior to execution of code generated from C2xLP source.
The configuration required for each operating mode is summarized in Table 2-1 .
Table 2-1. Configuration for Device Modes
C2xLP SourceC27x Mode (Reset) 28x Mode Compatible Mode
OBJMODE 0 1 1AMODE 0 0 1PAGE0 0 0 0M0M1MAP
(1)
1 1 1Other Settings SXM = 1, C = 1, SPM = 0
(1)
Normally for C27x compatibility, the M0M1MAP would be 0. On these devices, however, it is tied offhigh internally; therefore, at reset, M0M1MAP is always configured for 28x mode.
The boot ROM does not change the state of the PLL. Note that the PLL multiplier is not affected by areset from the debugger. Therefore, a boot that is initialized from a reset from Code Composer Studio™may be at a different speed than booting by pulling the external reset line ( XRS) low.
When branching directly to flash, M0 single-access RAM (SARAM), or one-time-programmable (OTP)memory, the watchdog is not touched. In the other boot modes, the watchdog is disabled before bootingand then re-enabled and cleared before branching to the final destination address.
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2.5 Taking an ITRAP Interrupt
2.6 Internal Pullup Resisters
2.7 PIE Configuration
2.8 Reserved Memory
Taking an ITRAP Interrupt
If an illegal opcode is fetched, the 28x will take an ITRAP (illegal trap) interrupt. During the boot process,the interrupt vector used by the ITRAP is within the CPU vector table of the boot ROM. As of version 4 ofthe boot ROM code, the ITRAP vector points to an interrupt service routine (ISR) within the boot ROMnamed ITRAPIsr(). This interrupt service routine attempts to enable the watchdog and then loops foreveruntil the processor is reset. This ISR will be used for any ITRAP until the user's application initializes andenables the peripheral interrupt expansion (PIE) block. Once the PIE is enabled, the ITRAP vector locatedwithin the PIE vector table will be used. Prior to boot ROM code version 4, the ITRAP interrupt vector inthe CPU vector table pointed to a RAM location in M0 memory. Refer to Section 4.1 to determine the bootROM code version of a particular device.
Each GPIO pin has an internal pullup resistor that can be enabled or disabled in software. The pins thatare read by the boot mode selection code to determine the boot mode selection have pull-ups enabledafter reset by default. In noisy conditions it is still recommended that you configure each of the three bootmode selection pins externally.
The individual bootloaders SCI, SPI, eCAN, and parallel boot all enable the pullup resistors for the pinsthat are used for control and data transfer. The bootloader leaves the resistors enabled for these pinswhen it exits. For example, the SCI-A bootloader enables the pullup resistors on the SCITXA and SCIRXApins. It is your responsibility to disable them, if desired, after the bootloader exits.
The boot modes do not enable the PIE. It is left in its default state, which is disabled.
The first 80 words of the M1 memory block (address 0x400 - 0x44F) are reserved for the stack and .ebsscode sections during the boot-load process. If code is bootloaded into this region there is no errorchecking to prevent it from corrupting the boot ROM stack.
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