Epson S1C63616 User manual

S1C63616
Technical Manual
Rev.1.0

NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission
of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does
not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application
or use in any product or circuit and, further, there is no representation that this material is applicable to products
requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is
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this material will be free from any patent or copyright infringement of a third party. This material or portions thereof
may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and
Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or
other approval from another government agency.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
© SEIKO EPSON CORPORATION 2011, All rights reserved.

Devices
S1 C 17xxx F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 17000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Corresponding model number
17xxx: for S1C17xxx
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number

SIC63616-(Rev. 1.0) NO. 4
3240-0412
Contents
Chapter 1 outline___________________________________________________ 1
1.1 Features ......................................................................................................... 1
1.2 Block Diagram............................................................................................... 2
1.3 Pin Layout Diagram ...................................................................................... 3
1.4 Pin Description.............................................................................................. 5
1.5 Mask Option .................................................................................................. 6
Chapter 2 power supply and initial reset _______________________________ 9
2.1 Power Supply ................................................................................................. 9
2.1.1 Operating voltage.......................................................................................... 9
2.1.2 Internal power supply circuit ........................................................................ 9
2.2 Initial Reset.................................................................................................. 11
2.2.1 Reset terminal (RESET)............................................................................... 11
2.2.2 Simultaneous high input to P1x ports (P10-P13)........................................ 12
2.2.3 Internal register at initial resetting ............................................................. 12
2.2.4 Terminal settings at initial resetting............................................................ 13
2.3 Test Terminal (TEST) ................................................................................... 13
Chapter 3 Cpu, roM, raM _________________________________________ 14
3.1 CPU ............................................................................................................. 14
3.2 Code ROM ................................................................................................... 14
3.3 RAM............................................................................................................. 14
3.4 Data ROM.................................................................................................... 15
Chapter 4 peripheral CirCuits and operation _______________________________16
4.1 Memory Map ............................................................................................... 16
4.2 Power Control.............................................................................................. 32
4.2.1 Configuration of power supply circuit......................................................... 32
4.2.2 Controlling the power supply voltage booster/halver and voltage regulators33
4.2.3 Heavy load protection function ................................................................... 34
4.2.4 I/O memory for power control..................................................................... 34
4.2.5 Programming notes ..................................................................................... 36
4.3 Watchdog Timer ........................................................................................... 37
4.3.1 Configuration of watchdog timer................................................................. 37
4.3.2 Interrupt function ........................................................................................ 37
4.3.3 I/O memory of watchdog timer.................................................................... 38
4.3.4 Programming notes ..................................................................................... 38
4.4 Oscillation Circuit ....................................................................................... 39
4.4.1 Configuration of oscillation circuit ............................................................. 39
4.4.2 Mask option ................................................................................................. 39
4.4.3 OSC1 oscillation circuit .............................................................................. 40
4.4.4 OSC3 oscillation circuit .............................................................................. 40
4.4.5 Switching the CPU clock............................................................................. 41
4.4.6 I/O memory of oscillation circuit ................................................................ 42
4.4.7 Programming notes ..................................................................................... 43

SIC63616-(Rev. 1.0) NO. 5
3240-0412
4.5 I/O Ports (P00-P03, P10-P13, P20-P23 and P40-P43) ............... 44
4.5.1 Configuration of I/O ports........................................................................... 44
4.5.2 Mask option ................................................................................................. 45
4.5.3 I/O control registers and input/output mode ............................................... 46
4.5.4 Input interface level..................................................................................... 46
4.5.5 Pull-down during input mode...................................................................... 46
4.5.6 Special output.............................................................................................. 47
4.5.7 Key input interrupt function ........................................................................ 49
4.5.8 I/O memory of I/O ports .............................................................................. 51
4.5.9 Programming notes ..................................................................................... 61
4.6 LCD Driver.................................................................................................. 62
4.6.1 Configuration of LCD driver....................................................................... 62
4.6.2 Power supply for LCD driving .................................................................... 63
4.6.3 Controlling LCD display ............................................................................. 65
4.6.4 Display memory........................................................................................... 69
4.6.5 LCD contrast adjustment............................................................................. 72
4.6.6 I/O memory of LCD driver .......................................................................... 73
4.6.7 Programming notes ..................................................................................... 78
4.7 Clock Timer ................................................................................................. 79
4.7.1 Configuration of clock timer........................................................................ 79
4.7.2 Controlling clock manager.......................................................................... 79
4.7.3 Data reading and hold function .................................................................. 79
4.7.4 Interrupt function ........................................................................................ 80
4.7.5 I/O memory of clock timer........................................................................... 81
4.7.6 Programming notes ..................................................................................... 83
4.8 Stopwatch Timer .......................................................................................... 84
4.8.1 Configuration of stopwatch timer................................................................ 84
4.8.2 Controlling clock manager.......................................................................... 84
4.8.3 Counter and prescaler................................................................................. 85
4.8.4 Capture buffer and hold function ................................................................ 85
4.8.5 Stopwatch timer RUN/STOP and reset........................................................ 86
4.8.6 Direct input function and key mask ............................................................. 87
4.8.7 Interrupt function ........................................................................................ 90
4.8.8 I/O memory of stopwatch timer................................................................... 92
4.8.9 Programming notes ..................................................................................... 96
4.9 Programmable Timer................................................................................... 97
4.9.1 Configuration of programmable timer......................................................... 97
4.9.2 Controlling clock manager....................................................................... 100
4.9.3 Basic count operation................................................................................ 101
4.9.4 Event counter mode (Timers 0, 2, 4 and 6) ............................................... 102
4.9.5 PWM mode (Timers 0-7) ........................................................................... 103
4.9.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3, Timer 4 + 5, Timer 6 + 7). 104
4.9.7 Interrupt function ...................................................................................... 105
4.9.8 Control of TOUT output ............................................................................ 105
4.9.9 Clock output to serial interface and R/f converter .................................... 106
4.9.10 I/O memory of programmable timer........................................................ 107
4.9.11 Programming notes ................................................................................. 119
4.10 Serial Interface .......................................................................................... 121
4.10.1 Configuration of serial interface ............................................................. 121
4.10.2 Serial interface terminals ........................................................................ 121
4.10.3 Mask option ............................................................................................. 122
4.10.4 Operating mode of serial interface ......................................................... 123
4.10.5 Setting synchronous clock........................................................................ 124
4.10.6 Data input/output and interrupt function ................................................ 125
4.10.7 Data transfer in SPI mode....................................................................... 128
4.10.8 I/O memory of serial interface ................................................................ 129

SIC63616-(Rev. 1.0) NO. 6
3240-0412
4.10.9 Programming notes ................................................................................. 134
4.11 Sound Generator........................................................................................ 135
4.11.1 Configuration of sound generator ........................................................... 135
4.11.2 Controlling clock manager...................................................................... 135
4.11.3 Control of buzzer output.......................................................................... 135
4.11.4 Setting of buzzer frequency and sound level............................................ 136
4.11.5 Digital envelope ...................................................................................... 137
4.11.6 One-shot output ....................................................................................... 138
4.11.7 I/O memory of sound generator .............................................................. 139
4.11.8 Programming notes ................................................................................. 142
4.12 Integer Multiplier....................................................................................... 143
4.12.1 Configuration of integer multiplier.......................................................... 143
4.12.2 Controlling clock manager...................................................................... 143
4.12.3 Multiplication mode ................................................................................ 143
4.12.4 Division mode.......................................................................................... 144
4.12.5 Execution cycle........................................................................................ 145
4.12.6 I/O memory of integer multiplier............................................................. 146
4.12.7 Programming note................................................................................... 148
4.13 R/f Converter ............................................................................................. 149
4.13.1 Configuration of R/f converter................................................................. 149
4.13.2 Controlling clock manager...................................................................... 150
4.13.3 Connection terminals and CR oscillation circuit .................................... 150
4.13.4 Operation of R/f conversion .................................................................... 152
4.13.5 Interrupt function .................................................................................... 154
4.13.6 Continuous oscillation function............................................................... 156
4.13.7 I/O memory of R/f converter.................................................................... 156
4.13.8 Programming notes ................................................................................. 160
4.14 SVD (Supply Voltage Detection) Circuit.................................................... 161
4.14.1 Configuration of SVD circuit................................................................... 161
4.14.2 SVD operation ......................................................................................... 161
4.14.3 I/O memory of SVD circuit...................................................................... 162
4.14.4 Programming notes ................................................................................. 162
4.15 Interrupt and HALT/SLEEP ...................................................................... 163
4.15.1 Interrupt factor........................................................................................ 165
4.15.2 Interrupt mask ......................................................................................... 166
4.15.3 Interrupt vector........................................................................................ 167
4.15.4 I/O memory of interrupt .......................................................................... 169
4.15.5 Programming notes ................................................................................. 172
Chapter 5 suMMary of notes ________________________________________ 173
5.1 Notes for Low Current Consumption......................................................... 173
5.2 Summary of Notes by Function.................................................................. 174
5.3 Precautions on Mounting .......................................................................... 179
Chapter 6 BasiC external wiring diagraM _____________________________ 181
Chapter 7 eleCtriCal CharaCteristiCs_________________________________ 182
7.1 Absolute Maximum Rating ........................................................................ 182
7.2 Recommended Operating Conditions........................................................ 182
7.3 DC Characteristics.................................................................................... 183
7.4 Analog Circuit Characteristics and Current Consumption....................... 184
7.5 Oscillation Characteristics........................................................................ 187
7.6 Serial Interface AC Characteristics........................................................... 188

SIC63616-(Rev. 1.0) NO. 7
3240-0412
7.7 Timing Chart.............................................................................................. 189
7.8 Characteristics Curves (reference value).................................................. 190
Chapter 8 paCkage ________________________________________________ 201
8.1 Plastic Package.......................................................................................... 201
8.2 Ceramic Package for Test Samples............................................................ 202
Chapter 9 pad layout ______________________________________________ 203
9.1 Diagram of Pad Layout ............................................................................. 203
9.2 Pad Coordinates ........................................................................................ 204
appendix a peripheral CirCuit Boards for s1C6f632________________________205
A.1 Names and Functions of Each Part ........................................................... 205
A.1.1 S5U1C63000P6......................................................................................... 205
A.1.2 S5U1C6F632P2 ........................................................................................ 208
A.2 Connecting to the Target System................................................................ 210
A.3 Downloading to S5U1C63000P6 .............................................................. 214
A.3.1 Downloading Circuit Data 1 -
when new ICE (S5U1C63000H2/S5U1C63000H6) is used ............ 214
A.3.2 Downloading Circuit Data 2 -
when previous ICE (S5U1C63000H1) is used................................. 215
A.4 Usage Precautions..................................................................................... 216
A.4.1 Operational precautions ........................................................................... 216
A.4.2 Differences with the actual IC................................................................... 216
A.5 Product Specifications ............................................................................... 219
A.5.1 Specifications of S5U1C63000P6 ............................................................. 219
A.5.2 Specifications of S5U1C6F632P2............................................................. 220
revision history _________________________________________221

SIC63616-(Rev. 1.0) NO. P1
3240-0412
chapter 1 Outline
The S1C63616 is a microcomputer which has a 4-bit CPU S1C63000 as the core CPU, ROM (16,384 words ×
13 bits), RAM (2,048 words ×4 bits), multiply-divide circuit, serial interface, watchdog timer, programmable
timer, time base counters (2 systems), a dot matrix LCD driver that can drive a maximum 1,280 dots of LCD
panel, and an R/f converter that can measure temperature and humidity using sensors such as a thermistor.
The S1C63616 features low current consumption, this makes it suitable for battery driven clocks and
watches with temperature and humidity measurement functions.
1.1 Features
OSC1 oscillation circuit ...........................32.768 kHz (Typ.) crystal oscillation circuit
OSC3 oscillation circuit ...........................
4.2 MHz (Max.) ceramic or 1.8 MHz (Typ.) CR oscillation circuit (∗1)
Instruction set............................................Basic instruction: 47 types (411 instructions with all)
Addressing mode: 8 types
Instruction execution time .......................During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec
During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec
ROM capacity............................................Code ROM: 16,384 words ×13 bits
Data ROM: 2,048 words ×4 bits
RAM capacity............................................Data memory: 2,048 words ×4 bits
Display memory: 2,048 bits
I/O port .......................................................16 bits (pull-down resistors may be incorporated∗1
Shared with 4 serial I/F I/O pins, 4 R/f converter I/O pins,
and 3 special output pins ∗2)
Serial interface..........................................1 port (8-bit clock synchronous system)
LCD driver .................................................40 segments ×32 commons, 48 segments ×24 commons, or
56 segments ×16 commons (∗2)
Time base counter ...................................Clock timer
Stopwatch timer (1/1000 sec, with direct key input function)
Programmable timer ................................16-bit timer ×4 ch. (each 16-bit timer is configurable to two 8-bit
timer channels ∗2)
Watchdog timer.........................................Built-in
Sound generator.......................................With envelope and 1-shot output functions
R/f converter ........................................2 ch., CR oscillation type, 20-bit counter
Supports resistive humidity sensors
Multiply-divide circuit ...........................8-bit accumulator ×1 ch.
Multiplication: 8 bits ×8 bits →16-bit product
Division: 16 bits ÷8 bits →8-bit quotient and 8-bit remainder
Supply voltage detection (SVD) circuit Programmable 16 detection voltage levels (∗2)
External interrupt......................................Key input interrupt: 8 systems
Internal interrupt .......................................Clock timer interrupt: 8 systems
Stopwatch timer interrupt: 4 systems
Programmable timer interrupt: 16 systems
Serial interface interrupt: 1 system
R/f converter interrupt: 3 systems
Power supply voltage...............................1.6 to 5.5 V
Operating temperature range .................-40 to 85°C
Current consumption (Typ.) ....................During SLEEP (32 kHz) 0.08 µA
During HALT (32 kHz) 0.6 µA
During running (32 kHz) 2.5 µA
During running (4 MHz) 320 µA
Shipment form...........................................TQFP15-128pin or die form
∗1: Can be selected with mask option ∗2: Can be selected with software

SIC63616-(Rev. 1.0) NO. P2
3240-0412
1.2 Block Diagram
OSC1
OSC2
OSC3
OSC4
TEST
COM0–15
(SEG55–40)COM16–31
SEG0–39
V DD
V C1–5
V D1–2
V OSC
CA–CG
V
SS
RESET
P00–03, P10–13
P20–23
P40–43
SEN0(P02), REF0(P01), RFOUT(P03)
RFIN0(P00)
SEN1, HUD, REF1
RFIN1
BZ(P03)
TOUT_A(P13)
SIN(P22)
SOUT(P21)
SRDY/SS(P23)
SCLK(P20)
Core CPU S1C63000
Code ROM
16,384 words ×13 bits
System Reset
Control
Interrupt
Generator
OSC
RAM
2,048 words ×4 bits
Data ROM
2,048 words ×4 bits
LCD Controller
& Driver
Power
Controller
SVD
Watchdog
Timer
Clock
Timer
Stopwatch
Timer
Programmable
Timer
Sound
Generator
Integer Multiplier
Test
R/f Converter
I/O Port
Serial
Interface
Fig. 1.2.1 Block diagram

SIC63616-(Rev. 1.0) NO. P3
3240-0412
1.3 Pin Layout Diagram
TQFP15-128pin (Plastic Package)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
SEG17
N.C. N.C.
SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
SEG40/COM31 SEG41/COM30 SEG42/COM29 SEG43/COM28
N.C. N.C. N.C.
COM0 N.C. N.C. HUD SEN1 REF1 RFIN1 V
SS
P00/RFIN0 P01/REF0 P02/SEN0 V
DD
P03/RFOUT/BZ P10/RUN/LAP P11/RUN/LAP P12/EVIN_A P13/TOUT_A P20/SCLK P21/SOUT P22/SIN P23/SRDY/SS/FOUT P40 P41/EVIN_B P42/EVIN_C P43/EVIN_D RESET TEST V
OSC
V
D1
N.C. N.C. N.C.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
OSC2
OSC1
V
SS
OSC4
OSC3
V
DD
V C1
V C2
V C3
V C4
V
C5
CA
CB
CC
CD
CE
CF
CG
V
D2
V SS
COM16/SEG55
COM17/SEG54
COM18/SEG53
COM19/SEG52
COM20/SEG51
COM21/SEG50
COM22/SEG49
COM23/SEG48
COM24/SEG47
COM25/SEG46
COM26/SEG45
COM27/SEG44
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
Fig. 1.3.1 Pin layout diagram (TQFP15-128pin)

SIC63616-(Rev. 1.0) NO. P4
3240-0412
QFP17-144pin (Ceramic Package for Test Samples)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
N.C.
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
SEG40/COM31 SEG41/COM30 SEG42/COM29 SEG43/COM28
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
N.C. HUD SEN1 REF1 N.C. RFIN1 N.C. N.C. VSS
P00/RFIN0 P01/REF0 P02/SEN0 VDD P03/RFOUT/BZ P10/RUN/LAP P11/RUN/LAP P12/EVIN_A P13/TOUT_A P20/SCLK P21/SOUT P22/SIN P23/SRDY/SS/FOUT P40 P41/EVIN_B P42/EVIN_C P43/EVIN_D RESET TEST N.C. N.C. N.C. N.C. N.C. VOSC N.C. VD1
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
OSC2
OSC1
VSS
OSC4
OSC3
VDD
VC1
VC2
VC3
VC4
VC5
CA
CB
CC
CD
CE
CF
CG
VD2
VSS
COM16/SEG55
COM17/SEG54
COM18/SEG53
COM19/SEG52
COM20/SEG51
COM21/SEG50
COM22/SEG49
COM23/SEG48
COM24/SEG47
COM25/SEG46
COM26/SEG45
COM27/SEG44
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
Fig. 1.3.2 Pin layout diagram (QFP17-144pin)

SIC63616-(Rev. 1.0) NO. P5
3240-0412
1.4 Pin Description
Table 1.4.1 Pin description
Pin name
VDD
VSS
VD1
VOSC
VD2
VC1–VC5
CA–CE
CF, CG
OSC1
OSC2
OSC3
OSC4
P00/RFIN0
P01/REF0
P02/SEN0
P03/RFOUT/BZ
P10/RUN/LAP
P11/RUN/LAP
P12/EVIN_A
P13/TOUT_A
P20/SCLK
P21/SOUT
P22/SIN
P23/SRDY/SS
/FOUT
P40
P41/EVIN_B
P42/EVIN_C
P43/EVIN_D
COM0–COM15
COM16–COM31
/SEG55–SEG40
SEG0–SEG39
RFIN1
REF1
SEN1
HUD
RESET
TEST
Function
Power (+) supply pins
Power (–) supply pins
Internal logic voltage regulator output pin
Crystal oscillation circuit operating voltage output pin
Power supply voltage booster/halver output pin
LCD drive voltage output pins
LCD system voltage boost capacitor connecting pins
Power supply voltage boost/halving capacitor connecting pins
Crystal oscillation input pin
Crystal oscillation output pin
Ceramic or CR oscillation input pin (mask option)
Ceramic or CR oscillation output pin (mask option)
I/O port or R/f converter Ch.0 CR oscillation input pin (software switch)
I/O port or R/f converter Ch.0 reference oscillation output pin (software switch)
I/O port or R/f converter Ch.0 CR oscillation output pin (software switch)
I/O port, R/f converter oscillation frequency output pin, or sound output pin
(software switch)
I/O port or stopwatch Run/Lap input pin (software switch)
I/O port or stopwatch Run/Lap input pin (software switch)
I/O port or event counter input pin (software switch)
I/O port or programmable timer output pin (software switch)
I/O port or serial I/F clock I/O pin (software switch)
I/O port or serial I/F data output pin (software switch)
I/O port or serial I/F data input pin (software switch)
I/O port, serial I/F ready signal output, SS signal input or FOUT clock output pin
(software switch)
I/O port pin
I/O port or event counter input pin (software switch)
I/O port or event counter input pin (software switch)
I/O port or event counter input pin (software switch)
LCD common output pins
LCD common output or segment output pins (software switch)
LCD segment output pins
R/f converter Ch.1 CR oscillation input pin
R/f converter Ch.1 reference oscillation output pin
R/f converter Ch.1 CR oscillation output pin
R/f converter AC-bias oscillation output pin for humidity sensor
Initial reset input pin
Test input pin
Die
53, 76
39, 56, 80
59
60
40
52–48
47–43
42, 41
57
58
54
55
79
78
77
75
74
73
72
71
70
69
68
67
66
65
64
63
85–100
38–23
101–118, 1–22
81
82
83
84
62
61
Pin No. I/O
–
–
–
–
–
–
–
–
I
O
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
O
O
O
I
I
TQFP15-128
59, 85
45, 62, 89
68
68
46
58–54
53–49
48, 47
63
64
60
61
88
87
86
84
83
82
81
80
79
78
77
76
75
74
73
72
96–111
44–33, 29–26
112–128, 4–25,
90
91
92
93
71
70
QFP17-144
67, 96
53, 70, 100
73
75
54
66–62
61–57
56, 55
71
72
68
69
99
98
97
95
94
93
92
91
90
89
88
87
86
85
84
83
112–127
52–41, 28–25
128–144, 2–24,
103
105
106
107
82
81

SIC63616-(Rev. 1.0) NO. P6
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1.5 Mask Option
Mask options shown below are provided for the S1C63616. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog, that has been prepared as the development software tool of S1C63616, is used for this
selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the
"S5U1C63000A Manual" for the winfog.
<Outline of the mask option>
(1) OSC1 oscillation circuit
The OSC1 oscillator type is fixed at crystal oscillation. Refer to Section 4.4.3, "OSC1 oscillation circuit",
for details.
(2) OSC3 oscillation circuit
The OSC3 oscillator type can be selected from ceramic oscillation or CR oscillation (external R). Refer to
Section 4.4.4, "OSC3 oscillation circuit", for details.
(3) RESET terminal pull-down resistor
This option is used to select whether an internal pull-down resistor is incorporated into the RESET input
port. Refer to Section 2.2.1, "Reset terminal (RESET)", for details.
(4) I/O port pull-down resistor
This option is used to select whether an internal pull-down resistor that will be enabled in input mode
is incorporated into each I/O port (P00–P03, P10–P13, P20–P23, P40–P43). Refer to Section 4.5.2, "Mask
option", for details.
(5) Output specification of the I/O port
This option is used to select either complementary output or P-channel open drain output as the output
cell type of each I/O port (P00–P03, P10–P13, P20–P23, P40–P43). Refer to Section 4.5.2, "Mask option",
for details.
(6) Multiple key entry reset function (by simultaneous high input to the P1x ports)
This option is used to select whether the function to reset the IC by pressing multiple keys simultane-
ously is implemented or not. A combination of the P1x ports (P10–P13) to be used for this function can
also be selected. Refer to Section 2.2.2, "Simultaneous high input to P1x ports (P10–P13)", for details.
(7) Time authorize circuit for the multiple key entry reset function
When the multiple key entry reset option (option (6)) is selected, the time authorize circuit can also be
incorporated. The time authorize circuit measures the high pulse width of the simultaneous input sig-
nals and asserts the reset signal if it is longer than the predetermined time. This option is not available
when the multiple key entry reset option is not selected. Refer to Section 2.2.2, "Simultaneous high input
to P1x ports (P10–P13)", for details.
(8) LCD drive power supply
This option is used to select the LCD drive bias from 1/5 bias (with VC2 reference voltage), 1/4 bias (with
VC2 reference voltage) and 1/4 bias (with VC1 reference voltage). Refer to Section 4.6.2, "Power supply
for LCD driving", for details.

SIC63616-(Rev. 1.0) NO. P7
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<Option List>
The following is the option list for the S1C63616.
Multiple selections are available in each option item as indicated in the option list. Select the specifications
that meet the target system and check the appropriate box. Be sure to record the specifications for unused
functions too, according to the instructions provided.
1. OSC1 SYSTEM CLOCK
1. Crystal
2. OSC3 SYSTEM CLOCK
1. CR (external R)
2. Ceramic (4.2 MHz)
3. RESET PORT PULL DOWN RESISTOR
 •RESET 1. Use 2. Not Use
4. I/O PORT PULL DOWN RESISTOR
 •P00 1. Use 2. Not Use
 •P01 1. Use 2. Not Use
 •P02 1. Use 2. Not Use
 •P03 1. Use 2. Not Use
 •P10 1. Use 2. Not Use
 •P11 1. Use 2. Not Use
 •P12 1. Use 2. Not Use
 •P13 1. Use 2. Not Use
 •P20 1. Use 2. Not Use
 •P21 1. Use 2. Not Use
 •P22 1. Use 2. Not Use
 •P23 1. Use 2. Not Use
 •P40 1. Use 2. Not Use
 •P41 1. Use 2. Not Use
 •P42 1. Use 2. Not Use
 •P43 1. Use 2. Not Use
5. I/O PORT OUTPUT SPECIFICATION
 •P00 1. Complementary 2. Pch Open Drain
 •P01 1. Complementary 2. Pch Open Drain
 •P02 1. Complementary 2. Pch Open Drain
 •P03 1. Complementary 2. Pch Open Drain
 •P10 1. Complementary 2. Pch Open Drain
 •P11 1. Complementary 2. Pch Open Drain
 •P12 1. Complementary 2. Pch Open Drain
 •P13 1. Complementary 2. Pch Open Drain
 •P20 1. Complementary 2. Pch Open Drain
 •P21 1. Complementary 2. Pch Open Drain
 •P22 1. Complementary 2. Pch Open Drain
 •P23 1. Complementary 2. Pch Open Drain
 •P40 1. Complementary 2. Pch Open Drain
 •P41 1. Complementary 2. Pch Open Drain
 •P42 1. Complementary 2. Pch Open Drain
 •P43 1. Complementary 2. Pch Open Drain

SIC63616-(Rev. 1.0) NO. P8
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6. MULTIPLE KEY ENTRY RESET COMBINATION
1. Not Use
2. Use <P10, P11>
3. Use <P10, P11, P12>
4. Use <P10, P11, P12, P13>
7. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE
1. Not Use
2. Use
8. LCD DRIVING POWER
1. 1/5 Bias, VC2 Reference
2. 1/4 Bias, VC2 Reference
3. 1/4 Bias, VC1 Reference

SIC63616-(Rev. 1.0) NO. P9
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chapter 2 pOwer Supply and initial reSet
2.1 Power Supply
This section explains the operating voltage and the configuration of the internal power supply circuit of the
S1C63616.
2.1.1 Operating voltage
The S1C63616 operating power voltage is as follows:
1.6 V to 5.5 V
2.1.2 Internal power supply circuit
The S1C63616 incorporates the power supply circuit shown in Figure 2.1.2.1. When voltage within the range
described above is supplied to VDD (+) and VSS (GND), all the voltages needed for the internal circuits are
generated internally in the IC.
VC1–VC5
OSC3
OSC4
OSC1
OSC2
COM0–COM31
SEG0–SEG39
∗1 Leave these terminals open when the power supply voltage booster/halver is not used.
∗2 Connect when the 1/5 bias LCD drive power is used. (Leave the terminal open when the 1/4 bias LCD drive power is used.)
∗3 Can be selected as the power source for the LCD system voltage regulator when the power supply voltage booster/halver
operates in boost mode.
∗4 HLON is prohibited from use.
∗1
∗2
Power supply voltage
booster/halver
Oscillation system
voltage regulator
Internal voltage
regulator
OSC3
oscillation circuit
Internal circuits
OSC1
oscillation circuit
DBON
VCSEL
HLON
External
power
supply
VDD
CF
CG
VD2
VD1
VOSC
VC1
VC2
VC3
VC4
VC5
CA
CB
CC
CD
CE
VSS
VDD
VD1
VD2
VOSC
LCD
driver
circuit
LCD system
voltage
regulator
∗3
∗4
VDD
Fig. 2.1.2.1 Configuration of power supply circuit
The power supply circuit is broadly divided into four blocks.
Table 2.1.2.1 Power supply circuit
Circuit
Internal and oscillation system voltage regulators
Internal circuits and OSC3 oscillation circuit
OSC1 oscillation circuit
LCD system voltage regulator
LCD driver
Power supply circuit
Power supply voltage (VDD)
Internal voltage regulator
Oscillation system voltage regulator
Power supply voltage booster/halver (halving mode)
LCD system voltage regulator
Output voltage
—
VD1
VOSC
VDD or VD2
VC1—VC5
Note: The supply voltage booster/halver circuit can perform either boosting or halving the supply voltage at
a time. The boosting and halving operations cannot be performed simultaneously.

SIC63616-(Rev. 1.0) NO. P10
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Power supply voltage booster/halver circuit
The S1C63616 supports a wide supply voltage (VDD) range that exceeds the operating voltage range of
the voltage regulator (LCD system voltage regulator). The power supply voltage booster/halver circuit
generates the VD2 voltage to drive the voltage regulators when the supply voltage VDD is out of the
operating voltage range of the voltage regulators.
Table 2.1.2.2 Relationship between supply voltage VDD and voltage regulator operating voltage
Power supply
voltage VDD
1.6 to 2.5 V
2.5 to 5.5 V
Power source for
LCD system voltage regulator
VD2 (≈ VDD × 2)
VDD
When a VC2 reference voltage option for the LCD drive power supply is selected, the LCD system volt-
age regulator must be driven with a 2.5 V or more operating voltage. Therefore, the LCD system voltage
regulator can be driven with VDD if 2.5 V or more supply voltage VDD is used. When the supply voltage
VDD is less than 2.5 V, drive the power supply voltage booster/halver in boost mode to generate VD2
and use it to drive the LCD system voltage regulator. The VD2 voltage generated in boost mode is about
double the VDD voltage level.
The VD2 voltage is not required when the power supply voltage (VDD) is within the range from 2.5 V to
5.5 V (1.6 V to 5.5 V when the VC1 reference LCD drive power option is selected). In this case the power
supply voltage booster/halver can be turned off.
The S1C63616 allows software to control the power supply voltage booster/halver and to select the
power source of the voltage regulator. Refer to Section 4.2, "Power Control", for details.
Internal voltage regulator
The internal voltage regulator generates the operating voltage VD1 for driving the internal logic circuits
and the OSC3 oscillation circuit.
Oscillation system voltage regulator
The oscillation system voltage regulator generates the VOSC voltage for driving the OSC1 oscillation
circuit and is provided separately with the internal voltage regulator to stabilize the oscillation and to
reduce power consumption.
LCD system voltage regulator
The LCD system voltage regulator generates the LCD drive voltages VC1 to VC5. See Chapter 7, "Electri-
cal Characteristics" for the voltage values.
In the S1C63616, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD
panel connected to the SEG and COM terminals.
Notes:• BesurenottousetheVD1,VD2,VOSC andVC1toVC5 terminal output voltages to drive external
circuits.
 • IfVDDequaltoorlessthan2.5VisusedasthepowersourcefortheLCDsystemvoltage
regulator,theVC1toVC5voltagescannotbegeneratedwithinspecications(whenaVC2 reference
voltage option is selected).
 • HLONisprohibitedfromuse.Alwaysbesuretosetto"0".

SIC63616-(Rev. 1.0) NO. P11
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2.2 Initial Reset
The S1C63616 should be reset to initialize the internal circuits. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous high input to P10–P13 ports (mask option)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
RESET
P10
P11
P12
P13
OSC2
OSC1
R Q
S
Internal
initial
reset
Divider
1 kHz
1 Hz
16 Hz
OSC1
oscillation
circuit
Noise
reject
circuit
Time
authorize
circuit
Mask option
Mask option
VSS
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a high level (VDD). After that the
initial reset is released by setting the reset terminal to a low level (VSS) and the CPU starts operating.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 16 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 16,396/fOSC1 seconds (500 msec when fOSC1 = 32.768 kHz) is needed until
the internal initial reset is released after the reset terminal goes to low level. Be sure to maintain a reset
input of 0.1 msec or more. However, when turning the power on, the reset terminal should be set at a high
level as in the timing shown in Figure 2.2.1.1.
Note that a reset pulse shorter than 100 nsec is rejected as noise.
VDD
RESET
2.0 msec or more
1.3 V
0.5•VDD
0.9•VDD or more (high level)
Power on
Fig. 2.2.1.1 Initial reset at power on
Theresetterminalshouldbesetto0.9•VDD or more (high level) until the supply voltage becomes 1.3 V or
more.
Afterthat,alevelof0.5•VDD or more should be maintained more than 2.0 msec.
The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the
resistor is used or not.

SIC63616-(Rev. 1.0) NO. P12
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2.2.2 Simultaneous high input to P1x ports (P10-P13)
Another way of executing initial reset externally is to input high level signals simultaneously to the P1x
ports (P10–P13) selected by a mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals
at high level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal
operation. The noise reject circuit does not operate immediately after turning the power on until the oscilla-tion. The noise reject circuit does not operate immediately after turning the power on until the oscilla-
tion circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for at least 1.5
msec (when the oscillation frequency fOSC1 is 32.768 kHz) after oscillation starts.
Table 2.2.2.1 shows the combinations of P1x ports (P10–P13) that can be selected by a mask option.
Table 2.2.2.1 Combinations of P1x ports
Not use
P10∗P11
P10∗P11∗P12
P10∗P11∗P12∗P13
1
2
3
4
When, for instance, mask option 4 (P10∗P11∗P12∗P13) is selected, initial reset is executed when the signals
input to the four ports P10–P13 are all high at the same time. When 2 or 3 is selected, the initial reset is done
when a key entry including a combination of selected input ports is made.
Further, the time authorize circuit mask option is selected when this reset function is selected. The time
authorize circuit checks the input time of the simultaneous high input and performs initial reset if that time
is the defined time (1 to 2 sec) or more.
If using this function, make sure that the specified ports do not go high at the same time during ordinary
operation.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.3.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if neces-
sary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including NMI
are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
Table 2.2.3.1 Initial values
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
CPU core
Symbol
A
B
EXT
X
Y
PC
SP1
SP2
Z
C
I
E
Q
Number of bits
4
4
8
16
16
16
8
8
1
1
1
1
16
Setting value
Undefined
Undefined
Undefined
Undefined
Undefined
0110H
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral circuits
Number of bits
4
4
–
Setting value
Undefined
Undefined
∗
∗See Section 4.1, "Memory Map".

SIC63616-(Rev. 1.0) NO. P13
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2.2.4 Terminal settings at initial resetting
The I/O port (P) terminals are shared with special output terminals and input/output terminals of the
serial interface, R/f converter, stopwatch timer and programmable timer (event counter). These functions
are selected by the software. At initial reset, these terminals are configured to the general purpose I/O port
terminals. Set them according to the system in the initial routine.
Table 2.2.4.1 shows the list of the shared terminal settings.
Table 2.2.4.1 List of shared terminal settings
Terminal
name
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P40
P41
P42
P43
Terminal status
at initial reset
P00 (Input & pulled down∗)
P01 (Input & pulled down∗)
P02 (Input & pulled down∗)
P03 (Input & pulled down∗)
P10 (Input & pulled down∗)
P11 (Input & pulled down∗)
P12 (Input & pulled down∗)
P13 (Input & pulled down∗)
P20 (Input & pulled down∗)
P21 (Input & pulled down∗)
P22 (Input & pulled down∗)
P23 (Input & pulled down∗)
P40 (Input & pulled down∗)
P41 (Input & pulled down∗)
P42 (Input & pulled down∗)
P43 (Input & pulled down∗)
TOUT
TOUT_A
FOUT
FOUT
BZ
BZ
Master
SCLK(O)
SOUT(O)
SIN(I)
Slave
SCLK(I)
SOUT(O)
SIN(I)
SRDY(O)/SS(I)
R/f converter
RFIN0
REF0
SEN0
RFOUT
Stopwatch
direct input
RUN/LAP
RUN/LAP
Event
counter
EVIN_A
EVIN_B
EVIN_C
EVIN_D
∗When "With Pull-Down" is selected by mask option (high impedance when "Gate Direct" is selected)
Special output
When special outputs/peripheral functions are used (selected by software)
Serial I/F
For setting procedure of the functions, see explanations for each of the peripheral circuits.
2.3 Test Terminal (TEST)
This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST
terminal to VSS.