Epson S1C60N03 User manual

MF1045-03
Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C60N03 Technical Hardware
S1C60N03

NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001 All rights reserved.

The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C60 Family processors
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
S1 C60N01 F0A01 Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C60R08 D1 1Packing specification
Version (1: Version 1 ∗2)
Tool type (D1: Development Tool ∗1)
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
S1C62 Family processors
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
KIT6003
KIT6004
KIT6007
New No.
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
00
00

S1C60N03 TECHNICAL MANUAL EPSON i
CONTENTS
CONTENTS
CHAPTER 1INTRODUCTION ____________________________________________ 1
1.1 Features ......................................................................................................... 1
1.2 Block Diagram .............................................................................................. 2
1.3 Pad Layout .................................................................................................... 3
1.3.1 Pad layout diagram.................................................................................... 3
1.3.2 Pad coordinates.......................................................................................... 3
1.4 Pad Description ............................................................................................ 3
CHAPTER 2POWER SUPPLY AND INITIAL RESET_____________________________ 4
2.1 Power Supply ................................................................................................4
2.2 Initial Reset ................................................................................................... 6
2.2.1 Oscillation detection circuit....................................................................... 6
2.2.2 Reset terminal (RESET) ............................................................................. 6
2.2.3 Simultaneous high input to input ports (K00–K03) .................................. 6
2.2.4 Internal register following initialization ................................................... 7
2.3 Test Terminal (TEST) ....................................................................................7
CHAPTER 3 CPU, ROM, RAM________________________________________ 8
3.1 CPU............................................................................................................... 8
3.2 ROM .............................................................................................................. 8
3.3 RAM .............................................................................................................. 8
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 9
4.1 Memory Map ................................................................................................. 9
4.2 Oscillation Circuit ....................................................................................... 11
4.2.1 Crystal oscillation circuit.......................................................................... 11
4.2.2 CR oscillation circuit ................................................................................ 11
4.3 Input Ports (K00–K03) ................................................................................12
4.3.1 Configuration of input port ....................................................................... 12
4.3.2 Interrupt function ...................................................................................... 12
4.3.3 Mask option ............................................................................................... 13
4.3.4 I/O memory of input port .......................................................................... 14
4.3.5 Programming note..................................................................................... 14
4.4 Output Ports (R00–R03) .............................................................................. 15
4.4.1 Configuration of output port..................................................................... 15
4.4.2 Mask option ............................................................................................... 15
4.4.3 I/O memory of output port ........................................................................ 17
4.4.4 Programming note..................................................................................... 18
4.5 LCD Driver (COM0–COM3, SEG0–SEG14) ............................................. 19
4.5.1 Configuration of LCD driver .................................................................... 19
4.5.2 Cadence adjustment of oscillation frequency........................................... 24
4.5.3 Mask option ............................................................................................... 25
4.5.4 I/O memory of LCD driver........................................................................ 26
4.5.5 Programming note..................................................................................... 26

ii EPSON S1C60N03 TECHNICAL MANUAL
CONTENTS
4.6 Clock Timer .................................................................................................. 27
4.6.1 Configuration of clock timer..................................................................... 27
4.6.2 Interrupt function ...................................................................................... 27
4.6.3 Mask option ............................................................................................... 28
4.6.4 I/O memory of clock timer ........................................................................ 28
4.6.5 Programming notes ................................................................................... 29
4.7 Interrupt and HALT .....................................................................................30
4.7.1 Interrupt factors ........................................................................................ 31
4.7.2 Specific masks for interrupt ...................................................................... 31
4.7.3 Interrupt vectors ........................................................................................ 32
4.7.4 I/O memory of interrupt ............................................................................ 32
4.7.5 Programming notes ................................................................................... 33
CHAPTER 5BASIC EXTERNAL WIRING DIAGRAM ____________________________ 34
CHAPTER 6ELECTRICAL CHARACTERISTICS ________________________________ 36
6.1 Absolute Maximum Rating...........................................................................36
6.2 Recommended Operating Conditions..........................................................36
6.3 DC Characteristics ...................................................................................... 37
6.4 Analog Circuit Characteristics and Current Consumption ........................38
6.5 Oscillation Characteristics.......................................................................... 40
CHAPTER 7CERAMIC PACKAGE FOR TEST SAMPLES _________________________ 41
CHAPTER 8PRECAUTIONS ON MOUNTING _________________________________ 42

S1C60N03 TECHNICAL MANUAL EPSON 1
CHAPTER 1: INTRODUCTION
CHAPTER 1INTRODUCTION
The S1C60N03 Series single-chip microcomputer features an S1C6200B CMOS 4-bit CPU as the core. It
contains a 768 (words) ×12 (bits) ROM, 64 (words) ×4 (bits) RAM, LCD driver , 4-bit input port (K00–
K03), 4-bit output port (R00–R03) and a timer.
The S1C60N03 Series is configured as follows, depending on the supply voltage.
S1C60N03:3.0 V (1.8 to 3.6 V)
S1C60L03:1.5 V (1.2 to 2.0 V)
1.1 Features
Core CPU........................................... S1C6200B
Built-in oscillation circuit ............. Crystal 32.768 kHz (Typ.) or CR oscillation circuit 65 kHz (Typ.)
Instruction set .................................. 100 instructions
ROM capacity................................... 768 words ×12 bits
RAM capacity................................... 64 words ×4 bits
Input port .......................................... 4 bits (pull-down resistors are available by mask option)
Output ports ..................................... 4 bits (clock and buzzer outputs are possible by mask option)
LCD driver ........................................ 15 segments ×4, 3 or 2 commons
(1/4, 1/3 or 1/2 duty are selectable by mask option)
Timer .................................................. 1 system (clock timer) built-in
Interrupt ............................................ External: Input port interrupt 1 system
Internal: Timer interrupt 1 system
Supply voltage ................................. 1.5 V (1.2 to 2.0 V) S1C60L03
3.0 V (1.8 to 3.6 V) S1C60N03
Current consumption (Typ.) ......... During HALT: 1.0 µA (32 kHz crystal, with power divider OFF)
During execution: 2.5 µA (32 kHz crystal, with power divider OFF)
15 µA (32 kHz crystal, with power divider ON)
Supply form ..................................... Chip

2EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 1: INTRODUCTION
1.2 Block Diagram
OSC1
OSC2
COM0–3
SEG0–14
V DD
CA, CB
V
S2
V SS
K00–K03
TEST
RESET
R00 (FOUT, BUZZER)
∗1
R01 (BUZZER)
∗1
R02, R03
∗1: Terminal specifications can be selected by mask option.
Core CPU S1C6200B
ROM
768 words ×12 bits
System Reset
Control
Interrupt
Generator
RAM
64 words ×4 bits
LCD Driver
15 SEG ×4 COM
Power
Controller
OSC
FOUT
& Buzzer
Clock
Timer
Input Port
Output Port
Fig. 1.2.1 S1C60N03 block diagram

S1C60N03 TECHNICAL MANUAL EPSON 3
CHAPTER 1: INTRODUCTION
1.3 Pad Layout
1.3.1 Pad layout diagram
X
(0, 0)
Die No.
Y
2.03 mm
2.32 mm
151015
20 25
30
35
Fig. 1.3.1.1 Pad layout
1.3.2 Pad coordinates
Table 1.3.2.1 Pad coordinates (unit: µm)
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pad name
TEST
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
X
980
850
720
590
460
330
200
70
-60
-190
-320
-450
Y
849
849
849
849
849
849
849
849
849
849
849
849
No.
13
14
15
16
17
18
19
20
21
22
23
24
Pad name
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
CA
CB
V S2
V SS
X
-580
-710
-840
-970
-983
-853
-723
-593
-463
-333
-203
-50
Y
849
849
849
849
-849
-849
-849
-849
-849
-849
-849
-849
No.
25
26
27
28
29
30
31
32
33
34
35
36
Pad name
OSC2
OSC1
V DD
RESET
R00
R01
R02
R03
K00
K01
K02
K03
X80
210
340
470
994
994
994
994
994
994
994
994
Y
-849
-849
-849
-849
-760
-542
-403
-269
-120
10
140
270
1.4 Pad Description
Table 1.4.1 Pan description
Pad name
V
DD
V SS
V S2
CA, CB
OSC1
OSC2
K00–03
R00
R01
R02, R03
SEG0–14
COM0–3
RESET
TEST
Function
Power supply terminal (+)
Power supply terminal (-)
LCD system voltage doubler (2·V
SS )/halver (V SS /2) output
Booster capacitor connecting terminal
Crystal or CR oscillation input terminal *
Crystal or CR oscillation output terminal *
Input port terminal
Output port terminal, BUZZER or FOUT output terminal *
Output port terminal or BUZZER output terminal *
Output port terminal
LCD segment output or DC output terminal *
LCD common output terminal (1/4, 1/3 or 1/2 duty are selectable *)
Initial reset input terminal
Test input terminal
Pad No.
27
24
23
21, 22
26
25
33–36
29
30
31, 32
2–16
17–20
28
1
I/O
(I)
(I)
O
–
I
O
I
O
O
O
O
O
I
I
∗Can be selected by mask option
Chip thickness: 400 µm
Pad opening: 95 µm

4EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
With a single external power supply (∗) supplied to VDD through VSS, the S1C60N03 Series generates the
necessary internal voltages with the voltage doubler/halver and power divider.
∗Supply voltage: S1C60N03 ... 3.0 V S1C60L03 ... 1.5 V
Figure 2.1.1 shows the basic configuration of the power divider and voltage doubler/halver.
V DD
V DD
V L1
V S2
V L2
V L3
LON
Power
divider Voltage halver
(S1C60N03)
Voltage
doubler
(S1C60L03)
V S2
CA
CB
V SS
Mask option
Fig. 2.1.1 Basic configuration of the power divider and voltage doubler/halver
The power divider and voltage doubler/halver generate the LCD drive voltage (VL1, VL2, VL3). The
circuit is configured according to the model and the LCD drive bias selected by mask option. The LCD
drive bias can be selected from 1/3 bias, 1/2 bias (A) and 1/2 bias (B).
For S1C60N03
When 1/3 bias or 1/2 bias (A) is selected, the power divider is used to generate VL1 and VL2 by dividing
the source voltage with the resistors. The voltage doubler/halver is not used. In the S1C60N03, this
selection can reduce the external component count.
When 1/2 bias (B) is selected in the S1C60N03, the voltage halver is used to generate VL1 and VL2 and the
power divider is disconnected. This selection can reduce current consumption, but two external capaci-
tors are necessary for the voltage halver.
In the S1C60N03, the voltage doubler is not used.
Figure 2.1.2 shows the power circuit configuration of the S1C60N03 according to the selected mask
option.
For S1C60L03
The S1C60L03 always uses the voltage doubler to generate the LCD drive voltage from 1.5 V source
voltage. The voltage halver is not used.
When 1/3 bias or 1/2 bias (A) is selected, the power divider is used to generate VL1 and VL2 by dividing
the VS2 voltage generated by the voltage doubler.
When 1/2 bias (B) is selected in the S1C60L03, the power divider is not used.
Figure 2.1.3 shows the power circuit configuration of the S1C60L03 according to the selected mask option.

S1C60N03 TECHNICAL MANUAL EPSON 5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
S1C60N03
VDD
VS2
CA
CB
VSS
3.0 V
NC
NC
NC
VL1 = 1/3·VSS
VL2 = 2/3·VSS
VL3 = VSS
VDD
3 V LCD Panel
1/4, 1/3 or 1/2 duty, 1/3 bias
VL3 is shorted to VSS internally.Note:
VDD
VS2
CA
CB
VSS
3.0 V
NC
NC
NC
VL1 = 1/2·VSS
VL2 = 1/2·VSS
VL3 = VSS
VDD
3 V LCD Panel
1/4, 1/3 or 1/2 duty, 1/2 bias (A)
VL3–VSS and VL1–VL2 are shorted internally.Note:
VDD
VS2
CA
CB
VSS
3.0 V
VL1 = 1/2·VSS
VL2 = 1/2·VSS
VL3 = VSS
VDD
VS2
3 V LCD Panel
1/4, 1/3 or 1/2 duty, 1/2 bias (B)
VL3–VSS and VL1–VL2 are shorted internally.Note:
Voltage
halver
Fig. 2.1.2 Power circuit configuration of S1C60N03
S1C60L03
3 V LCD Panel
1/4, 1/3 or 1/2 duty, 1/3 bias
VL3 is shorted to VS2 internally.Note:
VDD
VS2
CA
CB
VSS
1.5 V
VL1 = 1/2·VS2
VL2 = 1/2·VS2
VL3 = 2·VSS
VDD
VS2
3 V LCD Panel
1/4, 1/3 or 1/2 duty, 1/2 bias (A)
VL3–VS2 and VL1–VL2 are shorted internally.Note:
Voltage
doubler
VDD
VS2
CA
CB
VSS
1.5 V
VL1 = VSS
VL2 = VSS
VL3 = 2·VSS
VDD
VS2
3 V LCD Panel
1/4, 1/3 or 1/2 duty, 1/2 bias (B)
VL3–VS2 and VL1–VL2 are shorted internally.Note:
Voltage
doubler
VDD
VS2
CA
CB
VSS
1.5 V
VL1 = 1/3·VS2
VL2 = 2/3·VS2
VL3 = 2·VSS
VDD
VS2 Voltage
doubler
Fig. 2.1.3 Power circuit configuration of S1C60L03

6EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C60N03 Series circuits, an initial reset must be executed. There are three ways of doing this.
(1) Initial reset by the oscillation detection circuit (Note)
(2) External initial reset via the RESET terminal
(3) External initial reset by simultaneous high input to K00–K03 (depending on mask option)
Figure 2.2.1 shows the configuration of the initial reset circuit.
Vss
RESET
K03
K02
K01
K00
OSC2
OSC1 OSC1
Oscillation
circuit
Vss
Oscillation
detection
circuit
Noise
rejection
circuit
Initial
reset
Noise
rejection
circuit
Fig. 2.2.1 Configuration of initial reset circuit
Note: Be sure to use reset function (2) or (3) at power-on because the initial reset function by the
oscillation detection circuit (1) may not operate normally depending on the power-on procedure.
2.2.1 Oscillation detection circuit
The oscillation detection circuit outputs the initial reset signal at power-on until the oscillation circuit
starts oscillating, or when the oscillation circuit stops oscillating for some reason.
However, use the following reset functions at power-on because the initial reset function by the oscilla-
tion detection circuit may not operate normally depending on the power-on procedure.
2.2.2 Reset terminal (RESET)
An initial reset can be invoked externally by making the reset terminal high. This high level must be
maintained for at least 5 msec (when oscillating frequency fosc = 32 kHz), because the initial reset circuit
contains a noise rejection circuit. When the reset terminal goes low the CPU begins to operate.
2.2.3 Simultaneous high input to input ports (K00–K03)
Another way of invoking an initial reset externally is to input a high signal simultaneously to the input
ports (K00–K03) selected with the mask option. The specified input port terminals must be kept high for
at least 4 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit. Table
2.2.3.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.3.1 Input port combinations
A Not used
B K00*K01
C K00*K01*K02
D K00*K01*K02*K03
When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the
signals input to the four ports K00–K03 are all high at the same time.
When this function is used, make sure that the specified ports do not go high at the same time during
normal operation.

S1C60N03 TECHNICAL MANUAL EPSON 7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.4 Internal register following initialization
An initial reset initializes the CPU as shown in the table below.
Table 2.2.4.1 Initial values
∗See Section 4.1, "Memory Map".
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Index register X
Index register Y
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
CPU Core
Symbol
PCS
PCP
NPP
SP
X
Y
RP
A
B
I
D
Z
C
Bit size
8
4
4
8
8
8
4
4
4
1
1
1
1
Initial value
00H
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral Circuits
Bit size
64 ×4
16 ×4
–
Initial value
Undefined
Undefined
∗
2.3 Test Terminal (TEST)
This terminal is used when IC is inspected for shipment. During normal operation connect it to VSS.

8EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3 CPU, ROM, RAM
3.1 CPU
The S1C60N03 Series employs the S1C6200B core CPU, so that register configuration, instructions, and so
forth are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B.
Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B.
Note the following points with regard to the S1C60N03 Series:
(1) Since the S1C60N03 Series don't provides the SLEEP function, the SLP instruction can not be used.
(2) Because the ROM capacity is 768 words, 12 bits per word, bank bits are unnecessary, and PCB and
NBP are not used.
(3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is
invalid.
PUSH XP POP XP LD XP,r LD r,XP
PUSH YP POP YP LD YP,r LD r,YP
3.2 ROM
The built-in ROM, a mask ROM for the program, has a capacity of 768 ×12-bit steps. The program area is
3 pages (0–2), each consisting of 256 steps (00H–FFH). After an initial reset, the program start address is
set to page 1, step 00H. The interrupt vectors are allocated to page l, steps 01H–07H.
Step 00H
Step 07H
Step 08H
Step FFH
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
Page 0
Page 1
Page 2
Step 01H
Fig. 3.2.1 ROM configuration
3.3 RAM
The RAM, a data memory for storing a variety of data, has a capacity of 64 words, 4-bit words. When
programming, keep the following points in mind:
(1) Part of the data memory is used as stack area when saving subroutine return addresses and registers,
so be careful not to overlap the data area and stack area.
(2) Subroutine calls and interrupts take up three words on the stack.
(3) Data memory 000H–00FH is the memory area pointed by the register pointer (RP).

S1C60N03 TECHNICAL MANUAL EPSON 9
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION
Peripheral circuits (timer, I/O, and so on) of the S1C60N03 Series are memory mapped. Thus, all the
peripheral circuits can be controlled by using memory operations to access the I/O memory. The follow-
ing sections describe how the peripheral circuits operate.
4.1 Memory Map
The data memory of the S1C60N03 Series has an address space of 89 words, of which 16 words are
allocated to display memory and 9 words, to I/O memory. Figure 4.1.1 show the overall memory map for
the S1C60N03 Series, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space).
Address
Page High
Low 0123456789ABCDEF
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
3
0
1
2
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM area (000H–03FH)
64 words ×4 bits (R/W)
Display memory ares (0E0H–0EFH) 16 words ×4 bits (W only)
Unused area
I/O memory See Table 4.1.1
Fig. 4.1.1 Memory map
Note: Memory is not mounted in unused area within the memory map and in memory area not indicated
in this chapter. For this reason, normal operation cannot be assured for programs that have been
prepared with access to these areas.

10 EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 I/O memory map
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0F0H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗ 2
–
∗ 2
–
∗ 2
–
∗ 2
High
High
High
High
Low
Low
Low
Low
K0 input port data
0F2H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
∗ 2
–
∗ 2
–
∗ 2
–
∗ 2
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Clock timer data (16 Hz)
0F3H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
0F4H
TMRST EIT2 EIT16 EIT32
WR/W
TMRST
∗ 3
EIT2
EIT16
EIT32
Reset
0
0
0
Reset
Enable
Enable
Enable
–
Mask
Mask
Mask
Clock timer reset
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 16 Hz)
Interrupt mask register (clock timer 32 Hz)
0F5H
000IK0
R
0
∗ 3
0
∗ 3
0
∗ 3
IK0
∗ 4
–
∗ 2
–
∗ 2
–
∗ 2
0
–
–
–
Yes
–
–
–
No
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
0F6H
0 IT2 IT16 IT32
R
0
∗ 3
IT2
∗ 4
IT16
∗ 4
IT32
∗ 4
–
∗ 2
0
0
0
–
Yes
Yes
Yes
–
No
No
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 16 Hz)
Interrupt factor flag (clock timer 32 Hz)
0F8H
LON 0 0 CSDC
R/W R/WR
LON
0
∗ 3
0
∗ 3
CSDC
0
–
∗ 2
–
∗ 2
0
On
–
–
Static
Off
–
–
Dynamic
LCD power and display On/Off conrol
Unused
Unused
LCD drive switch
∗1
∗2Initial value at initial reset Not set in the circuit ∗3 ∗4Always "0" being read Reset (0) immediately after being read
0F1H
R03 R02 R01
BUZZER
R00
FOUT
BUZZER
R/W
R03
R02
R01
BUZZER
R00
FOUT
BUZZER
0
0
0
0
0
0
0
High
High
High
On
High
On
On
Low
Low
Low
Off
Low
Off
Off
R03 output port data
R02 output port data
R01 output port data
Buzzer output On/Off control
R00 output port data
FOUT output On/Off
control
Buzzer inverted output On/Off control
0F7H
XBZR 0 XFOUT1 XFOUT0
R/W R R/W
XBZR
0
∗ 3
XFOUT1
XFOUT0
0
–
∗ 2
0
0
2 kHz
–4 kHz –
Buzzer frequency control
Unused
FOUT frequency control
0: F1, 1: F2, 2: F3, 3: F4

S1C60N03 TECHNICAL MANUAL EPSON 11
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.2 Oscillation Circuit
The S1C60N03 Series has a built-in oscillation circuit that generates the operating clock of the CPU and
the peripheral circuit. Either crystal oscillation or CR oscillation can be selected for the oscillation circuit
by mask option.
4.2.1 Crystal oscillation circuit
The crystal oscillation circuit can be selected by mask option. The oscillation frequency (fosc) is 32.768
kHz (Typ.).
Figure 4.2.1.1 shows the configuration of the crystal oscillation circuit.
VDD
VDD
OSC2
OSC1
X'tal
CGCPU
and peripheral circuits
RF
CD
RD
Fig. 4.2.1.1 Configuration of crystal oscillation circuit
As Figure 4.2.1.1 indicates, the crystal oscillation circuit can be configured simply by connecting the
crystal oscillator X'tal (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals and the trimmer capaci-
tor CG(5–25 pF) between the OSC1 and VDD terminals.
Note: The OSC1 and OSC2 terminals on the board should be shielded with the VDD (+ side).
4.2.2 CR oscillation circuit
The CR oscillation circuit can also be selected by mask option. The oscillation frequency (fosc) is 65 kHz
(Typ.).
Figure 4.2.2.1 shows the configuration of the CR oscillation circuit.
OSC2
OSC1 CPU
and peripheral circuits
CCR
RCR
Fig. 4.2.2.1 Configuration of CR oscillation circuit
As Figure 4.2.2.1 indicates, the CR oscillation circuit can be configured simply by connecting the resistor
RCR between terminals OSC1 and OSC2 since capacity (CCR) is built-in.
See Chapter 6, "Electrical Characteristics" for RCR value.

12 EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.3 Input Ports (K00–K03)
4.3.1 Configuration of input port
The S1C60N03 Series has a 4-bit general-purpose input port. Each of the input port terminals (K00–K03)
has an internal pull-down resistor. The pull-down resistor can be selected for each bit with the mask
option.
Figure 4.3.1.1 shows the configuration of input port.
Mask option
Address
Data bus
Kxx
Interrupt
request
V
DD
V SS
Fig. 4.3.1.1 Configuration of input port
Selecting "pull-down resistor enabled" with the mask option allows input from a push button, key matrix,
and so forth. When "pull-down resistor disabled" is selected, the port can be used for slide switch input
and interfacing with other LSIs.
4.3.2 Interrupt function
All four input port bits (K00–K03) provide the interrupt function. The conditions for issuing an interrupt
can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected
individually for all four bits by the software. Figure 4.3.2.1 shows the configuration of K00–K03.
Data bus
Address
Interrupt mask
register (EIK)
Kxx
Mask option
(K00–K03)
Noise
rejector Interrupt factor
flag (IK0) Interrupt
request
Address Address
Fig. 4.3.2.1 Input interrupt circuit configuration (K00–K03)
The interrupt mask registers (EIK00–EIK03) enable the interrupt mask to be selected individually for
K00–K03. An interrupt occurs when the input value which are not masked change and the interrupt
factor flag (IK0) is set to 1.

S1C60N03 TECHNICAL MANUAL EPSON 13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Input interrupt programming related precautions
Port K input
Factor flag set Not set
Mask register
Active status
➀
When the content of the mask register is rewritten, while the port
K input is in the active status. The input interrupt factor flag is
set at ➀.Fig. 4.3.2.2 Input interrupt timing
When using an input interrupt, if you rewrite the content of the mask register, when the value of the
input terminal which becomes the interrupt input is in the active status (input terminal = high status), the
factor flag for input interrupt may be set.
For example, a factor flag is set with the timing of ➀shown in Figure 4.3.2.2. However, when clearing the
content of the mask register with the input terminal kept in the high status and then setting it, the factor
flag of the input ir 5rrupt is again set at the timing that has been set.
Consequently, when the input terminal is in the active status (high status), do not rewrite the mask
register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in
this case. When clearing, then setting the mask register, set the mask register, when the input terminal is
not in the active status (low status).
4.3.3 Mask option
The contents that can be selected with the input port mask option are as follows:
(1) An internal pull-down resistor can be selected for each of the four bits of the input ports (K00–K03).
Having selected "pull-down resistor disabled", take care that the input does not float. Select "pull-
down resistor enabled" for input ports that are not being used.
(2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring
through noise. The mask option enables selection of the noise rejection circuit for each separate
terminal series. When "use" is selected, a maximum delay of 0.5 msec (fosc = 32 kHz) occurs from the
time an interrupt condition is established until the interrupt factor flag (IK0) is set to 1.

14 EPSON S1C60N03 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.3.4 I/O memory of input port
Table 4.3.4.1 list the input port control bits and their addresses.
Table 4.3.4.1 Input port control bits
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0F0H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗ 2
–
∗ 2
–
∗ 2
–
∗ 2
High
High
High
High
Low
Low
Low
Low
K0 input port data
0F3H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
0F5H
000IK0
R
0
∗ 3
0
∗ 3
0
∗ 3
IK0
∗ 4
–
∗ 2
–
∗ 2
–
∗ 2
0
–
–
–
Yes
–
–
–
No
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
∗1
∗2Initial value at initial reset Not set in the circuit ∗3 ∗4Always "0" being read Reset (0) immediately after being read
K00–K03: Input port data (0F0H)
The input data of the input port terminals can be read with these registers.
When 1 is read: High level
When 0 is read: Low level
Writing: Invalid
The value read is 1 when the terminal voltage of the input port (K00–K03) goes high (VDD), and 0 when
the voltage goes low (VSS). These are read only bits, so writing cannot be done.
EIK00–EIK03: Interrupt mask registers (0F3H)
Masking the interrupt of the input port terminals can be done with these registers.
When 1 is written: Enable
When 0 is written: Mask
Reading: Valid
With these registers, masking of the input port bits can be done for each of the four bits.
After an initial reset, these registers are all set to 0.
IK0: Interrupt factor flag (0F5H•D0)
This flag indicates the occurrence of an input interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flag IK0 is associated with K00–K03. From the status of this flag, the software can
decide whether an input interrupt has occurred.
This flag is reset when the software has read it.
Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not
be generated.
After an initial reset, this flag is set to 0.
4.3.5 Programming note
When modifying the input port from high level to low level with pull-down resistor, a delay will occur at
the fall of the waveform due to time constant of the pull-down resistor and input gate capacities. Provide
appropriate waiting time in the program when performing input port reading.