Epson S1C63666 User manual

Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C63666 Technical Hardware
S1C63666

NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2007, All rights reserved.

Revisions and Additions for this manual
Section
1.1
1.5
2.1.5
2.2
2.2.1
2.2.2
4.1
4.6.4
4.6.5
4.8.1
4.8.2
4.8.3
4.8.5
4.10.6
4.10.7
4.11.1
4.11.7
4.11.9
4.12.3
4.15.2
4.15.3
4.15.4
4.15.5
4.15.6
4.17.2
4.17.3
4.17.4
4.18
4.18.1
4.18.2
4.18.4
5.2
5.3
7.1
7.2
7.3
7.4
7.5
7.6
A.2
A.3.2
Page
1
5–8
11
12
12
13
17, 18, 20, 24
43–44
46
53
53
57
58
72
74, 76, 77
78
82
88
91
112
113–114
116–117
118, 120, 121
121
124
125
126
128
129
130
131–132
138
140
142
142
142
143
144
146
155
158
Item
Features
Mask Option
LCD system voltage circuit
Initial Reset
Reset terminal (RESET)
Simultaneous high input to terminals
K00–K03
Memory Map
Special output
I/O memory of output ports
Configuration of LCD driver
Power supply for LCD driving
Control of LCD display and drive waveform
Segment option
Interrupt function
I/O memory of stopwatch timer
Configuration of programmable timer
Control of TOUT output
I/O memory of programmable timer
Master mode and slave mode of serial interface
Connection terminals and CR oscillation
circuit
Operation of R/f conversion
Interrupt function
I/O memory of R/f converter
Programming notes
Mask option
SVD operation
I/O memory of SVD circuit
Interrupt and HALT
Interrupt factor
Interrupt mask
I/O memory of interrupt
Summary of Notes by Function
Precautions on Mounting
Absolute Maximum Rating
Recommended Operating Conditions
DC Characteristics
Analog Circuit Characteristics and Power
Current Consumption
Oscillation Characteristics
Serial Interface AC Characteristics
Connecting to the Target System
Differences with the actual IC
Contents
Explanation was revised.
Explanation was revised.
Figure 2.1.5.1 was revised.
Figure 2.2.1 was revised.
Explanation was added.
Explanation was revised.
Table 2.2.2.1 was revised.
Explanation was revised.
Tables 4.1.1(a), (c), (g) were revised.
Figures 4.6.4.1–4.6.4.2 were revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
A note was added.
Figure 4.8.5.1 was revised.
Explanation was revised.
Table 4.10.7.1 was revised.
Explanation was revised.
Explanation was revised.
Figures 4.11.7.1–4.11.7.2 were revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Figure 4.15.2.3 was revised.
Explanation was revised.
Figures 4.15.3.1–4.15.3.2 were revised.
Explanation was revised.
Figures 4.15.4.1–4.15.4.4 were revised.
Table 4.15.5.1 was revised.
Explanation was revised.
Item (4) was added.
Explanation was revised.
Explanation was revised.
Table 4.17.4.1 was revised.
Explanation was revised.
Figure 4.18.1 was revised.
Table 4.18.1.1 was revised.
Table 4.18.2.1 was revised.
Tables 4.18.4.1(a), (b) were revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Table was revised.
Table was revised.
Table was revised.
Table was revised.
Table was revised.
Figure was revised.
Figure A.2.1 was revised.
Explanation was revised.
Figure was deleted.
Chapter
1
2
4
5
7
Appendix

Devices
S1 C 63158 F 0A01
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 63000 A1 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Ex : EVA board
Px : Peripheral board
Wx: Flash ROM writer for the microcomputer
Xx : ROM writer peripheral board
Cx : C compiler package
Ax : Assembler package
Dx : Utility tool by the model
Qx : Soft simulator
Corresponding model number
63000: common to S1C63 Family
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number

S1C63666 TECHNICAL MANUAL EPSON i
CONTENTS
CONTENTS
CHAPTER 1OUTLINE ________________________________________________ 1
1.1 Features ......................................................................................................... 1
1.2Block Diagram .............................................................................................. 2
1.3 Pin Layout Diagram .....................................................................................3
1.4 Pin Description ............................................................................................. 4
1.5 Mask Option.................................................................................................. 5
CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 9
2.1 Power Supply ................................................................................................9
2.1.1 Voltage regulator for OSC1 oscillation circuit ......................................... 10
2.1.2 Low-speed operation voltage regulator .................................................... 10
2.1.3 High-speed operation voltage regulator................................................... 10
2.1.4 Internal operating voltage VD1....................................................................................... 10
2.1.5 LCD system voltage circuit ....................................................................... 10
2.1.6 Halver mode and saving power ................................................................ 11
2.1.7 Analog system power supply ..................................................................... 11
2.2 Initial Reset ..................................................................................................12
2.2.1 Reset terminal (RESET) ............................................................................ 12
2.2.2 Simultaneous high input to terminals K00–K03 ...................................... 13
2.2.3 Internal register at initial resetting........................................................... 13
2.2.4 Terminal settings at initial resetting ......................................................... 14
2.3 Test Terminal (TEST) ................................................................................... 14
CHAPTER 3 CPU, ROM, RAM________________________________________ 15
3.1 CPU..............................................................................................................15
3.2 Code ROM....................................................................................................15
3.3 RAM .............................................................................................................15
3.4 Data ROM ....................................................................................................16
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 17
4.1 Memory Map................................................................................................17
4.2 Power Control ..............................................................................................25
4.2.1 Configuration of power supply circuit...................................................... 25
4.2.2 Power control procedure ........................................................................... 26
4.2.3 I/O memory for power control .................................................................. 27
4.2.4 Programming notes ................................................................................... 29
4.3Watchdog Timer ........................................................................................... 30
4.3.1 Configuration of watchdog timer .............................................................. 30
4.3.2 Interrupt function ...................................................................................... 30
4.3.3 I/O memory of watchdog timer ................................................................. 31
4.3.4 Programming notes ................................................................................... 31
4.4 Oscillation Circuit ....................................................................................... 32
4.4.1 Configuration of oscillation circuit .......................................................... 32
4.4.2 OSC1 oscillation circuit ............................................................................ 32
4.4.3 OSC3 oscillation circuit ............................................................................ 33
4.4.4 Switching of operating voltage ................................................................. 34
4.4.5 Clock frequency and instruction execution time....................................... 34
4.4.6 I/O memory of oscillation circuit.............................................................. 35
4.4.7 Programming notes ................................................................................... 36

ii EPSON S1C63666 TECHNICAL MANUAL
CONTENTS
4.5 Input Ports (K00–K03 and K10–K13) .........................................................37
4.5.1 Configuration of input ports ..................................................................... 37
4.5.2 Interrupt function ...................................................................................... 37
4.5.3 Mask option ............................................................................................... 38
4.5.4 I/O memory of input ports......................................................................... 39
4.5.5 Programming notes ................................................................................... 41
4.6 Output Ports (R00–R03 and R10–R13) .......................................................42
4.6.1 Configuration of output ports ................................................................... 42
4.6.2 Mask option ............................................................................................... 42
4.6.3 High impedance control ............................................................................ 43
4.6.4 Special output ............................................................................................ 43
4.6.5 I/O memory of output ports....................................................................... 45
4.6.6 Programming notes ................................................................................... 47
4.7 I/O Ports (P00–P03 and P10–P13) ............................................................. 48
4.7.1 Configuration of I/O ports ........................................................................ 48
4.7.2 Mask option ............................................................................................... 49
4.7.3 I/O control registers and input/output mode ............................................ 49
4.7.4 Pull-down during input mode ................................................................... 49
4.7.5 I/O memory of I/O ports............................................................................ 50
4.7.6 Programming note..................................................................................... 52
4.8 LCD Driver (COM0–COM7, SEG0–SEG63) ............................................. 53
4.8.1 Configuration of LCD driver .................................................................... 53
4.8.2 Power supply for LCD driving .................................................................. 53
4.8.3 Control of LCD display and drive waveform ........................................... 53
4.8.4 Display memory......................................................................................... 58
4.8.5 Segment option .......................................................................................... 58
4.8.6 LCD contrast adjustment .......................................................................... 60
4.8.7 I/O memory of LCD driver........................................................................ 61
4.8.8 Programming note..................................................................................... 62
4.9 Clock Timer ..................................................................................................63
4.9.1 Configuration of clock timer ..................................................................... 63
4.9.2 Data reading and hold function ................................................................ 63
4.9.3 Interrupt function ...................................................................................... 64
4.9.4 I/O memory of clock timer ........................................................................ 65
4.9.5 Programming notes ................................................................................... 66
4.10 Stopwatch Timer........................................................................................... 67
4.10.1 Configuration of stopwatch timer ........................................................... 67
4.10.2 Counter and prescaler............................................................................. 67
4.10.3 Capture buffer and hold function............................................................ 68
4.10.4 Stopwatch timer RUN/STOP and reset ................................................... 69
4.10.5 Direct input function and key mask ........................................................ 69
4.10.6 Interrupt function .................................................................................... 72
4.10.7 I/O memory of stopwatch timer .............................................................. 74
4.10.8 Programming notes ................................................................................. 77
4.11 Programmable Timer ...................................................................................78
4.11.1 Configuration of programmable timer.................................................... 78
4.11.2 Basic count operation ............................................................................. 79
4.11.3 Setting the input clock ............................................................................. 80
4.11.4 Event counter mode (timer 0) ................................................................. 80
4.11.5 16-bit timer (timer 0 + timer 1) .............................................................. 81
4.11.6 Interrupt function .................................................................................... 82
4.11.7 Control of TOUT output .......................................................................... 82
4.11.8 Transfer rate setting for serial interface ................................................ 83
4.11.9 I/O memory of programmable timer ....................................................... 84
4.11.10 Programming notes ............................................................................... 89

S1C63666 TECHNICAL MANUAL EPSON iii
CONTENTS
4.12 Serial Interface (SIN, SOUT, SCLK, SRDY)................................................ 90
4.12.1 Configuration of serial interface ............................................................ 90
4.12.2 Mask option ............................................................................................. 91
4.12.3 Master mode and slave mode of serial interface.................................... 91
4.12.4 Data input/output and interrupt function ............................................... 92
4.12.5 I/O memory of serial interface................................................................ 95
4.12.6 Programming notes ................................................................................. 98
4.13 Sound Generator.......................................................................................... 99
4.13.1 Configuration of sound generator .......................................................... 99
4.13.2 Control of buzzer output.......................................................................... 99
4.13.3 Setting of buzzer frequency and sound level.......................................... 100
4.13.4 Digital envelope ..................................................................................... 101
4.13.5 One-shot output ...................................................................................... 102
4.13.6 I/O memory of sound generator ............................................................. 103
4.13.7 Programming notes ................................................................................ 105
4.14 Integer Multiplier........................................................................................106
4.14.1 Configuration of integer multiplier........................................................ 106
4.14.2 Multiplication mode ............................................................................... 106
4.14.3 Division mode......................................................................................... 107
4.14.4 Execution cycle....................................................................................... 108
4.14.5 I/O memory of integer multiplier ........................................................... 109
4.14.6 Programming note.................................................................................. 110
4.15 R/f Converter...............................................................................................111
4.15.1 Configuration of R/f converter ............................................................... 111
4.15.2 Connection terminals and CR oscillation circuit .................................. 111
4.15.3 Operation of R/f conversion ................................................................... 113
4.15.4 Interrupt function ................................................................................... 116
4.15.5 I/O memory of R/f converter .................................................................. 118
4.15.6 Programming notes ................................................................................ 121
4.16 Analog Comparator ....................................................................................122
4.16.1 Configuration of analog comparator..................................................... 122
4.16.2 Analog comparator operation................................................................ 122
4.16.3 I/O memory of analog comparator ........................................................ 123
4.16.4 Programming notes ................................................................................ 123
4.17 SVD (Supply Voltage Detection) Circuit.....................................................124
4.17.1 Configuration of SVD circuit ................................................................. 124
4.17.2 Mask option ............................................................................................ 124
4.17.3 SVD operation ........................................................................................ 125
4.17.4 I/O memory of SVD circuit..................................................................... 126
4.17.5 Programming notes ................................................................................ 126
4.18 Interrupt and HALT .................................................................................... 127
4.18.1 Interrupt factor....................................................................................... 129
4.18.2 Interrupt mask ........................................................................................ 130
4.18.3 Interrupt vector ...................................................................................... 130
4.18.4 I/O memory of interrupt ......................................................................... 131
4.18.5 Programming notes ................................................................................ 133
CHAPTER 5SUMMARY OF NOTES ______________________________________ 134
5.1 Notes for Low Current Consumption.......................................................... 134
5.2 Summary of Notes by Function................................................................... 135
5.3 Precautions on Mounting ........................................................................... 139
CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ___________________________ 141

iv EPSON S1C63666 TECHNICAL MANUAL
CONTENTS
CHAPTER 7ELECTRICAL CHARACTERISTICS _______________________________ 142
7.1 Absolute Maximum Rating.......................................................................... 142
7.2 Recommended Operating Conditions......................................................... 142
7.3 DC Characteristics .....................................................................................142
7.4 Analog Circuit Characteristics and Power Current Consumption ............ 143
7.5 Oscillation Characteristics.........................................................................144
7.6 Serial Interface AC Characteristics ...........................................................146
7.7 Timing Chart ...............................................................................................147
7.8 R/f Converter Characteristics.....................................................................147
CHAPTER 8PACKAGE _______________________________________________ 148
8.1 Plastic Package ...........................................................................................148
8.2 Ceramic Package for Test Samples.............................................................149
CHAPTER 9PAD LAYOUT ____________________________________________ 150
9.1 Diagram of Pad Layout...............................................................................150
9.2 Pad Coordinates.......................................................................................... 151
APPENDIX S5U1C63000P1 MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63666) __ 152
A.1 Names and Functions of Each Part ............................................................ 152
A.2 Connecting to the Target System ................................................................155
A.3 Usage Precautions ...................................................................................... 157
A.3.1 Operational precautions .......................................................................... 157
A.3.2 Differences with the actual IC ................................................................. 157

S1C63666 TECHNICAL MANUAL EPSON 1
CHAPTER 1: OUTLINE
CHAPTER 1OUTLINE
The S1C63666 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU,
ROM (16,384 words ×13 bits), RAM (5,120 words ×4 bits), multiply-divide circuit, serial interface, watchdog
timer, programmable timer, time base counters (2 systems), an LCD driver that can drive a maximum 64
segments ×8 commons, sound generator and R/f converter built-in. The S1C63666 features low current
consumption, this makes it suitable for battery driven portable equipment with R/f converter.
1.1 Features
OSC1 oscillation circuit ...................... 32.768 kHz (Typ.) crystal oscillation circuit
OSC3 oscillation circuit ...................... 4 MHz (Max.) ceramic or 1.1 MHz (Typ.) CR oscillation circuit (∗1)
Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)
Addressing mode: 8 types
Instruction execution time................... During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec
During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec
ROM capacity ..................................... Code ROM: 16,384 words ×13 bits
Data ROM: 4,096 words ×4 bits
RAM capacity...................................... Data memory: 5,120 words ×4 bits
Display memory: 160 words ×4 bits
Input port............................................. 8 bits (Pull-down resistors may be supplemented ∗1)
Output port.......................................... 8 bits (It is possible to switch the 2 bits to special output ∗2)
I/O port................................................ 8 bits (It is possible to switch the 4 bits to serial I/F input/output ∗2)
Serial interface.................................... 1 port (8-bit clock synchronous system)
LCD driver........................................... 64 segments ×4, 5 or 8 commons (∗2)
Time base counter.............................. Clock timer
Stopwatch timer (1/1000 sec, with direct key input function)
Programmable timer ........................... 8 bits ×3 ch. or 16 bits ×1 ch. + 8 bits ×1 ch. (∗2)
Watchdog timer................................... Built-in
Sound generator ................................. With envelope and 1-shot output functions
R/f converter ....................................... 2 ch., CR oscillation type, 20-bit counter
Multiply-divide circuit .......................... 8-bit accumulator ×1 ch.
Multiplication: 8 bits ×8 bits →16-bit product
Division: 16 bits ÷8 bits →8-bit quotient and 8-bit remainder
Analog comparator ............................. 1 ch.
Supply voltage detection (SVD) circuit.. Criteria voltage is selectable from 8 types (1.85 to 2.90 V ∗2)
(External voltage detection is possible ∗1)
External interrupt ................................ Input port interrupt: 2 systems
Internal interrupt ................................. Clock timer interrupt: 4 systems
Stopwatch timer interrupt: 4 systems
Programmable timer interrupt: 3 systems
Serial interface interrupt: 1 system
R/f converter interrupt: 2 systems
Power supply voltage.......................... 2.4 to 3.6 V: Max. 4 MHz operation in normal mode
2.4 to 3.6 V: 32 kHz operation in halver mode
1.5 to 3.6 V: 32 kHz operation in normal mode
Operating temperature range ............. -20 to 70°C
Current consumption (Typ.) ................ Low-speed operation (OSC1 = 32 kHz crystal oscillation):
During HALT 3.0 V (LCD ON, halver mode) 0.65 µA
During operation 3.0 V (LCD ON, halver mode) 2.5 µA
High-speed operation (OSC3):
During operation 3.0 V (LCD ON) 1 mA
Package .............................................. QFP20-144pin (plastic) or chip
∗1: Can be selected with mask option ∗2: Can be selected with software

2EPSON S1C63666 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.2 Block Diagram
Fig. 1.2.1 Block diagram
OSC1
OSC2
OSC3
OSC4
COM0–7
SEG0–63
VDD
VDDA
VC1–3
VD1–2
VOSC
CA–CD
VSS
VSSA
SVD
K00–K03
K10–K13
TEST
SEN0, SEN1
REF
RFIN
RFOUT
RESET
R00–R03
R10–R13
P00–P03
P10–P13
BZ
BZ
CMPP0
CMPM0
Core CPU S1C63000
ROM
16,384 words ×13 bits System Reset
Control
Interrupt
Generator
OSC
RAM
5,120 words ×4 bits
Data ROM
4,096 words ×4 bits
LCD Driver
64 SEG ×8 COM
Power
Controller
SVD
Sound
Generator
Analog
Comparator
Clock
Timer
Stopwatch
Timer
Programmable
Timer/Counter
Input Port
R/F Converter
Serial Interface
I/O Port
Output Port

S1C63666 TECHNICAL MANUAL EPSON 3
CHAPTER 1: OUTLINE
1.3 Pin Layout Diagram
QFP20-144pin
73108
37
72
INDEX
361
144
109
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pin name
N.C.
COM0
COM1
COM2
COM3
CA
CB
VC1
VC2
VC3
CMPP0
CMPM0
SVD
VSSA
RFOUT
RFIN
REF
SEN0
SEN1
VDDA
CC
CD
VD2
VDD
VOSC
OSC1
OSC2
VD1
OSC3
OSC4
VSS
TEST
RESET
N.C.
N.C.
N.C.
Pin name
N.C.
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
N.C.
N.C.
N.C.
Pin name
N.C.
N.C.
N.C.
COM4
COM5
COM6
COM7
VDD
K00
K01
K02
K03
K10
K11
K12
K13
P00
P01
P02
P03
P10
P11
P12
P13
R00
R01
R02
R03
R10
R11
R12
R13
BZ
BZ
VSS
N.C.
Pin name
N.C.
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
N.C.
N.C.
N.C.
N.C. : No Connection
Fig. 1.3.1 Pin layout diagram (QFP20-144pin)

4EPSON S1C63666 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.4 Pin Description
Table 1.4.1 Pin description
Pin name
V
DD
V SS
V DDA
V SSA
V D1
V D2
V OSC
V C1 –V C3
CA, CB
CC, CD
OSC1
OSC2
OSC3
OSC4
K00–K03
K10–K13
P00
P01
P02
P03
P10–P13
R00
R01
R02
R03
R10–R13
COM0–COM7
SEG0–SEG63
SEN0
SEN1
REF
RFIN
RFOUT
CMPP0
CMPM0
BZ
BZ
SVD
RESET
TEST
Function
Power (+) supply pin
Power (–) supply pin
Analog system power (+) supply pin (=V
DD )
Analog system power (–) supply pin (=V
SS )
Internal logic system regulated voltage output pin
1/2V
DD voltage halver output pin
Oscillation system regulated voltage output pin
LCD system power supply pin
LCD system voltage booster capacitor connecting pin
Voltage halver capacitor connecting pin
Crystal oscillation input pin
Crystal oscillation output pin
Ceramic or CR oscillation input pin (selected by mask option)
Ceramic or CR oscillation output pin (selected by mask option)
Input port pins
Input port pins
I/O port or serial I/F data input pin (selected by software)
I/O port or serial I/F data output pin (selected by software)
I/O port or serial I/F clock I/O pin (selected by software)
I/O port or serial I/F ready signal output pin (selected by software)
I/O port pins
Output port pin
Output port pin
Output port or TOUT output pin (selected by software)
Output port or FOUT output pin (selected by software)
Output port pins
LCD common output pin (1/4, 1/5 or 1/8 duty is selectable by software)
LCD segment output pin
R/f converter sensor 0 CR oscillation output pin
R/f converter sensor 1 CR oscillation output pin
R/f converter reference resistor CR oscillation output pin
R/f converter CR oscillation input pin
R/f converter oscillation frequency output pin
Analog comparator non-inverted input pin
Analog comparator inverted input pin
Sound output pin
Sound inverted output pin
SVD external voltage input pin
Initial reset input pin
Testing input pin
I/O
–
–
–
–
–
–
–
–
–
–
I
O
I
O
I
I
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
O
I
I
O
O
I
I
I
Pin No.
24
31
20
14
28
23
25
8–10
6, 7
21, 22
26
27
29
30
81–84
85–88
89
90
91
92
93–96
97
98
99
100
101–104
2–5, 76–79
110–141, 38–69
18
19
17
16
15
11
12
105
106
13
33
32

S1C63666 TECHNICAL MANUAL EPSON 5
CHAPTER 1: OUTLINE
1.5 Mask Option
Mask options shown below are provided for the S1C63666. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog and segment option generator winsog, that have been prepared as the development
software tool of S1C63666, are used for this selection. Mask pattern of the IC is finally generated based on
the data created by winfog and winsog. Refer to the "S5U1C63000A Manual" for winfog and winsog.
<Outline of the mask option>
(1) OSC1 oscillation circuit
The OSC1 oscillation circuit is fixed at crystal oscillation. Refer to Section 4.4.2, "OSC1 oscillation
circuit", for details.
(2) OSC3 oscillation circuit
The OSC3 oscillator type can be selected from ceramic oscillation, CR oscillation (external R) and CR
oscillation (built-in R). Refer to Section 4.4.3, "OSC3 oscillation circuit", for details.
(3) External voltage detection of the SVD circuit
External voltage (SVD terminal voltage) detection can be selected in addition to supply voltage (VDD
terminal–VSS terminal) detection. Refer to Section 4.17.2, "Mask option", for details.
(4) Input port pull-down resistor
The mask option is used to select whether the pull-down resistor is supplemented to the input ports
or not. It is possible to select for each bit of the input ports.
Refer to Section 4.5.3, "Mask option", for details.
(5) RESET terminal pull-down resistor
This option is used to select whether the pull-down resistor is supplemented to the RESET terminal or
not. Refer to Section 2.2.1, "Reset terminal (RESET)", for details.
(6) I/O port pull-down resistor
The mask option is used to select whether the pull-down resistor working in the input mode is
supplemented to the I/O ports or not. It is possible to select for each bit of the input ports.
Refer to Section 4.7.2, "Mask option", for details.
(7) Output specification of the output port
Either complementary output or P-channel open drain output can be selected as the output specifica-
tion for the output ports R00–R03 and R10–R13. The selection is done in 1-bit units.
Refer to Section 4.6.2, "Mask option", for details.
(8) Output specification of the I/O port
For the output specification when the I/O ports P00–P03 and P10–P13 are in the output mode, either
complementary output or P-channel open drain output can be selected in 1-bit units.
Refer to Section 4.7.2, "Mask option", for details.
(9) External reset by simultaneous high input to the input port (K00–K03)
This function resets the IC when several keys are pressed simultaneously. The mask option is used to
select whether this function is used or not. Further when the function is used, a combination of the
input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected.
Refer to Section 2.2.2, "Simultaneous high input to terminals K00–K03", for details.
(10) Time authorize circuit for the simultaneous high input reset function
When the external reset function (shown in 9 above) is used, the time authorize circuit is enabled. The
reset function works only when the input time of simultaneous low is more than the rule time if the
time authorize circuit is being used. When the external reset function is not used, the time authorize
circuit cannot be used. Refer to Section 2.2.2, "Simultaneous high input to terminals K00–K03", for
details.

6EPSON S1C63666 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
(11) Synchronous clock polarity in the serial interface
The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface
is selected by mask option. Either positive polarity or negative polarity can be selected.
Refer to Section 4.12.2, "Mask option", for details.
(12) LCD drive power
Either the internal power supply or an external power supply can be selected for driving LCD.
Refer to Section 4.8.2, "Power supply for LCD driving", for details.
(13) LCD segment specification
The display memory can be allocated to the optional SEG terminal. It is also possible to set the
optional SEG terminal for DC output.
Refer to Section 4.8.5, "Segment option", for details.
<Option list>
The following is the option list for the S1C63666.
Multiple selections are available in each option item as indicated in the option list. Select the specifica-
tions that meet the target system and check the appropriate box. Be sure to record the specifications for
unused functions too.
1. OSC1 SYSTEM CLOCK
■■1. Crystal
2. OSC3 SYSTEM CLOCK
■■1. CR (built-in R)
■■2. CR (external R)
■■3. Ceramic
3. SVD EXTERNAL VOLTAGE DETECTION
■■1. Not Use
■■2. Use
4. INPUT PORT PULL DOWN RESISTOR
• K00 ■■1. With Resistor ■■2. Gate Direct
• K01 ■■1. With Resistor ■■2. Gate Direct
• K02 ■■1. With Resistor ■■2. Gate Direct
• K03 ■■1. With Resistor ■■2. Gate Direct
• K10 ■■1. With Resistor ■■2. Gate Direct
• K11 ■■1. With Resistor ■■2. Gate Direct
• K12 ■■1. With Resistor ■■2. Gate Direct
• K13 ■■1. With Resistor ■■2. Gate Direct
5. RESET PORT PULL DOWN RESISTOR
• RESET ■■1. With Resistor ■■2. Gate Direct
6. I/O PORT PULL DOWN RESISTOR
• P00 ■■1. With Resistor ■■2. Gate Direct
• P01 ■■1. With Resistor ■■2. Gate Direct
• P02 ■■1. With Resistor ■■2. Gate Direct
• P03 ■■1. With Resistor ■■2. Gate Direct
• P10 ■■1. With Resistor ■■2. Gate Direct
• P11 ■■1. With Resistor ■■2. Gate Direct
• P12 ■■1. With Resistor ■■2. Gate Direct
• P13 ■■1. With Resistor ■■2. Gate Direct

S1C63666 TECHNICAL MANUAL EPSON 7
CHAPTER 1: OUTLINE
7. OUTPUT PORT OUTPUT SPECIFICATION
• R00 ■■1. Complementary ■■2. Pch-OpenDrain
• R01 ■■1. Complementary ■■2. Pch-OpenDrain
• R02 ■■1. Complementary ■■2. Pch-OpenDrain
• R03 ■■1. Complementary ■■2. Pch-OpenDrain
• R10 ■■1. Complementary ■■2. Pch-OpenDrain
• R11 ■■1. Complementary ■■2. Pch-OpenDrain
• R12 ■■1. Complementary ■■2. Pch-OpenDrain
• R13 ■■1. Complementary ■■2. Pch-OpenDrain
8. I/O PORT OUTPUT SPECIFICATION
• P00 ■■1. Complementary ■■2. Pch-OpenDrain
• P01 ■■1. Complementary ■■2. Pch-OpenDrain
• P02 ■■1. Complementary ■■2. Pch-OpenDrain
• P03 ■■1. Complementary ■■2. Pch-OpenDrain
• P10 ■■1. Complementary ■■2. Pch-OpenDrain
• P11 ■■1. Complementary ■■2. Pch-OpenDrain
• P12 ■■1. Complementary ■■2. Pch-OpenDrain
• P13 ■■1. Complementary ■■2. Pch-OpenDrain
9. MULTIPLE KEY ENTRY RESET COMBINATION
■■1. Not Use
■■2. Use (K00, K01)
■■3. Use (K00, K01, K02)
■■4. Use (K00, K01, K02, K03)
10. MULTIPLE KEY ENTRY RESETTIME AUTHORIZE
■■1. Not Use
■■2. Use
11. SIO SYNC CLOCK & SRDY
■■1. Negative
■■2. Positive
12. LCD DRIVING POWER
■■1. Internal Power (3.0 V panel)
■■2. External Power 1/3 bias, VDD=VC2 (4.5 V panel)
■■3. External Power 1/3 bias, VDD=VC3 (3.0 V panel)
■■4. External Power 1/2 bias, VDD=VC3, VC1=VC2 (3.0 V panel)

8EPSON S1C63666 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
13. SEGMENT OPTION
<address> H:
L:
D:
RAM data high-order address (0–9)
RAM data low-order address (0–F)
Data bit (0–3)
<Output specification> S:
C:
N:
Segment output
Complementary output
Nch open drain output
Pin
name
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
H L D
COM0
Address (F0xx)
H L D
COM1
H L D
COM2
H L D
COM3
H L D
COM4
H L D
COM5
H L D
COM6
H L D SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
SEG output
■
S
DC output
■
C
■
N
COM7 Output specification

S1C63666 TECHNICAL MANUAL EPSON 9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
The S1C63666 operating power voltage is as follows:
Table 2.1.1 Operating voltage
Operating mode
Normal mode
Halver mode
Normal mode
Maximum operating frequency
4 MHz (OSC3)
32 kHz (OSC1 only)
32 kHz (OSC1 only)
Operating voltage
2.4 V to 3.6 V
2.4 V to 3.6 V
1.5 V to 3.6 V
The S1C63666 operates by applying a single power supply within the above range between VDD and VSS.
The S1C63666 itself generates the voltage necessary for all the internal circuits by the built-in power
supply circuits shown in Table 2.1.2.
Table 2.1.2 Power supply circuits
Circuit
OSC1 circuit
Internal circuits
(low-speed operation)
OSC3 and internal circuits
(high-speed operation)
LCD driver
Power supply
Voltage regulator for
OSC1 oscillation circuit
Low-speed operation
voltage regulator
High-speed operation
voltage regulator
LCD system voltage
circuit
Output voltage
V
OSC
V D1L
V D3
V C1 –V C3
Note: • Do not drive external loads with the output voltage from the internal power supply circuits.
•See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.
External
power
supply
LCD system
voltage regulator
LCD driver
CC
CD
V
DDA
V DD
V D2
V C1
V C2
V C3
CA
CB
V
OSC
V D1
V SS
V SSA
V C1
V C1
V C2
V C3
V D1L
V OSC
V D3
V D2 =1/2 V DD
V D1
Voltage
halver
Voltage booster
LCD system voltage circuit
LPWR
VDC3
VDC2
VDC0
VDC1
Low-speed operation
voltage regulator
Voltage regulator for
OSC1 oscillation circuit
OSC1
oscillation circuit
CPU,
internal circuits
R/f
converter
High-speed operation
voltage regulator
OSC3
oscillation circuit
+
Fig. 2.1.1 Configuration of power supply

10 EPSON S1C63666 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1Voltage regulator for OSC1 oscillation circuit
This voltage regulator generates the VOSC voltage (0.98 V Typ.) for driving the OSC1 oscillation circuit.
This regulator always operates to drive the OSC1 oscillation circuit.
2.1.2 Low-speed operation voltage regulator
The low-speed operation voltage regulator generates the VD1L voltage (1.25 V Typ.) for driving the
internal logic circuits in low-speed mode. This regulator always operates and the output voltage is used
as the operating voltage of the CPU and internal logic circuits when they are driven with the OSC1 clock
(32 kHz).
2.1.3 High-speed operation voltage regulator
The high-speed operation voltage regulator generates the VD3 voltage (2.0 V Typ.) for driving the OSC3
oscillation circuit and the internal logic circuits in high-speed mode. Since this regulator stops normally, it
should be turned it on using software before switching to the high-speed mode. Refer to Section 4.4,
"Oscillation Circuit", for the control method.
2.1.4 Internal operating voltageVD1
The internal operating voltage VD1 is the voltage for driving the CPU and internal logic circuits.
The S1C63666 is designed with twin clock specifications; it has two types of oscillation circuits OSC1 and
OSC3 built-in. Use OSC1 clock for normal operation, and switch to OSC3 using software when high-
speed operation is necessary. When switching the clock, the operating voltage VD1 must be switched
using software to stabilize the operation of the oscillation circuit and internal circuits.
In low-speed operation, VD1L generated by the low-speed operation voltage regulator is used as VD1. In
high-speed operation, VD3 generated by the high-speed operation voltage regulator is used as VD1.
Refer to Section 4.4, "Oscillation Circuit", for the control method.
2.1.5 LCD system voltage circuit
The LCD system voltage circuit generates the LCD drive voltage. This circuit allows the software to turn
on and off. Turn this circuit on before starting display on the LCD. The LCD system voltage circuit
generates VC1 with the voltage regulator built-in, and generates two other voltages (VC2 = 2VC1, VC3 =
3VC1) by boosting VC1. The VC1 voltage value can be adjusted using software in 16 steps (0.95 to 1.40 V).
The LCD system voltage regulator can be disabled by mask option. In this case, external elements can be
minimized because the external capacitors for the LCD system voltage regulator are not necessary.
However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when
the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used.
Figure 2.1.5.1 shows the external element configuration when the LCD system voltage regulator is not
used.