Epson S5U13513P00C100 User manual

Revision 1.1
S1D13513 Display Controller
S5U13513P00C100 Evaluation Board
User Manual
Document Number: X78A-G-003-01
Status: Revision 1.1
Issue Date: 2010/09/06
© SEIKO EPSON CORPORATION 2006-2010. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.2 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.3 S1D13513 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4.1 Connecting to the Epson S5U13U00P00C100 USB Adapter Board . . . . . . . . . 15
4.4.2 Connecting to the Epson PC Card Extender Board . . . . . . . . . . . . . . . . . . 15
4.4.3 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 YUV Output for TV Display . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Keypad Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9 PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 GPIO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 S5U13513P00C100 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1 EPSON Display Controllers (S1D13513) . . . . . . . . . . . . . . . . . . . . 31
9.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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1 Introduction
This manual describes the setup and operation of the S5U13513P00C100 Evaluation
Board. The evaluation board is designed as an evaluation platform for the S1D13513
Display Controller.
The S5U13513P00C100 evaluation board can connect to the S5U13U00P00C100 USB
Adapter board so that it can be used with a laptop or desktop computer, via USB 2.0. With
some minor modifications, it is possible to connect the S5U13513P00C100 evaluation
board to a Epson PC Card Extender board instead of a USB Adapter board. The
S5U13513P00C100evaluationboardcan alsobe usedwithmanyother nativeplatformsvia
the host connectors which provide the appropriate signals to support a variety of CPUs.
This user manual is updated as appropriate. Please check the Epson Research and Devel-
opment Website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
documentati[email protected].

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2 Features
The S5U13513P00C100 Evaluation Board includes the following features:
• 256-pin PBGA S1D13513 Display Controller
• On-board SDRAM, selectable as 8MB x 32-bit or 8MB x 16-bit
• Headers for connection to the S5U13U00P00C100 USB Adapter board or to the PC
Card Extender board
• Headers for connecting to various Host Bus Interfaces
• Headers for connecting to LCD panels
• Headers for connecting to cameras
• On-board 10MHz crystal (used for OSC1 clock input)
• On-board 27MHz crystal (used for OSC2 clock input)
• 14-pin DIP socket (used to install an oscillator for CLKI3 clock input)
• 3.3V input power
• On-board voltage regulator with 1.8V output

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3 Installation and Configuration
The S5U13513P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm
resistors which allow it to be used with a variety of different configurations.
3.1 Configuration DIP Switch
The S1D13513 has configuration inputs (CNF[8:0]) which are read on the rising edge of
RESET#. A 10-position DIP switch (SW1) is used to configure the S1D13513 for multiple
Host Bus Interfaces. The following figure shows the location of DIP switch SW1 on the
S5U13513P00C100.
Figure 3-1: Configuration DIP Switch (SW1) Location
All S1D13513 configuration inputs (CNF[8:0]) are fully configurable using DIP switch
SW1 as described below.
Table 3-1: Summary of Power-On/Reset Options
SDU13513B00C
SW1-[10:1] Config S1D13513 CNF[8:0] Config Power-On/Reset State
1 (ON) 0 (OFF)
SW1-[10] - Not used
SW1-[9:8] CNF[8:7]
00b CLKI3 is the PLL1 clock source
01b BUSCLK is the PLL1 clock source
10b OSC1 is the PLL1 clock source
11b OSC2 is the PLL1 clock source
SW1-[6] CNF5 Indirect access Direct access
SW1-[7] CNF6 See Table 3-2: “CNF[4:0] Setting
for CNF[6] = 1b” See Table 3-3: “CNF[4:0] Setting for CNF[6] = 0b”
SW1-[5:1] CNF[4:0] 00000b Parallel Direct 80 Type 2: 1CS#
(see Table 3-2: “CNF[4:0] Setting for CNF[6] = 1b” )
= Required settings when using S5U13U00P00C100 USB Adapter board (SW1-[9:1] = 101000000b)
DIP SWITCH - SW1

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Table 3-2: CNF[4:0] Setting for CNF[6] = 1b
CNF[4:0] Host Bus
00000b Parallel Direct 80 Type 2: 1 CS#
00001b Reserved
00010b Parallel Indirect 80 Type 2
00011b Reserved
00100b Parallel Direct 80 Type 1: 1 CS#
00101b Parallel Direct 68: 1 CS#
00110b Parallel Indirect 80 Type 1
00111b Parallel Indirect 68
01000b Parallel Direct 80 Type 2: 2 CS#
01001b Reserved
01010b Reserved
01011b Reserved
01100b Parallel Direct 80 Type 1: 2 CS#
01101b Parallel Direct 68: 2 CS#
01110b Reserved
01111b Reserved
10000b Serial on HVDD1: Data valid on falling edge
10001b Serial on HVDD2: Data valid on falling edge
10010b Reserved
10011b Reserved
10100b Reserved
10101b Reserved
10110b Reserved
10111b Reserved
11000b Serial on HVDD1: Data valid on rising edge
11001b Serial on HVDD2: Data valid on rising edge
11010b Reserved
11011b Reserved
11100b Reserved
11101b Reserved
11110b Reserved
11111b Reserved
= Required settings when using S5U13U00P00C100 USB Adapter board
(SW1-[9:1] = 101000000b)

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Table 3-3: CNF[4:0] Setting for CNF[6] = 0b
CNF[4:0] Host Bus
00000b Generic Little Endian: Active Low WAIT# with tri-state
00001b Generic Little Endian: Active Low WAIT# always driven
00010b Generic Little Endian: Active HIgh WAIT# with tri-state
00011b Reserved
00100b Generic Big Endian: Active Low WAIT# with tri-state
00101b Generic Big Endian: Active Low WAIT# always driven
00110b Generic Big Endian: Active HIgh WAIT# with tri-state
00111b Reserved
01000b MIPS/ISA Little Endian: Active Low WAIT# with tri-state
01001b MIPS/ISA Little Endian: Active Low WAIT# always driven
01010b MIPS/ISA Little Endian: Active HIgh WAIT# with tri-state
01011b Reserved
01100b MC68000 Big Endian: Active High WAIT# with tri-state
01101b Reserved
01110b MC68030 Big Endian: Active High WAIT# with tri-state
01111b Reserved
10000b PR31500/31700/TX3912 Little Endian: Active Low WAIT# with tri-state
(16-bit memory accesses only)
10001b PR31500/31700/TX3912 Little Endian: Active Low WAIT# always driven
(16-bit memory accesses only)
10010b Reserved
10011b Reserved
10100b Reserved
10101b Reserved
10110b MPC821/555/556 Big Endian: Active High WAIT# with tri-state
10111b Reserved
11000b SH3 Little Endian: Active Low WAIT# with tri-state
11001b SH3 Little Endian: Active Low WAIT# always driven
11010b SH4 Little Endian: Active High WAIT# with tri-state
11011b Reserved
11100b SH3 Big Endian: Active Low WAIT# with tri-state
11101b SH3 Big Endian: Active Low WAIT# always driven
11110b SH4 Big Endian: Active High WAIT# with tri-state
11111b Reserved

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3.2 Configuration Jumpers
The S5U13513P00C100 has 11 jumperblocks which configure various board settings. The
jumper positions for each function are shown below.
Table 3-4: Configuration Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 COREVDD Normal — COREVDD current
measurement
JP2 PLLVDD1 Normal — PLLVDD1 current
measurement
JP3 PLLVDD2 Normal — PLLVDD2 current
measurement
JP4 OSCVDD1 Normal — OSCVDD1 current
measurement
JP5 OSCVDD2 Normal — OSCVDD2 current
measurement
JP6 HVDD1 Normal — HVDD1 current
measurement
JP7 HVDD2 Normal — HVDD2 current
measurement
JP8 HVDD3 Normal — HVDD3 current
measurement
JP9 HVDD4 Normal — HVDD4 current
measurement
JP10 HVDD5 Normal — HVDD5 current
measurement
JP11 SDRAM Width Select 32-bit wide SDRAM 16-bit wide SDRAM —

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JP1-JP10 - Power Supplies for the S1D13513
JP1-JP10 can be used to measure current consumption of each S1D13513 power supply.
When the jumper is at position 1-2, normal operation is selected.
When no jumper is installed, the current consumption for each power supply can be
measured by connecting an ammeter to pin 1 and 2 of the jumper.
The jumper associated to each power supply is as follows:
JP1 for COREVDD
JP2 for PLLVDD1
JP3 for PLLVDD2
JP4 for OSCVDD1
JP5 for OSCVDD2
JP6 for HVDD1 (Host interface)
JP7 for HVDD2 (LCD Panel interface)
JP8 for HVDD3 (Camera2 interface)
JP9 for HVDD4 (Camera1 interface)
JP10 for HVDD5 (SDRAM interface)
Figure 3-2: Configuration Jumper Locations (JP1-JP10)
JP10
JP1
JP8
JP9
JP7
JP6
JP4
JP5
JP2
JP3

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JP11 - SDRAM Width Select
JP11 is used to select the bus width of the external SDRAM.
When the jumper is at position 1-2, the external SDRAM is 32-bit wide and memory size
is 32MB. The memory consists of 2 chips in parallel, each 16MB and 16-bit wide.
When the jumper is at position 2-3, the external SDRAM is 16-bit wide and memory size
is 16MB. In this position one memory chip is disabled and only one chip is active (16MB
and 16-bit wide).
Figure 3-3: Configuration Jumper Location (JP11)
JP11

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4 Technical Description
4.1 Power
4.1.1 Power Requirements
The S5U13513P00C100 evaluation board requires an external regulated power supply
(3.3V at 1A). The power is supplied to the evaluation board through pin 5 of the P2 header,
or pin 29 of the H2 header.
The green LED ‘3.3V Power’ is turned on when 3.3V power is applied to the board.
4.1.2 Voltage Regulators
The S5U13513P00C100 evaluation board has an on-board linear regulator to provide the
1.8V power required by the S1D13513 Display Controller.
Additionally, there is a step-up switching voltage regulator to generate 6~24V. This output
is adjustable and can be used to power the LED backlight on some LCD panels.
4.1.3 S1D13513 Power
The S1D13513 Display Controller requires 1.8V and 3.3V power supplies.
1.8V power is provided by the on-board linear voltage regulator. It is used for CoreVDD,
PLLVDD1, PLLVDD2, OSCVDD1, OSCVDD2.
3.3V power must be provided by the external power supply. It is used for HVDD1 (host
interface - HIOVDD), HVDD2 (LCD panel interface - PIOVDD), HVDD3 (camera 2
interface - CIOVDD2), HVDD4 (camera 1 interface - CIOVDD1), and HVDD5 (SDRAM
interface).
HIOVDD is connected to 3.3V through a 0 ohm resistor, R31. If it is desired to have a
different voltage for HIOVDD, R31 must be removed and the desired supply connected to
pin 11 of connector P1.
PIOVDD is connected to 3.3V through a 0 ohm resistor, R33. If it is desired to have a
different voltage for PIOVDD, R33 must be removed and the desired supply connected to
pin 32 of connector H4.
CIOVDD2 is connected to 3.3V through a 0 ohm resistor, R34. If it is desired to have a
different voltage for CIOVDD2, R34 must be removed and the desired supply connected to
pin 15 of connector H7.

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CIOVDD1 is connected to 3.3V through a 0 ohm resistor, R70. If it is desired to have a
different voltage forCIOVDD1, R70 must be removed and the desiredsupply connected to
pin 15 of connector H6.
HVDD5 is always connected to 3.3V.
Note
The recommended range for HVDD1 (HIOVDD), HVDD2 (PIOVDD), HVDD3
CIOVDD2), and HVDD4 (CIOVDD1) is 3.0V~3.6V.
4.2 Clocks
S1D13513 has four clock inputs: BUSCLK, OSC1, OSC2 and CLKI3. BUSCLK and
CLKI3 require a clock provided by an external oscillator. OSC1 and OSC2 have an internal
oscillator and can work with a crystal or with an external oscillator.
For the S5U13513P00C100 evaluation board, OSC1 and OSC2 use crystals (10MHz for
OSC1 and 27MHz for OSC2).
For theS5U13513P00C100 evaluation board, CLKI3 is not used and ispulled to ground by
a 10kΩresistor. However, if CLKI3 is required, connect a 14-pin, DIP package oscillator
in the Y1 footprint.
For the S5U13513P00C100 evaluation board, BUSCLK is not used and is pulled to ground
by a 10kΩresistor. However, if BUSCLK is required,the BUSCLK pin is connected to the
H2 connector and to the P1 connector where it may be provided by the host development
platform.
4.3 Reset
The S5U13513P00C100 evaluation board can be reset using a push-button, or via an active
low reset signal from the host development platform (see H2 connector or P1 connector).
The reset signal will reset the S1D13513 Display Controller and is available on the H6 and
H7 connectors. It is possible to remove the reset signal from the H6 and H7 connectors by
removing the 0 Ohm resistor R80 from the board.

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4.4 Host Interface
4.4.1 Connecting to the Epson S5U13U00P00C100 USB Adapter Board
The S5U13513P00C100 evaluation board is designed to connect to a S5U13U00P00C100
USB Adapter Board.The USB adapterboard providesa simple connection to anycomputer
via a USB 2.0 connection. The S5U13513P00C100 directly connects to the adapter board
through connectors P1 and P2. The USB adapter board also supplies the 3.3V power
required by the S5U13513P00C100.
4.4.2 Connecting to the Epson PC Card Extender Board
The S5U13513P00C100 evaluation board may be connected to an Epson PCCard Extender
Board, but it will require an external 3.3V power supply and some modifications to the
S5U13513P00C100 board.
The modifications required for the S5U13513P00C100 board are:
1. Remove R107 and R108 (0 ohm resistors, size 0603)
2. Remove R109 and R112 (0 ohm resistors, size 0402)
3. Populate R110 and R111 with 0 ohm resistors, size 0402 (or short the pads on the
board)
4. Set DIP switch SW1-[5:1] to 00100b (CNF[4:0]=00100b) to select Parallel Direct 80
Type 1: 1CS# host interface
To use a modified S5U13513P00C100 with an Epson PC Card Extender board:
1. Connect the 2 boards using connectors P1 and P2.
2. Connect 3.3V power supply to the S5U13513P00C100. Connect the positive of the
power supply to test point TP3.3VDD1, and the negative to test point TPGND2
3. Plug the PC Card Extender (with S5U13513P00C100 connected to it) into a PC Card
slot on a PC.
4. Turn on the 3.3V power supply and the S5U13513P00C100 is ready to use. Note that
a windows driver is required to be installed on the PC (the S1D13xxx PCI/PC Card
Bus driver is available from www.erd.epson.com).

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4.4.3 Direct Host Bus Interface Support
The S1D13513 Display Controller directly supports many host bus interfaces. For detailed
S1D13513 pin mapping, refer to the S1D13513 Hardware Functional Specification,
document number X78B-A-001-xx.
All S1D13513 host interface pins are available on connectors H2 and H3 which allow the
S5U13513P00C100 to be connected to a variety of development platforms. However,
connectors H2 and H3 are not populated on the S5U13513P00C100 evaluation board.
If connectors H2 and H3 are added, all host interface signals must match HVDD1 of the
S1D13513. For the maximum/minimum values of the voltages, refer to the S1D13513
Hardware Functional Specification, document number X78B-A-001-xx.
The following diagram shows the location of the host bus connectors, H2 and H3. They are
0.1x0.1” 34-pin headers (17x2).
Figure 4-1: Host Bus Connector Locations (H2 and H3)
For the pinout of connectors H2 and H3, see “Schematic Diagrams” on page 24.
H2
H3

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4.5 LCD Panel Interface
The LCD interface signals are available on connectors H4 and H5. Connector H5 includes
GPIOG[4:0] which may be used as additional signals for extended TFT interfaces. For
S1D13513 LCD interface pin mapping, referto the S1D13513 HardwareFunctional Speci-
fication, document number X78B-A-001-xx.
Connectors H4 and H5 are both 0.1x0.1” 40-pin headers (20x2). For the pinout of
connectors H4 and H5, see “Schematic Diagrams” on page 24.
On the evaluation board there is an adjustable 6~24V, 40mA max. power supply. This
voltage is provided only on connector H4 (it is not used elsewhere on the board). It is
intended for use to power the LED backlight on some LCD panels. The voltage is adjusted
by the R106 pot.
Note
For LCD panels that use CCFL backlight, an external power supply must be used to pro-
vide power to the inverter for CCFL backlight. Usually, the inverter current consump-
tion is higher than the maximum 40mA current available from the on-board voltage
regulator.
The following diagram shows the location of the LCD panel connectors H4 and H5.
Figure 4-2: LCD Panel Connectors Locations (H4, H5)
H5
H4

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4.6 Camera Interface
All the signals for the Camera1 interface are available on connector H6. All the signals for
the Camera2 interface are available on connector H7. H6 and H7 are 0.1x0.1” 20-pin
headers (10x2). For the pinout of connectors H6 and H7, see “Schematic Diagrams” on
page 24.
The S1D13513 Camera1 interface signals use the GPIOC[7:0] and GPIOD[3:0] pins. The
Camera2 interface signals use the GPIOA[7:0] and GPIOB[7:0] pins. These GPIO pins
may be configured for a variety of S1D13513 supported functions. GPIOC[7:0] and
GPIOD[3:0] may be configured as GPIO pins, Camera1 interface pins, or as YUV output
pins. GPIOA[7:0] and GPIOB[7:0] may be configured as GPIO pins, Camera2 interface
pins, Keypad interface pins, or PWM output pins. For detailed S1D13513 GPIO pin
mapping, refer to the S1D13513 Hardware Functional Specification, document number
X78B-A-001-xx.
Connector H6 and H7 may be used to evaluate any function for which the GPIOA[7:0],
GPIOB[7:0], GPIOC[7:0], GPIOD[3:0] can be configured.
The S1D13513 has an I2C interface which uses two signals that are connected to both the
H6 and H7 connectors. The default configuration of the evaluation board has the I2C
signals, I2C_SCL and I2C_SDA, pulled high to CIOVDD1. If the I2C signals must be
pulled high to CIOVDD2, R162 and R175 must be removed and 4.7kΩresistors must be
mounted for R164 and R177.
The reset signal provided on H6 and H7 is active low and is pulled to HIOVDD when
inactive.
The following diagram shows the location of the camera connectors H6 and H7.
Figure 4-3: Camera Expansion Connector Locations (H6, H7)
H6
H7

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4.7 YUV Output for TV Display
The S1D13513 can output YUV data which can be used to display an image on a TV screen
via an external video encoder. The YUV output is multiplexed with other functions on the
GPIOC[7:0] and GPIOD[2:0] pins. These pins are routed to connector H6.
4.8 Keypad Interface
The S1D13513 has a 5x5 keypad interface which is multiplexed with other functions on the
GPIOA[4:0] and GPIOB[4:0] pins. These pins are routed to connectors H6 and H7. It is
possible to use a Keypad device with the S5U13513P00C100 evaluation board by
connecting it to the H6 and H7 connectors.
4.9 PWM Outputs
The S1D13513 has 4 PWM outputs which may be used to control the brightness of 4 LEDs.
It also has an input, AUDIN, which is used to control the overall operation of the PWM
outputs. The PWM output function is multiplexed on the GPIOA[7:5] and GPIOB[7] pins.
AUDIN is multiplexed on the GPIOD[3] pin. These pins are routed to connector H6 and
H7.
4.10 GPIO Connections
The S1D13513 Display Controller GPIO pins have multiple functions. All the GPIO pins
are routed to the connectors on the S5U13513P00C100 evaluation board. If any pin is
configured as a GPIO, it will be available on the connectors as listed below:
GPIOA[7:0] pins are routed to connector H7.
GPIOB[7:5] and GPIOB[3:0] pins are routed to connector H7. GPIOB[6:5] are also routed
to connector H6.
GPIOB[4] pin is routed to connector H6.
GPIOC[7:0] pins are routed to connector H6.
GPIOD[3:0] pins are routed to connector H6.
GPIOG[4:0] pins are routed to connector H5.
FPDAT[23:18] which may be used as GPIOH[5:0] are routed to connector H5.

Page 20 Epson Research and Development
Vancouver Design Center
S1D13513 S5U13513P00C100 Evaluation Board User Manual
X78A-G-003-01 Issue Date: 2010/09/06
Revision 1.1
4.11 JTAG Connector
The S1D13513 design includes a JTAG interface. All the JTAG signals are available on
connector H1, however, connector H1 is not populated on the board. For the pinout of
connector H1, see “Schematic Diagrams” on page 24.
The following diagram shows the location of the JTAG connector (H1).
Figure 4-4: JTAG Connector Location
H1