Espressif Systems ESP32-S3 Instruction Manual

ESP32-S3
Hardware Design Guidelines
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Dec 25, 2023

Table of contents
Table of contents i
1 About This Document 3
1.1 Introduction .............................................. 3
1.2 Latest Version of This Document ................................... 3
2 Product Overview 5
3 Schematic Checklist 7
3.1 Power Supply ............................................. 9
3.1.1 Digital Power Supply .................................... 9
3.1.2 Analog Power Supply .................................... 9
3.1.3 RTC Power Supply ..................................... 11
3.2 Chip Power-up and Reset Timing .................................. 11
3.3 Flash and PSRAM .......................................... 13
3.3.1 In-Package Flash and PSRAM ............................... 13
3.3.2 O󰝗-Package Flash and PSRAM ............................... 14
3.4 Clock Source ............................................. 14
3.4.1 External Crystal Clock Source (Compulsory) ........................ 14
3.4.2 RTC Clock Source (Optional) ................................ 15
3.5 RF .................................................. 16
3.5.1 RF Circuit .......................................... 16
3.5.2 RF Tuning .......................................... 16
3.6 UART ................................................ 18
3.7 Strapping Pins ............................................ 18
3.8 GPIO ................................................. 19
3.9 ADC ................................................. 22
3.10 SDIO ................................................. 22
3.11 USB .................................................. 22
3.12 Touch Sensor ............................................. 23
4 PCB Layout Design 25
4.1 General Principles of PCB Layout .................................. 25
4.2 Positioning a Module on a Base Board ................................ 26
4.3 Power Supply ............................................. 28
4.3.1 General Guidelines ..................................... 28
4.3.2 3.3 V Power Layout ..................................... 28
4.3.3 Analog Power Layout .................................... 29
4.4 Crystal ................................................ 29
4.5 RF .................................................. 31
4.6 Flash and PSRAM .......................................... 31
4.7 UART ................................................ 33
4.8 USB .................................................. 34
4.9 SDIO ................................................. 34
4.10 Touch Sensor ............................................. 34
4.10.1 Electrode Pattern ...................................... 35
4.10.2 PCB Layout ......................................... 35
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4.10.3 Waterproof and Proximity Sensing Design ......................... 36
4.11 Typical Layout Problems and Solutions ................................ 36
4.11.1 1. The voltage ripple is not large, but the TX performance of RF is rather poor. . . . . . . 36
4.11.2 2. When ESP32-S3 sends data packages, the voltage ripple is small, but RF TX perfor-
mance is poor. ........................................ 37
4.11.3 3. When ESP32-S3 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. ..................... 37
4.11.4 4. TX performance is not bad, but the RX sensitivity is low. ................ 38
5 Hardware Development 39
5.1 ESP32-S3 Modules .......................................... 39
5.2 ESP32-S3 Development Boards ................................... 39
5.3 Download Guidelines ......................................... 39
6 Related Documentation and Resources 41
7 Glossary 43
8 Revision History 45
8.1 ESP Hardware Design Guidelines v1.0 ................................ 45
9 Disclaimer and Copyright Notice 47
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Table of contents
This document provides guidelines for the ESP32-S3 SoC.
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Table of contents
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Chapter 1
About This Document
1.1 Introduction
The hardware design guidelines advise on how to integrate ESP32-S3 into a product. These guidelines will help to
achieve optimal performance of your product, ensuring technical accuracy and adherence to Espressif’s standards.
The guidelines are intended for hardware and application engineers.
The document assumes that you possess a certain level of familiarity with the ESP32-S3 SoC. In case you lack prior
knowledge, we recommend utilizing this document in conjunction with the ESP32-S3 Series Datasheet.
1.2 Latest Version of This Document
Check the link to make sure that you use the latest version of this document: https://docs.espressif.com/projects/
esp-hardware-design-guidelines/en/latest/esp32s3/index.html
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Chapter 1. About This Document
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Chapter 2
Product Overview
ESP32-S3 is a system on a chip that integrates the following features:
• Wi-Fi (2.4 GHz band)
• Bluetooth® 5 (LE)
• Dual high-performance Xtensa® 32-bit LX7 CPU cores
• Ultra Low Power coprocessor running either RISC-V or FSM core
• Multiple peripherals
• Built-in security hardware
• USB OTG interface
• USB Serial/JTAG Controller
Powered by 40 nm technology, ESP32-S3 provides a robust, highly-integrated platform, which helps meet the con-
tinuous demands for e󰝚cient power usage, compact design, security, high performance, and reliability. Typical
application scenarios for ESP32-S3 include:
• Smart Home
• Industrial Automation
• Health Care
• Consumer Electronics
• Smart Agriculture
• POS Machines
• Service Robot
• Audio Devices
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers
• Cameras for Video Streaming
• USB Devices
• Speech Recognition
• Image Recognition
• Wi-Fi + Bluetooth Networking Card
• Touch and Proximity Sensing
For more information about ESP32-S3, please refer to ESP32-S3 Series Datasheet.
Note: Unless otherwise speci󰝘ed, “ESP32-S3”used in this document refers to the series of chips, instead of a
speci󰝘c chip variant.
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Chapter 2. Product Overview
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Chapter 3
Schematic Checklist
The integrated circuitry of ESP32-S3 requires only 20 electrical components (resistors, capacitors, and inductors)
and a crystal, as well as an SPI 󰝙ash. The high integration of ESP32-S3 allows for simple peripheral circuit design.
This chapter details the schematic design of ESP32-S3.
The following 󰝘gure shows a reference schematic design of ESP32-S3. It can be used as the basis of your schematic
design.
Fig. 1: ESP32-S3 Reference Schematic
Note that Figure ESP32-S3 Reference Schematic shows the connection for 3.3 V, quad, o󰝗-package SPI 󰝙ash/PSRAM.
• In cases where 1.8 V or 3.3 V, octal, in-package or o󰝗-package SPI 󰝙ash/PSRAM is used, GPIO33 ~ GPIO37
are occupied and cannot be used for other functions.
• If an in-package SPI 󰝙ash/PSRAM is utilized, where VDD_SPI is set at either 1.8 V or 3.3 V, GPIO45 will no
longer have any impact. In these scenarios, the presence of R1 is optional. However, in all other cases, refer to
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Chapter 3. Schematic Checklist
Table IO Pad Status After Chip Initialization in the USB-OTG Download Boot Mode to determine whether R1
should be populated or not.
• The connection for 1.8 V, octal, o󰝗-package 󰝙ash/PSRAM is as shown in Figure ESP32-S3 Schematic for
O-Package 1.8 V Octal Flash/PSRAM.
• When only in-package 󰝙ash/PSRAM is used, there is no need to populate the resistor on the SPI traces or to
care the SPI traces.
Fig. 2: ESP32-S3 Schematic for O󰝗-Package 1.8 V Octal Flash/PSRAM
Any basic ESP32-S3 circuit design may be broken down into the following major building blocks:
•Power supply
•Chip power-up and reset timing
•Flash and PSRAM
•Clock source
•RF
•UART
•Strapping pins
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•GPIO
•ADC
•SDIO
•USB
•Touch sensor
The rest of this chapter details the speci󰝘cs of circuit design for each of these sections.
3.1 Power Supply
The general recommendations for power supply design are:
• When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is
no less than 500 mA.
• It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32-S3 Series Datasheet > Section Power Supply.
3.1.1 Digital Power Supply
ESP32-S3 has pin46 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 3.0 V ~ 3.6 V.
It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
Pin VDD_SPI can serve as the power supply for the external device at either 1.8 V or 3.3 V (default). It is recom-
mended to add extra 0.1 μF and 1 μF decoupling capacitors close to VDD_SPI.
• When VDD_SPI operates at 1.8 V, it is powered by ESP32-S3’s internal LDO. The typical current this LDO
can o󰝗er is 40 mA.
• When VDD_SPI operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 14 Ω resistor, therefore,
there will be some voltage drop from VDD3P3_RTC.
Attention: When using VDD_SPI as the power supply pin for in-package or o󰝗-package 3.3 V 󰝙ash/PSRAM,
the supply voltage should be 3.0 V or above, so as to meet the requirements of 󰝙ash/PSRAM’s working voltage.
Depending on the value of EFUSE_VDD_SPI_FORCE, the VDD_SPI voltage can be controlled in two ways, as
Table VDD_SPI Voltage Control shows.
Table 1: VDD_SPI Voltage Control
EFUSE_VDD_SPI_FORCEGPIO45 EFUSE_VDD_SPI_FORCEVolt-
age
VDD_SPI Power Source
0 0 Ignored 3.3 V VDD3P3_RTC via RSPI (de-
fault)
0 1 Ignored 1.8 V Flash Voltage Regulator
1 Ignored 0 1.8 V Flash Voltage Regulator
1 Ignored 1 3.3 V VDD3P3_RTC via RSPI
VDD_SPI can also be driven by an external power supply.
The schematic for the digital power supply pins is shown in Figure ESP32-S3 Schematic for Digital Power Supply Pins.
3.1.2 Analog Power Supply
ESP32-S3’s VDDA and VDD3P3 pins are the analog power supply pins, working at 3.0 V ~ 3.6 V.
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Fig. 3: ESP32-S3 Schematic for Digital Power Supply Pins
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For VDD3P3, when ESP32-S3 is transmitting signals, there may be a sudden increase in the current draw, causing
power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work
in conjunction with the 1 μF capacitor(s).
It is suggested to add an extra 10 μF capacitor at the power entrance. If the power entrance is close to VDD3P3, then
two 10 μF capacitors can be merged into one.
Add a LC circuit on the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is
preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32-S3 Schematic
for Analog Power Supply Pins.
Fig. 4: ESP32-S3 Schematic for Analog Power Supply Pins
3.1.3 RTC Power Supply
ESP32-S3’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling
capacitor near this power pin in the circuit.
Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32-S3 Schematic for RTC Power Supply Pin.
3.2 Chip Power-up and Reset Timing
ESP32-S3’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low.
When ESP32-S3 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU
is pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been
brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused
by external interferences, make the CHIP_PU trace as short as possible.
Figure ESP32-S3 Power-up and Reset Timing shows the power-up and reset timing of ESP32-S3.
Table Description of Timing Parameters for Power-up and Reset provides the speci󰝘c timing requirements.
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Fig. 5: ESP32-S3 Schematic for RTC Power Supply Pin
Fig. 6: ESP32-S3 Power-up and Reset Timing
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Table 2: Description of Timing Parameters for Power-up and Reset
Parameter Description Minimum (µs)
tSTBL Time reserved for the power rails to stabilize before the CHIP_PU
pin is pulled high to activate the chip
50
tRST Time reserved for CHIP_PU to stay below VIL_nRST to reset the
chip
50
Attention:
• CHIP_PU must not be left 󰝙oating.
• To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, speci󰝘c
parameters should be adjusted based on the characteristics of the actual power supply and the power-up
and reset timing of the chip.
• If the user application has one of the following scenarios:
–Slow power rise or fall, such as during battery charging.
–Frequent power on/o󰝗 operations.
–Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being
unable to boot correctly. In this case, additional designs need to be added, such as:
–Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0
V.
–Implementing reset functionality through a button or the main controller.
3.3 Flash and PSRAM
ESP32-S3 requires in-package or o󰝗-package 󰝙ash to store application 󰝘rmware and data. In-package PSRAM or
o󰝗-package RAM is optional.
3.3.1 In-Package Flash and PSRAM
The tables list the pin-to-pin mapping between the chip and in-package 󰝙ash/PSRAM. Please note that the following
chip pins can connect at most one 󰝙ash and one PSRAM. That is to say, when there is only 󰝙ash in the package, the
pin occupied by 󰝙ash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM,
the pin occupied by PSRAM can only connect 󰝙ash; when there are both 󰝙ash and PSRAM, the pin occupied cannot
connect any more 󰝙ash or PSRAM.
Table 3: Pin-to-Pin Mapping Between Chip and In-Package Quad SPI
Flash
ESP32-S3FN8/ESP32-S3FH4R2 In-Package Flash (Quad SPI)
SPICLK CLK
SPICS0 CS#
SPID DI
SPIQ DO
SPIWP WP#
SPIHD HOLD#
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Table 4: Pin-to-Pin Mapping Between Chip and In-Package Quad SPI
PSRAM
ESP32-S3R2/ESP32-S3FH4R2 In-Package PSRAM (2 MB, Quad SPI)
SPICLK CLK
SPICS1 CE#
SPID SI/SIO0
SPIQ SO/SIO1
SPIWP SIO2
SPIHD SIO3
Table 5: Pin-to-Pin Mapping Between Chip and In-Package Octal SPI
PSRAM
ESP32-S3R8/ESP32-S3R8V In-Package PSRAM (8 MB, Octal SPI)
SPICLK CLK
SPICS1 CE#
SPID DQ0
SPIQ DQ1
SPIWP DQ2
SPIHD DQ3
GPIO33 DQ4
GPIO34 DQ5
GPIO35 DQ6
GPIO36 DQ7
GPIO37 DQS/DM
3.3.2 O-Package Flash and PSRAM
ESP32-S3 supports up to 1 GB o󰝗-package 󰝙ash and 1 GB o󰝗-package RAM. If VDD_SPI is used to supply power,
make sure to select the appropriate o󰝗-package 󰝙ash and RAM according to the power voltage on VDD_SPI (1.8
V/3.3 V). It is recommended to add a zero-ohm series resistor on the SPI communication lines to lower the driving
current, reduce interference to RF, adjust timing, and better shield from interference.
3.4 Clock Source
ESP32-S3 supports two external clock sources:
•External crystal clock source (Compulsory)
•RTC clock source (Optional)
3.4.1 External Crystal Clock Source (Compulsory)
The ESP32-S3 󰝘rmware only supports 40 MHz crystal.
The circuit for the crystal is shown in Figure ESP32-S3 Schematic for External Crystal. Note that the accuracy of the
selected crystal should be within ±10 ppm.
Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an
inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should
be adjusted after an overall test.
The initial values of external capacitors C1 and C4 can be determined according to the formula:
CL=C1×C4
C1 + C4+Cstray
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Fig. 7: ESP32-S3 Schematic for External Crystal
where the value of CL(load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the
PCB’s stray capacitance. The values of C1 and C4 need to be further adjusted after an overall test as below:
1. Select TX tone mode using the Certi󰝘cation and Test Tool.
2. Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to
obtain the actual frequency o󰝗set.
3. Adjust the frequency o󰝗set to be within ±10 ppm (recommended) by adjusting the external load capacitance.
• When the center frequency o󰝗set is positive, it means that the equivalent load capacitance is small, and the
external load capacitance needs to be increased.
• When the center frequency o󰝗set is negative, it means the equivalent load capacitance is large, and the external
load capacitance needs to be reduced.
• External load capacitance at the two sides are usually equal, but in special cases, they may have slightly di󰝗erent
values.
Note:
• Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable
performance within the operating temperature range, etc) may lead to the malfunction of ESP32-S3, resulting
in a decrease of the RF performance.
• It is recommended that the amplitude of the crystal is greater than 500 mV.
• When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps men-
tioned above to ensure that the frequency o󰝗set meets the requirements by adjusting capacitors at the two sides
of the crystal.
3.4.2 RTC Clock Source (Optional)
ESP32-S3 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock.
The external RTC clock source enhances timing accuracy and consequently decreases average power consumption,
without impacting functionality.
Figure ESP32-S3 Schematic for 32.768 kHz Crystal shows the schematic for the external 32.768 kHz crystal.
Please note the requirements for the 32.768 kHz crystal:
• Equivalent series resistance (ESR) ≤ 70 kΩ.
• Load capacitance at both ends should be con󰝘gured according to the crystal’s speci󰝘cation.
The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ≤ 10 MΩ). In general, you do not need to
populate the resistor.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
The external signal can be input to the XTAL’s P end through a DC blocking capacitor (about 20 pF). The XTAL’s
N end can be 󰝙oating. Figure ESP32-S3 Schematic for External Oscillator shows the schematic of the external signal.
The signal should meet the following requirements:
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Fig. 8: ESP32-S3 Schematic for 32.768 kHz Crystal
Fig. 9: ESP32-S3 Schematic for External Oscillator
External signal Amplitude (Vpp, unit: V)
Sine wave or square wave 0.6 < Vpp < VDD
3.5 RF
3.5.1 RF Circuit
ESP32-S3’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching
circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements:
• For the RF traces on the PCB board, 50 Ω impedance control is required.
• For the chip matching circuit, it must be placed close to the chip. A CLC structure is preferred.
–The CLC structure is mainly used to adjust the impedance point and suppress harmonics, and
a set of LC can be added if space permits.
–The RF matching circuit is shown in Figure ESP32-S3 Schematic for RF Matching.
• For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic
impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust
the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to
be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.
3.5.2 RF Tuning
The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly.
Follow the instructions below to do RF tuning.
Figure ESP32-S3 RF Tuning Diagram shows the general process of RF tuning.
In the matching circuit, de󰝘ne the port near the chip as Port 1 and the port near the antenna as Port 2. S11 describes
the ratio of the signal power re󰝙ected back from Port 1 to the input signal power, and S21 is used to describe the
transmission loss of signal from Port 1 to Port 2. If S11 is less than or equal to -10 dB and S21 is less than or equal to
-35 dB when transmitting 4.8 GHz and 7.2 GHz signals, the matching circuit can satisfy transmission requirements.
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Fig. 10: ESP32-S3 Schematic for RF Matching
Fig. 11: ESP32-S3 RF Tuning Diagram
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