Espressif Systems ESP32 Series Instruction Manual

ESP32
Hardware Design Guidelines
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Table of contents
Table of contents i
1 About This Document 3
1.1 Introduction .............................................. 3
1.2 Latest Version of This Document ................................... 3
2 Product Overview 5
3 Schematic Checklist 7
3.1 Power Supply ............................................. 8
3.1.1 Digital Power Supply .................................... 8
3.1.2 Analog Power Supply .................................... 9
3.1.3 RTC Power Supply ..................................... 11
3.2 Chip Power-up and Reset Timing .................................. 11
3.3 Flash and PSRAM .......................................... 12
3.3.1 In-Package Flash and PSRAM ............................... 12
3.3.2 O󰝗-Package Flash and PSRAM ............................... 13
3.4 Clock Source ............................................. 13
3.4.1 External Crystal Clock Source (Compulsory) ........................ 13
3.4.2 RTC Clock Source (Optional) ................................ 14
3.5 RF .................................................. 15
3.5.1 RF Circuit .......................................... 15
3.5.2 RF Tuning .......................................... 16
3.6 UART ................................................ 16
3.7 Strapping Pins ............................................ 17
3.8 GPIO ................................................. 18
3.9 ADC ................................................. 19
3.10 External Capacitor .......................................... 19
3.11 SDIO ................................................. 20
3.12 Touch Sensor ............................................. 20
4 PCB Layout Design 21
4.1 General Principles of PCB Layout .................................. 21
4.2 Positioning a Module on a Base Board ................................ 22
4.3 Power Supply ............................................. 23
4.3.1 General Guidelines ..................................... 23
4.3.2 3.3 V Power Layout ..................................... 24
4.3.3 Analog Power Layout .................................... 24
4.3.4 Two-layer PCB Design ................................... 24
4.4 Crystal ................................................ 24
4.5 RF .................................................. 26
4.5.1 RF Layout on Four-layer PCB ................................ 26
4.5.2 RF Layout on Two-layer PCB ................................ 28
4.6 Flash and PSRAM .......................................... 28
4.7 External RC .............................................. 28
4.8 UART ................................................ 29
4.9 SDIO ................................................. 29
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4.10 Touch Sensor ............................................. 30
4.10.1 Electrode Pattern ...................................... 30
4.10.2 PCB Layout ......................................... 30
4.11 Typical Layout Problems and Solutions ................................ 32
4.11.1 1. The voltage ripple is not large, but the TX performance of RF is rather poor. . . . . . . 32
4.11.2 2. When ESP32 sends data packages, the voltage ripple is small, but RF TX performance
is poor. ........................................... 32
4.11.3 3. When ESP32 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. ..................... 32
4.11.4 4. TX performance is not bad, but the RX sensitivity is low. ................ 32
5 Hardware Development 33
5.1 ESP32 Modules ............................................ 33
5.2 ESP32 Development Boards ..................................... 33
5.3 Download Guidelines ......................................... 33
6 Related Documentation and Resources 35
7 Glossary 37
8 Revision History 39
8.1 ESP Hardware Design Guidelines v1.0 ................................ 39
9 Disclaimer and Copyright Notice 41
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Table of contents
This document provides guidelines for the ESP32 SoC.
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Table of contents
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Chapter 1
About This Document
1.1 Introduction
The hardware design guidelines advise on how to integrate ESP32 into a product. These guidelines will help to
achieve optimal performance of your product, ensuring technical accuracy and adherence to Espressif’s standards.
The guidelines are intended for hardware and application engineers.
The document assumes that you possess a certain level of familiarity with the ESP32 SoC. In case you lack prior
knowledge, we recommend utilizing this document in conjunction with the ESP32 Series Datasheet.
1.2 Latest Version of This Document
Check the link to make sure that you use the latest version of this document: https://docs.espressif.com/projects/
esp-hardware-design-guidelines/en/latest/esp32/index.html
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Chapter 1. About This Document
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Chapter 2
Product Overview
ESP32 is a system on a chip that integrates the following features:
• Wi-Fi (2.4 GHz band)
• Bluetooth®
• Dual high-performance Xtensa® 32-bit LX6 CPU cores
• Ultra Low Power coprocessor
• Multiple peripherals
Powered by 40 nm technology, ESP32 provides a robust, highly-integrated platform, which helps meet the continuous
demands for e󰝚cient power usage, compact design, security, high performance, and reliability. Typical application
scenarios for ESP32 include:
• Smart Home
• Industrial Automation
• Health Care
• Consumer Electronics
• Smart Agriculture
• POS Machines
• Service Robot
• Audio Devices
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers
• Cameras for Video Streaming
• Speech Recognition
• Image Recognition
• SDIO Wi-Fi + Bluetooth Networking Card
• Touch and Proximity Sensing
For more information about ESP32, please refer to ESP32 Series Datasheet.
Note: Unless otherwise speci󰝘ed,“ESP32”used in this document refers to the series of chips, instead of a speci󰝘c
chip variant.
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Chapter 2. Product Overview
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Chapter 3
Schematic Checklist
The integrated circuitry of ESP32 requires only 20 electrical components (resistors, capacitors, and inductors) and
a crystal, as well as an SPI 󰝙ash. The high integration of ESP32 allows for simple peripheral circuit design. This
chapter details the schematic design of ESP32.
The following 󰝘gure shows a reference schematic design of ESP32. It can be used as the basis of your schematic
design.
Fig. 1: ESP32 Reference Schematic
Note that Figure ESP32 Reference Schematic shows the connection for quad 3.3 V external 󰝙ash/PSRAM. PSRAM’
s SCLK and 󰝙ash can share the clock from SD_CLK or GPIO17.
• In cases where quad 1.8 V external 󰝙ash/PSRAM is used, R9 should be populated.
• In cases where ESP32-D0WDR2-V3 with in-package quad 3.3 V PSRAM is used, the external 󰝙ash can be
connected as Figure ESP32 Reference Schematic shows.
• In cases where ESP32-U4WDH with in-package quad 3.3 V 󰝙ash is used, the in-package 󰝙ash is connected as
Figure ESP32 Schematic for Quad 3.3 V In-Package Flash shows.
Any basic ESP32 circuit design may be broken down into the following major building blocks:
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Chapter 3. Schematic Checklist
Fig. 2: ESP32 Schematic for Quad 3.3 V In-Package Flash
•Power supply
•Chip power-up and reset timing
•Flash and PSRAM
•Clock source
•RF
•UART
•Strapping pins
•GPIO
•ADC
•External capacitor
•SDIO
•Touch sensor
The rest of this chapter details the speci󰝘cs of circuit design for each of these sections.
3.1 Power Supply
The general recommendations for power supply design are:
• When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is
no less than 500 mA.
• It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32 Series Datasheet > Section Power Supply.
3.1.1 Digital Power Supply
ESP32 has pin37 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 1.8 V ~ 3.6 V. It is
recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
Pin VDD_SDIO can serve as the power supply for the external device at either 1.8 V or 3.3 V (default).
• When VDD_SDIO operates at 1.8 V, it is powered by ESP32’s internal LDO. The maximum current this
LDO can o󰝗er is 40 mA, and the output voltage range is 1.65 V ~ 2.0 V. When the VDD_SDIO outputs 1.8 V,
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it is recommended that users add a 2 kΩ ground resistor and a 4.7 μF ground capacitor close to VDD_SDIO.
See Figure ESP32 Schematic for 1.8 V VDD_SDIO Power Supply Pin.
• When VDD_SDIO operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 6 Ω resistor (internal to
the chip), therefore, there will be some voltage drop from VDD3P3_RTC. When the VDD_SDIO outputs 3.3
V, it is recommended that users add a 1 μF 󰝘lter capacitor close to VDD_SDIO. See Figure ESP32 Schematic
for 3.3 V VDD_SDIO Power Supply Pin.
Attention: When using VDD_SDIO as the power supply pin for in-package or o󰝗-package 3.3 V 󰝙ash/PSRAM,
the supply voltage should be 3.0 V or above, so as to meet the requirements of 󰝙ash/PSRAM’s working voltage.
Fig. 3: ESP32 Schematic for 1.8 V VDD_SDIO Power Supply Pin
Fig. 4: ESP32 Schematic for 3.3 V VDD_SDIO Power Supply Pin
VDD_SDIO can also be driven by an external power supply as shown in Figure ESP32 Schematic for VDD_SDIO Pin
Powered by External Supply.
3.1.2 Analog Power Supply
ESP32’s VDDA and VDD3P3 pins are the analog power supply pins, working at 2.3 V ~ 3.6 V.
For VDD3P3, when ESP32 is transmitting signals, there may be a sudden increase in the current draw, causing
power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work
in conjunction with the 1 μF capacitor(s).
Add a LC circuit on the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is
preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32 Schematic for
Analog Power Supply Pins.
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Fig. 5: ESP32 Schematic for VDD_SDIO Pin Powered by External Supply
Fig. 6: ESP32 Schematic for Analog Power Supply Pins
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3.1.3 RTC Power Supply
ESP32’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling
capacitor near this power pin in the circuit.
Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32 Schematic for RTC Power Supply Pin.
Fig. 7: ESP32 Schematic for RTC Power Supply Pin
3.2 Chip Power-up and Reset Timing
ESP32’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low.
When ESP32 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is
pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been
brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused
by external interferences, make the CHIP_PU trace as short as possible.
Figure ESP32 Power-up and Reset Timing shows the power-up and reset timing of ESP32.
Fig. 8: ESP32 Power-up and Reset Timing
Table Description of Timing Parameters for Power-up and Reset provides the speci󰝘c timing requirements.
Table 1: Description of Timing Parameters for Power-up and Reset
Parameter Description Minimum (µs)
tSTBL Time reserved for the power rails to stabilize before the CHIP_PU
pin is pulled high to activate the chip
50
tRST Time reserved for CHIP_PU to stay below VIL_nRST to reset the
chip
50
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Attention:
• CHIP_PU must not be left 󰝙oating.
• To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, speci󰝘c
parameters should be adjusted based on the characteristics of the actual power supply and the power-up
and reset timing of the chip.
• If the user application has one of the following scenarios:
–Slow power rise or fall, such as during battery charging.
–Frequent power on/o󰝗 operations.
–Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being
unable to boot correctly. In this case, additional designs need to be added, such as:
–Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0
V.
–Implementing reset functionality through a button or the main controller.
3.3 Flash and PSRAM
ESP32 requires in-package or o󰝗-package 󰝙ash to store application 󰝘rmware and data. In-package PSRAM or o󰝗-
package RAM is optional.
3.3.1 In-Package Flash and PSRAM
The tables list the pin-to-pin mapping between the chip and in-package 󰝙ash/PSRAM. Please note that the following
chip pins can connect at most one 󰝙ash and one PSRAM. That is to say, when there is only 󰝙ash in the package, the
pin occupied by 󰝙ash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM,
the pin occupied by PSRAM can only connect 󰝙ash; when there are both 󰝙ash and PSRAM, the pin occupied cannot
connect any more 󰝙ash or PSRAM.
Table 2: Pin-to-Pin Mapping Between Chip and In-Package Flash
ESP32-U4WDH In-Package Flash (4 MB)
SD_DATA_1 IO0/DI
GPIO17 IO1/DO
SD_DATA_0 IO2/WP#
SD_CMD IO3/HOLD#
SD_CLK CLK
GPIO16 CS#
GND VSS
VDD_SDIO VDD
Table 3: Pin-to-Pin Mapping Between Chip and In-Package PSRAM
ESP32-D0WDR2-V3 In-Package PSRAM (2 MB)
SD_DATA_1 SIO0/SI
SD_DATA_0 SIO1/SO
SD_DATA_3 SIO2
SD_DATA_2 SIO3
SD_CLK SCLK
GPIO16 CE#
GND VSS
VDD_SDIO VDD
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3.3.2 O-Package Flash and PSRAM
ESP32 supports up to 16 MB o󰝗-package 󰝙ash and 8 MB o󰝗-package RAM. If VDD_SDIO is used to supply power,
make sure to select the appropriate o󰝗-package 󰝙ash and RAM according to the power voltage on VDD_SDIO (1.8
V/3.3 V). It is recommended to add a zero-ohm series resistor on the SPI communication lines to lower the driving
current, reduce interference to RF, adjust timing, and better shield from interference.
3.4 Clock Source
ESP32 supports two external clock sources:
•External crystal clock source (Compulsory)
•RTC clock source (Optional)
3.4.1 External Crystal Clock Source (Compulsory)
The ESP32 󰝘rmware only supports 40 MHz crystal.
The circuit for the crystal is shown in Figure ESP32 Schematic for External Crystal. Note that the accuracy of the
selected crystal should be within ±10 ppm.
Fig. 9: ESP32 Schematic for External Crystal
Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an
inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should
be adjusted after an overall test.
The initial values of external capacitors C1 and C2 can be determined according to the formula:
CL=C1×C2
C1 + C2+Cstray
where the value of CL(load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the
PCB’s stray capacitance. The values of C1 and C2 need to be further adjusted after an overall test as below:
1. Select TX tone mode using the Certi󰝘cation and Test Tool.
2. Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to
obtain the actual frequency o󰝗set.
3. Adjust the frequency o󰝗set to be within ±10 ppm (recommended) by adjusting the external load capacitance.
• When the center frequency o󰝗set is positive, it means that the equivalent load capacitance is small, and the
external load capacitance needs to be increased.
• When the center frequency o󰝗set is negative, it means the equivalent load capacitance is large, and the external
load capacitance needs to be reduced.
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• External load capacitance at the two sides are usually equal, but in special cases, they may have slightly di󰝗erent
values.
Note:
• Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable
performance within the operating temperature range, etc) may lead to the malfunction of ESP32, resulting in
a decrease of the RF performance.
• It is recommended that the amplitude of the crystal is greater than 500 mV.
• When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps men-
tioned above to ensure that the frequency o󰝗set meets the requirements by adjusting capacitors at the two sides
of the crystal.
3.4.2 RTC Clock Source (Optional)
ESP32 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock.
The external RTC clock source enhances timing accuracy and consequently decreases average power consumption,
without impacting functionality.
Figure ESP32 Schematic for 32.768 kHz Crystal shows the schematic for the external 32.768 kHz crystal.
Fig. 10: ESP32 Schematic for 32.768 kHz Crystal
Please note the requirements for the 32.768 kHz crystal:
• Equivalent series resistance (ESR) ≤ 70 kΩ.
• Load capacitance at both ends should be con󰝘gured according to the crystal’s speci󰝘cation.
The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ≤ 10 MΩ). In general, you do not need to
populate the resistor.
When ESP32-D0WD-V3 connects to an external 32.768 kHz crystal, the parallel resistor must be populated. For
other ESP32 series chips, the resistor can be reserved.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
The external signal can be input to 32K_XN. A capacitor larger than 200 pF should be added to the 32K_XP side.
Figure ESP32 Schematic for External Oscillator shows the schematic of the external signal.
The signal should meet the following requirements:
External signal Amplitude (Vpp, unit: V)
Sine wave or square wave 0.6 < Vpp < VDD
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Fig. 11: ESP32 Schematic for External Oscillator
3.5 RF
3.5.1 RF Circuit
ESP32’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit,
the antenna and the antenna matching circuit. Each part should meet the following requirements:
• For the RF traces on the PCB board, 50 Ω impedance control is required.
• For the chip matching circuit, it must be placed close to the chip. A CLC structure is preferred.
–The CLC structure is mainly used to adjust the impedance point and suppress harmonics, and
a set of LC can be added if space permits.
–The RF matching circuit is shown in Figure ESP32 Schematic for RF Matching.
• For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic
impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust
the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to
be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.
Fig. 12: ESP32 Schematic for RF Matching
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3.5.2 RF Tuning
The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly.
Follow the instructions below to do RF tuning.
Figure ESP32 RF Tuning Diagram shows the general process of RF tuning.
Fig. 13: ESP32 RF Tuning Diagram
The initial value of the parameters in the matching network can be 0 Ω. The recommended value of S11 is 25+j0.
The recommended central frequency is 2442 MHz.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD
protection devices near the antenna.
Note: If RF function is not required, then the RF pin can be left 󰝙oating.
3.6 UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0,
please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available
GPIO by software con󰝘gurations. For these interfaces, it is also recommended to add a series resistor to the TX line
to suppress harmonics.
When using the AT 󰝘rmware, please note that the UART GPIO is already con󰝘gured (refer to AT Firmware Down-
load). It is recommended to use the default con󰝘guration.
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3.7 Strapping Pins
At each startup or reset, a chip requires some initial con󰝘guration parameters, such as in which boot mode to load
the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal
function pins.
All the information about strapping pins is covered in ESP32 Series Datasheet > Section Strapping Pins. In this
document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO0 and GPIO2 controls the boot mode. See Table Boot Mode
Control.
Table 4: Boot Mode Control
Boot Mode GPIO0 GPIO2
Default Con󰝘g 1 0
SPI Boot 1 Any value
Joint Download Boot10 0
Signals applied to the strapping pins should have speci󰝘c setup time and hold time. For more information, see Figure
Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.
Fig. 14: Setup and Hold Times for Strapping Pins
Table 5: Description of Timing Parameters for Strapping Pins
Parameter Description Minimum (ms)
tSU Time reserved for the power rails to stabilize before the chip enable
pin (CHIP_PU) is pulled high to activate the chip.
0
tHTime reserved for the chip to read the strapping pin values after
CHIP_PU is already high and before these pins start operating as
regular IO pins.
3
Attention: Do not add high-value capacitors at GPIO0, otherwise, the chip may not boot successfully.
1Joint Download Boot mode supports the following download methods:
• UART Download Boot
• SDIO Download Boot
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