Espressif Systems ESP32 Series Product manual

ESP32 Technical Reference Manual
Espressif Systems
August 31, 2016

About This Manual
ESP32 Technical Reference Manual targets application developers. The manual provides detailed and
complete information on how to use the ESP32 memory and peripherals.
Release Notes
Date Version Release notes
2016.08 V1.0 Initial release.
Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT
IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF
MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this
document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property
rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth
logo is a registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their
respective owners, and are hereby acknowledged.
Copyright © 2016 Espressif Inc. All rights reserved.

Contents
1 System and Memory 8
1.1 Introduction 8
1.2 Features 8
1.3 Functional Description 10
1.3.1 Address Mapping 10
1.3.2 Embedded Memory 10
1.3.2.1 Internal ROM 0 11
1.3.2.2 Internal ROM 1 11
1.3.2.3 Internal SRAM 0 12
1.3.2.4 Internal SRAM 1 12
1.3.2.5 Internal SRAM 2 13
1.3.2.6 DMA 13
1.3.2.7 RTC FAST Memory 13
1.3.2.8 RTC SLOW Memory 13
1.3.3 External Memory 13
1.3.4 Peripherals 14
1.3.4.1 Asymmetric PID Controller Peripheral 15
1.3.4.2 Non-Contiguous Peripheral Memory Ranges 15
1.3.4.3 Memory Speed 16
2 Interrupt Matrix 17
2.1 Introduction 17
2.2 Features 17
2.3 Functional Description 17
2.3.1 Peripheral Interrupt Source 17
2.3.2 CPU Interrupt 20
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 20
2.3.4 CPU NMI Interrupt Mask 21
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 21
3 Reset and Clock 22
3.1 System Reset 22
3.1.1 Introduction 22
3.1.2 Reset Source 22
3.2 System Clock 23
3.2.1 Introduction 23
3.2.2 Clock Source 24
3.2.3 CPU Clock 24
3.2.4 Peripheral Clock 25
3.2.4.1 APB_CLK Source 25
3.2.4.2 REF_TICK Source 26
3.2.4.3 LEDC_SCLK Source 26
3.2.4.4 APLL_SCLK Source 26
3.2.4.5 PLL_D2_CLK Source 26

3.2.4.6 Clock Source Considerations 27
3.2.5 Wi-Fi BT Clock 27
3.2.6 RTC Clock 27
4 IO_MUX and GPIO Matrix 28
4.1 Introduction 28
4.2 Peripheral Input via GPIO Matrix 29
4.2.1 Summary 29
4.2.2 Functional Description 29
4.2.3 Simple GPIO Input 30
4.3 Peripheral Output via GPIO Matrix 30
4.3.1 Summary 30
4.3.2 Functional Description 30
4.3.3 Simple GPIO Output 31
4.4 Direct I/O via IO_MUX 31
4.4.1 Summary 31
4.4.2 Functional Description 32
4.5 RTC IO_MUX for Low Power and Analog I/O 32
4.5.1 Summary 32
4.5.2 Functional Description 32
4.6 Light-sleep Mode Pin Functions 32
4.7 Pad Hold Feature 33
4.8 I/O Pad Power Supply 33
4.8.1 VDD_SDIO Power Domain 33
4.9 Peripheral Signal List 34
4.10 IO_MUX Pad List 38
4.11 RTC_MUX Pin List 39
4.12 Register Summary 40
4.13 Registers 45
5 LED_PWM 66
5.1 Introduction 66
5.2 Functional Description 66
5.2.1 Architecture 66
5.2.2 Timers 67
5.2.3 Channels 67
5.2.4 Interrupts 68
5.3 Register Summary 68
5.4 Registers 71
6 Remote Controller Peripheral 81
6.1 Introduction 81
6.2 Functional Description 81
6.2.1 RMT Architecture 81
6.2.2 RMT RAM 82
6.2.3 Clock 82
6.2.4 Transmitter 82

6.2.5 Receiver 83
6.2.6 Interrupts 83
6.3 Register Summary 84
6.4 Registers 85
7 PULSE_CNT 90
7.1 Introduction 90
7.2 Functional Description 90
7.2.1 Architecture 90
7.2.2 Counter Channel Inputs 90
7.2.3 Watchpoints 91
7.2.4 Examples 92
7.2.5 Interrupts 92
7.3 Register Summary 92
7.4 Registers 94
8 64-bit Timers 98
8.1 Introduction 98
8.2 Functional Description 98
8.2.1 16-bit Prescaler 98
8.2.2 64-bit Time-base Counter 98
8.2.3 Alarm Generation 99
8.2.4 MWDT 99
8.2.5 Interrupts 99
8.3 Register summary 99
8.4 Registers 101
9 Watchdog Timers 108
9.1 Introduction 108
9.2 Features 108
9.3 Functional Description 108
9.3.1 Clock 108
9.3.1.1 Operating Procedure 109
9.3.1.2 Write Protection 109
9.3.1.3 Flash Boot Protection 109
9.3.1.4 Registers 110
10 AES Accelerator 111
10.1 Introduction 111
10.2 Features 111
10.3 Functional Description 111
10.3.1 AES Algorithm Operations 111
10.3.2 Key, Plaintext and Ciphertext 111
10.3.3 Endianness 112
10.3.4 Encryption and Decryption Operations 114
10.3.5 Speed 114
10.4 Register summary 114

10.5 Registers 116
11 SHA Accelerator 118
11.1 Introduction 118
11.2 Features 118
11.3 Functional Description 118
11.3.1 Padding and Parsing the Message 118
11.3.2 Message Digest 118
11.3.3 Hash Operation 119
11.3.4 Speed 119
11.4 Register Summary 119
11.5 Registers 121

List of Tables
1 Address Mapping 10
2 Embedded Memory Address Mapping 11
3 Module with DMA 13
4 External Memory Address Mapping 14
5 Peripheral Address Mapping 14
6 PRO_CPU, APP_CPU interrupt configuration 18
7 CPU Interrupts 20
8 PRO_CPU and APP_CPU reset reason values 22
9 CPU_CLK Source 24
10 CPU_CLK Derivation 25
11 Peripheral Clock Usage 25
12 APB_CLK Derivation 26
13 REF_TICK Derivation 26
14 LEDC_SCLK Derivation 26
15 IO_MUX Light-sleep Pin Function Registers 32
16 GPIO Matrix Peripheral Signals 34
17 IO_MUX Pad Summary 38
18 RTC_MUX Pin Summary 39
26 Operation Mode 111
27 AES Text Endianness 112
28 AES-128 Key Endianness 113
29 AES-192 Key Endianness 113
30 AES-256 Key Endianness 113

List of Figures
1 System Structure 9
2 System Address Mapping 9
3 Interrupt Matrix Structure 17
4 System Reset 22
5 System Clock 23
6 IO_MUX, RTC IO_MUX and GPIO Matrix Overview 28
7 Peripheral Input via IO_MUX, GPIO Matrix 29
8 Output via GPIO Matrix 31
9 ESP32 I/O Pad Power Sources 33
10 LED_PWM Architecture 66
11 LED_PWM High-speed Channel Diagram 66
12 LED PWM Output Signal Diagram 67
13 Output Signal Diagram of Gradient Duty Cycle 68
14 RMT Architecture 81
15 Data Structure 82
16 PULSE_CNT Architecture 90
17 PULSE_CNT Upcounting Diagram 92
18 PULSE_CNT Downcounting Diagram 92

1 SYSTEM AND MEMORY
1. System and Memory
1.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning they use the
same addresses to access the same memory. Multiple peripherals in the system can access embedded memory
via DMA.
The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however for most
purposes the two CPUs are interchangeable.
1.2 Features
• Address Space
–Symmetric address mapping
–4 GB (32-bit) address space for both data bus and instruction bus
–1296 KB embedded memory address space
–19704 KB external memory address space
–512 KB peripheral address space
–Some embedded and external memory regions can be accessed by either data bus or instruction bus
–328 KB DMA address space
• Embedded Memory
–448 KB Internal ROM
–520 KB Internal SRAM
–8 KB RTC FAST Memory
–8 KB RTC SLOW Memory
• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.
–Supports up to 16 MB off-Chip SPI Flash.
–Supports up to 8 MB off-Chip SPI SRAM.
• Peripherals
–41 peripherals
• DMA
–13 modules are capable of DMA operation
Espressif Systems 8 ESP32 Technical Reference Manual V1.0

1.2 Features 1 SYSTEM AND MEMORY
Figure 1block diagram illustrates the system structure, the block diagram in Figure 2illustrates the address map
structure.
Figure 1: System Structure
Figure 2: System Address Mapping
Espressif Systems 9 ESP32 Technical Reference Manual V1.0