FSP Technology EP 1000 Series User manual

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Инструкция для
FSP EP 1000
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Page 1 of 28 Rev. A
UNINTERRUPTIBLE POWER SYSTEM
SPECIFICATION
EP 1000/ 1500/ 2000 Series

Page 2 of 28 Rev. A
1.0 Revision Summary
REVI SI ON SECTI ON DESCRI PTI ON
Rev. A Formal Release

Page 3 of 28 Rev. A
Table of Contents
1. I ntroduction……………………………………………………. 4
2. Block Diagram ……………………………………………....... 5
3. Control Power Circuit ……………………………………….. 7
4. Battery Charger ………………………………………………. 9
5. Line and Zero-Crossing Detection ……………………….. 11
6. I nverter Operation …………………………………………… 13
7. Active Clamp …………………………………………………… 16
8. Microprocessor (CPU) Control Circuit ………………...... 17
9. Relay Circuit …………………………………………………… 19
10. Display, Audio Alarm and Control Button …………….. 21
11. Load Detection Circuit …………………………………….. 23
12. I nterface Circuit …………………………………………….. 24
13. Troubleshooting …………………………………………….. 25

Page 4 of 28 Rev. A
1 I ntroduction
EPseries is a line interactive power system that has a step wave output. It prevents impulse,
surge, sag and power outage situations. It provides the UPSoutput load with a reliable
source. It has the following functions:
1.1 Boost:
If the utility voltage drops to line boost activated point*, the AVRwill be activated
and increase the input voltage by 1.18 times of incoming utility voltage.
*Boost activated point
110 VAC 120 VAC 220 VAC 230 VAC 240 VAC
99 VAC 108 VAC 198 VAC 207 VAC 216 VAC
1.2 Buck:
If the utility voltage reaches to line buck activated point, the AVRwill be activated
and decrease the input voltage by 0.85 times of incoming utility voltage.
*Buck activated point
110 VAC 120 VAC 220 VAC 230 VAC 240 VAC
121 VAC 132VAC 242 VAC 253 VAC 264VAC
1.3 50/ 60Hz Automatic Frequency Selection:
The output frequency will automatically match the input frequency (50 or 60Hz).
1.4 Communication Port (USB):
It provides remote shutdown capability via communication port for connected
computers.
1.5 Data line/ telephone line protection:
The unit provides RJ11 port to provide transient voltage surge suppression
(TVSS) for data line or telephone line.
1.6 Cold start (DC start):
The UPSisequipped with DCstart function to turn on the UPSwithout input source.
This manual contains block diagram, principle of operation, system outline and
troubleshooting.

Page 5 of 28 Rev. A
2 Block Diagram
The Block diagram of Vesta series (refer to Figure S-1) is divided into the following parts:
2.1 Main Relay (MAI N-RY):
It’s to switch the UPSbetween line mode and battery mode.
2.2 Boost Relay (BOOST-RY):
At line mode, this is a switch used to boost UPSoutput voltage 18% when the utility
voltage is under line boost activated point. (Refer to Boost activated point table in
P.4)
Relay OFF: line voltage is normal
Relay ON: line voltage is under line boost activated point.
2.3 Buck Relay:
At line mode, this isa switch used to lower UPSoutput voltage 15% when the utility
voltage is over line buck activated point. (Refer to Buck activated point table in P.4)
Relay OFF: line voltage is normal
Relay ON: line voltage is over line buck activated point
2.4 Main Transformer (MAI N TX):
The Main transformer has three functions:
2.4.1 I nverter Transformer
It provides voltage to UPS output and performs a full-bridge transformer
when UPS is at battery mode.
2.4.2 Boost/ Buck
The output coils have an output ratio. Thus the output voltage at boost mode is
given by (Boost Relay ON):
VOUT = VIN * 1.18
The Buck relay is ON when the utility voltage is beyond line buck activated point.
It can lower 15% of input voltage:
VOUT = VIN * 0.85
2.4.3 Charger:
The battery is charged by the mains through transformer and full-bridge
inverter.
2.5 Line Sense
The MCU detect the mains by input voltage and frequency signals converted from
the amplifier.

Page 6 of 28 Rev. A
2.6 CPU (MOTOROLA/ MC68HC908JL8CSP)
The Central Process Unit
2.7 Electricity Switch
It controls the +5Vdc and +12Vdc supplies.
+5Vdc and +12Vdc Control Power Generator.
Provide +5Vdc (generated from 7805 regulator) and +12Vdc power supply.
2.8 Charger:
The source for the Charger comes from the mains through the transformer and
full-bridge inverter. The charger is controlled with high frequency technology and
the acceptable charging voltage is 13.6~13.9V.
2.9 I nverter Circuit:
The inverter circuit is based on a full-bridge circuitry.
2.10 I nterface Circuit:
Vesta 1000: The UPSdisplay device contains three LEDs and one switch.
Vesta 1500/2000: The UPS display device contains six LEDs and one switch.
2.11 Batteries:
Acts as a power supply source while the UPS is on battery mode. Different types
of batteries are used for different models of UPS:
1000VA: 12V7Ah *2 pcs or equal capability
1500VA: 12V45W *2 pcs or equal capability
2000VA: 12V45W *2 pcs or equal capability
Figure S-1 Block Diagram

Page 7 of 28 Rev. A
3 Control power circuit
The control power (+12Vdc and +5Vdc) comes from the following sources (Figure S-2).
3.1 Start without input AC power (Cold start):
A “Cold start “is described as follows:
3.1.1 When “ON/OFF” switch (SW1) is pressed, a positive battery current flows
through SW1 to charge C15.
3.1.2 Q12 base receives a HI pulse and turns on (signal bypass C15 at t=0, and
charge C15 at t>0).
3.1.3 When Q12 turns on, the Q12 collector will drop to LOW and turn on Q11
(MPS2907A).
3.1.4 When Q11 turns on, the positive battery voltage via Q12 collector and
establishes a +12Vdc power supply. The +12Vdc power supply passes
through U03 (78L05) generating a +5Vdc logic power supply. And CPU
send HI signal (shutdown) to sustain Q12 on.
3.1.5 Figure W-1 shows the pulse on the C15, i.e. the base signal of Q12 during
the cold start.
3.2 Start with input AC power (AC start):
3.2.1 When we connect UPS to the utility, half-wave rectifier will activate Q12
through D2, ZD1, and Q16.
3.2.2 If “ON/OFF” switch is pressed, Q11 turns on and establishes a +12Vdc and
+5Vdc power supply similar to “Cold start”.
The SHUTDOWN network, triggered by pin 15 of the CPU, is used to shutdown the UPSon
battery mode. When a battery is in low battery voltage status, the CPU sends a “Low”
signal to turn off Q12. This causes Q11 to be turned off and isolates the control
power from batteries.

Page 8 of 28 Rev. A
Figure S-2 Control Power Circuit
CH1: C15 åGND Figure W-1 Cold Start

Page 9 of 28 Rev. A
4 Battery Charger
The flow chart of charger is described as follows: (Figure S-3-A & Figure S-3-B)
4.1 When UPSis connected to the utility, the control power (+5Vdc) will be established
and the CPU will start to work.
4.2 When CPU turns on Main Relay (RY01), the ACpower flows into Main Transformer.
4.3 Charging current will be generated from the inverter coil of the Main Transformer.
4.4 A PWM IC3843 is used to adjust the charging voltage and charging current. (Refer
to Figure S-3-A) The charging voltage can be set by changing the value of R87, R88,
R46 and R65. The charging current can be set by changing the value of R14.
Figure S-3-A Charger Control Circuit

Page 10 of 28 Rev. A
Figure S-3-B Charger Control Circuit

Page 11 of 28 Rev. A
5 Line and Zero-Crossing Detection
Please refer Figure S-4
5.1 Line Detection
The input voltage is fully rectified and generates a signal. The signal will be sent to
pin 11 of CPU through a voltage divider at R45, R45A and R40//R47. By monitoring
this rectified sinusoidal voltage, the CPU can identify if the utility is normal or
abnormal. There are two methods to evaluate if line voltage is abnormal.
5.1.1 Waveform detection:
If breakout occurs, the CPU is able to immediately detect it and transfers
to battery mode. The waveform detection has a short response time.
5.1.2 RMS value detection:
CPU calculates input RMS value every cycle. If RMS value is not in acceptable
range for 3 cycles, UPSwill transfer to battery mode. Compared to waveform
detection, although it will take longer response time, the RMSvalue can be
accurately detected.
5.2 Zero Crossing Detection
Zero Crossing Detection is used to minimize the phase difference between
the Inverter voltage and the input line voltage while UPS is switched from battery
mode to line mode. If the phase difference is too large, it will generate excess
energy which may damage the internal passive components such as relays.
The Zero Crossing signal is generated by the following conditions:
5.2.1 The signal of Line-I/P is full-bridge rectified waveform from line input.
The voltage of Pin 7 of IC324 drives Q14 (2222ASM) on or off.
5.2.2 The Zero Crossing signal comes from the collector of Q14 and goes
through MCU pin 27.
5.2.3 Refer to Figure W-2. The waveform of ZERO-CRO from Q14 collector and
Line-I/P.

Page 12 of 28 Rev. A
Figure S-4 Line and Zero Crossing Detecting Circuit
CH1: Line-I/P
CH2: Q14 collector Figure W-2 Zero Crossing

Page 13 of 28 Rev. A
6 I nverter Operation
The Inverter circuit (Figure S-5-A and Figure S-5-B) and PWM control are only active under
Battery mode. The Inverter circuit of Vesta is based on a full-Bridge circuitry and its output is
driven by a transistor which is controlled by CPU.
Refer to the Inverter circuit diagram, the CPU.M1, CPU.M2, CPU.M3, and CPU.M4 signals
are generated by CPU. Figure W-3 illustrates the waveforms of CPU.M1, CPU.M2, CPU.M3,
and CPU.M4 while the system is at no load condition. The duty cycles of CPU.M1, CPU.M2,
CPU.M3, and CPU.M4 signals are controlled by returned signal of output voltage (Please refer
to Charger circuit) to get a stable output.
The gates of MOSFETs are driven by transistors Q5, Q6, Q7, Q8, which are controlled by
theCPU.M1M2.VGSM3.VGSand CPU.M4. Thosesignalsare from CPUpin18, 19, 20 & 21
directly or indirectly. Figure W-3 (1) shows the collector waveforms for CPU pin18, 19, 20 and
21 while the system is at no load condition at battery mode.
These inverter transistorsare turned on and off alternately to transfer DCvoltage of battery to
an ACstepwave output voltage, and then magnifies through the transformer to generate
a stable 230VACoutput.
According to the diagram shown on “Figure W-3 Control logic (1)”, while the driving
signal M2.VGS and M3.VGS both get HI simultaneously in battery mode, the step output
waveform get approximately zero, which is named CLAMP. In full-bridge circuit,
unlike push-pull circuitry having isolated CLAMPcircuitry and driven signal, the CLAMPsignals
are included in inverter drive logic.

Page 14 of 28 Rev. A
Figure S-5-A Vesta 1000 I nverter circuit
Figure S-5-B Vesta 1500 & Vesta 2000 I nverter circuit

Page 15 of 28 Rev. A
CH1: DS-N
CH2: Output Voltage (1/200V)
Figure W-3 Control logic (1)

Page 16 of 28 Rev. A
7 Active Clamp
The purpose of Clamp is to pull down the output voltage while two sets of Inverter MOSFET
are OFF. The Clamp effect is active during the period of 0Vac at battery mode. CLAMP
principle is shown in the last paragraph of Chapter 6 Inverter Operation.

Page 17 of 28 Rev. A
8 Microprocessor(CPU) Control Circuit
The CPU is supplied by +5Vdc power supply to pin7 with ground pin at pin3. An
extra oscillation circuitry consisting of C01, C02, and crystal XL1 is connected to pin4 &5.
The Vesta series is using MOTOROLA/MC68HC908JL8CSPCPU. The pin definition is listed
below (Refer to Figure S-6 CPU control circuit):
PI N FUNCTI ON
Pin1 N/
A
Pin2 SW
Pin3 ground
Pin4 oscillation circuit
Pin5 oscillation circui
t
Pin6 main relay control
Pin7 Power source
Pin8 series detect (GREEN FUNTION)
Pin9 CHG.ON
Pin10 O/P-V detection
Pin11 Input line detection
Pin12 Load detection
Pin13 RXD
Pin14
T
XD
Pin15 Shutdown
Pin16 Buzzer control
Pin17 Battery voltage detection
Pin18 Inverter PWM signal (CPU.M3)
Pin19 Inverter PWM signal (CPU.M2)
Pin20 Inverter PWM signal (CPU.M4)
Pin21 Inverter PWM signal (CPU.M1)
Pin22 VA detect
Pin23 Series detect
Pin24 LED1 control
Pin25 LED2 control
Pin26 LED3 control
Pin27 ZERO-CRO control
Pin28 Buck relay control
Pin29 Boost relay control
Pin30 Reset control
Pin31 O-PRelay
Pin32 Voltage detect

Page 18 of 28 Rev. A
Figure S-6 CPU Control Circuit

Page 19 of 28 Rev. A
9 Relay Circuit
Figure S-7 is the relay circuit.
The RY01 (main relay) is used to switch between line and battery modes. When the UPS is
changing from battery to line mode, CPU pin6 is set to HI to turn on Q1AP(2SC1815) and
activatesRY01. Alternatively, if the UPSischanging from line mode to battery mode, CPUpin6
is set to LOW and turn off Q03. This causes RY01 to be OFF and return to its normal state.
R3AP, D1AP, C1APand Q2APare used to speed up the relay transfer action, so the power
failure time can be shorten to minimum. When UPStransfersto battery mode, C1APischarged
by the +12 Volts. After the main relay makes contact, C1APprovides instantaneous power to
the relay coils. Thiswill increase the magnetic force and shorten the transfer time from battery
mode to line modeby switching the relay. SeeFigure W-6 for voltage changeson C1AP, during
transfer time from line to battery mode.
CPU pin29 is used to drive signal for RY02 (boost relay). When the line input voltage is low
within boost activated point, pin29 sends a high signal to turn on Q05 (2SC1815). This will
activate the RY02, and UPSwill transfer to the Boost mode. When the line input voltage
increases to reach inactivated boost point, the UPS will return to normal mode by sending
a LOW signal from pin29. This forces RY02 to switch to its normal position (OFF). At battery
mode, pin29 is always set to LOW and RY02 is disabled.
Buck situation is the similar process. CPU pin28 is used to drive signal for RY03 (buck
relay). When the line input voltage risesbeyond buck activated point, CPU pin28 sends a high
signal to turn on RY03. When the line input voltage decreases below the inactivated buck
point, the UPSreturns back to normal mode by sending a LOW signal from pin28.
Figure S-7 Relay Circuit