Fujitsu SPARC JPS1 User manual

Fujitsu Limited
4-1-1 Kamikodanaka
Nahahara-ku, Kawasaki, 211-8588
Japan
SPARC JPS1
Implementation Supplement:
Fujitsu SPARC64 V
Fujitsu Limited
Release 1.0, 1 July 2002
Part No. 806-6755-1.0

Release 1.0, 1 July 2002 F. Chapter 2
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3SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

i
F.CHAPTER
Contents
1. Overview 1
Navigating the SPARC64 V Implementation Supplement 1
Fonts and Notational Conventions 1
The SPARC64 V processor 2
Component Overview 4
Instruction Control Unit (IU) 6
Execution Unit (EU) 6
Storage Unit (SU) 7
Secondary Cache and External Access Unit (SXU) 8
2. Definitions 9
3. Architectural Overview 13
4. Data Formats 15
5. Registers 17
Nonprivileged Registers 17
Floating-Point State Register (FSR) 18
Tick (TICK) Register 19
Privileged Registers 19
Trap State (TSTATE) Register 19
Version (VER) Register 20
Ancillary State Registers (ASRs) 20
Registers Referenced Through ASIs 22

ii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Floating-Point Deferred-Trap Queue (FQ) 24
IU Deferred-Trap Queue 24
6. Instructions 25
Instruction Execution 25
Data Prefetch 25
Instruction Prefetch 26
Syncing Instructions 27
Instruction Formats and Fields 28
Instruction Categories 29
Control-Transfer Instructions (CTIs) 29
Floating-Point Operate (FPop) Instructions 30
Implementation-Dependent Instructions 30
Processor Pipeline 31
Instruction Fetch Stages 31
Issue Stages 33
Execution Stages 33
Completion Stages 34
7. Traps 35
Processor States, Normal and Special Traps 35
RED_state 36
error_state 36
Trap Categories 37
Deferred Traps 37
Reset Traps 37
Uses of the Trap Categories 37
Trap Control 38
PIL Control 38
Trap-Table Entry Addresses 38
Trap Type (TT) 38
Details of Supported Traps 39
Trap Processing 39
Exception and Interrupt Descriptions 39
SPARC V9 Implementation-Dependent, Optional Traps That Are
Mandatory in SPARC JPS1 39

Release 1.0, 1 July 2002 F. Chapter Contents iii
SPARC JPS1 Implementation-Dependent Traps 39
8. Memory Models 41
Overview 42
SPARC V9 Memory Model 42
Mode Control 42
Synchronizing Instruction and Data Memory 42
A. Instruction Definitions: SPARC64 V Extensions 45
Block Load and Store Instructions (VIS I) 47
Call and Link 49
Implementation-Dependent Instructions 49
Floating-Point Multiply-Add/Subtract 50
Jump and Link 53
Load Quadword, Atomic [Physical] 54
Memory Barrier 55
Partial Store (VIS I) 57
Prefetch Data 57
Read State Register 58
SHUTDOWN (VIS I) 58
Write State Register 59
Deprecated Instructions 59
Store Barrier 59
B. IEEE Std 754-1985 Requirements for SPARC V9 61
Traps Inhibiting Results 61
Floating-Point Nonstandard Mode 61
fp_exception_other Exception (ftt=unfinished_FPop) 62
Operation Under FSR.NS = 1 65
C. Implementation Dependencies 69
Definition of an Implementation Dependency 69
Hardware Characteristics 70
Implementation Dependency Categories 70
List of Implementation Dependencies 70

iv SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
D. Formal Specification of the Memory Models 81
E. Opcode Maps 83
F. Memory Management Unit 85
Virtual Address Translation 85
Translation Table Entry (TTE) 86
TSB Organization 88
TSB Pointer Formation 88
Faults and Traps 89
Reset, Disable, and RED_state Behavior 91
Internal Registers and ASI operations 92
Accessing MMU Registers 92
I/D TLB Data In, Data Access, and Tag Read Registers 93
I/D TSB Extension Registers 97
I/D Synchronous Fault Status Registers (I-SFSR, D-SFSR) 97
MMU Bypass 104
TLB Replacement Policy 105
G. Assembly Language Syntax 107
H. Software Considerations 109
I. Extending the SPARC V9 Architecture 111
J. Changes from SPARC V8 to SPARC V9 113
K. Programming with the Memory Models 115
L. Address Space Identifiers 117
SPARC64 V ASI Assignments 117
Special Memory Access ASIs 119
Barrier Assist for Parallel Processing 121
Interface Definition 121
ASI Registers 122
M. Cache Organization 125
Cache Types 125
Level-1 Instruction Cache (L1I Cache) 126

Release 1.0, 1 July 2002 F. Chapter Contents v
Level-1 Data Cache (L1D Cache) 127
Level-2 Unified Cache (L2 Cache) 127
Cache Coherency Protocols 128
Cache Control/Status Instructions 128
Flush Level-1 Instruction Cache (ASI_FLUSH_L1I) 129
Level-2 Cache Control Register (ASI_L2_CTRL) 130
L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ) 130
L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG) 131
N. Interrupt Handling 133
Interrupt Dispatch 133
Interrupt Receive 135
Interrupt Global Registers 136
Interrupt-Related ASR Registers 136
Interrupt Vector Dispatch Register 136
Interrupt Vector Dispatch Status Register 136
Interrupt Vector Receive Register 136
O. Reset, RED_state, and error_state 137
Reset Types 137
Power-on Reset (POR) 137
Watchdog Reset (WDR) 138
Externally Initiated Reset (XIR) 138
Software-Initiated Reset (SIR) 138
RED_state and error_state 139
RED_state 140
error_state 140
CPU Fatal Error state 141
Processor State after Reset and in RED_state 141
Operating Status Register (OPSR) 146
Hardware Power-On Reset Sequence 147
Firmware Initialization Sequence 147
P. Error Handling 149
Error Classification 149
Fatal Error 149

vi SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
error_state Transition Error 150
Urgent Error 150
Restrainable Error 152
Action and Error Control 153
Registers Related to Error Handling 153
Summary of Actions Upon Error Detection 154
Extent of Automatic Source Data Correction for Correctable Error 157
Error Marking for Cacheable Data Error 157
ASI_EIDR 161
Control of Error Action (ASI_ERROR_CONTROL) 161
Fatal Error and error_state Transition Error 163
ASI_STCHG_ERROR_INFO 163
Fatal Error Types 164
Types of error_state Transition Errors 164
Urgent Error 165
URGENT ERROR STATUS (ASI_UGESR) 165
Action of async_data_error (ADE) Trap 168
Instruction End-Method at ADE Trap 170
Expected Software Handling of ADE Trap 171
Instruction Access Errors 173
Data Access Errors 173
Restrainable Errors 174
ASI_ASYNC_FAULT_STATUS (ASI_AFSR) 174
ASI_ASYNC_FAULT_ADDR_D1 177
ASI_ASYNC_FAULT_ADDR_U2 178
Expected Software Handling of Restrainable Errors 179
Handling of Internal Register Errors 181
Register Error Handling (Excluding ASRs and ASI Registers) 181
ASR Error Handling 182
ASI Register Error Handling 183
Cache Error Handling 188
Handling of a Cache Tag Error 188
Handling of an I1 Cache Data Error 190
Handling of a D1 Cache Data Error 190
Handling of a U2 Cache Data Error 192
Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache 193

Release 1.0, 1 July 2002 F. Chapter Contents vii
TLB Error Handling 195
Handling of TLB Entry Errors 195
Automatic Way Reduction of sTLB 196
Handling of Extended UPA Bus Interface Error 197
Handling of Extended UPA Address Bus Error 197
Handling of Extended UPA Data Bus Error 197
Q. Performance Instrumentation 201
Performance Monitor Overview 201
Sample Pseudocodes 201
Performance Monitor Description 203
Instruction Statistics 204
Trap-Related Statistics 206
MMU Event Counters 207
Cache Event Counters 208
UPA Event Counters 210
Miscellaneous Counters 211
R. UPA Programmer’s Model 213
Mapping of the CPU’s UPA Port Slave Area 213
UPA PortID Register 214
UPA Config Register 215
S. Summary of Differences between SPARC64 V and UltraSPARC-III 219
Bibliography 223
General References 223
Index 225

viii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V •Release 1.0, 1 July 2002

1
F.CHAPTER 1
Overview
1.1 Navigating the SPARC64 V
Implementation Supplement
We suggest that you approach this Implementation Supplement SPARC Joint
Programming Specification as follows.
1. Familiarize yourself with the SPARC64 V processor and its components by
reading these sections:
■The SPARC64 V processor on page 2
■Component Overview on page 4
■Processor Pipeline on page 31
2. Study the terminology in Chapter 2, Definitions:
3. For details of architectural changes, see the remaining chapters in this
Implementation Supplement as your interests direct.
For this revision, we added new appendixes: Appendix R, UPA Programmer’s Model,
and Appendix S, Summary of Differences between SPARC64 V and UltraSPARC-III.
1.2 Fonts and Notational Conventions
Please refer to Section 1.2 of Commonality for font and notational conventions.

2SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V •Release 1.0, 1 July 2002
1.3 The SPARC64 V processor
The SPARC64 V processor is a high-performance, high-reliability, and high-integrity
processor that fully implements the instruction set architecture that conforms to
SPARC V9, as described in JPS1 Commonality. In addition, the SPARC64 V processor
implements the following features:
■64-bit virtual address space and 43-bit physical address space
■Advanced RAS features that enable high-integrity error handling
Microarchitecture for High Performance
The SPARC64 V is an out-of-order execution superscalar processor that issues up to
four instructions per cycle. Instructions in the predicted path are issued in program
order and are stored temporarily in reservation stations until they are dispatched out
of program order to appropriate execution units. Instructions commit in program
order when no exceptional conditions occur during execution and all prior
instructions commit (that is, the result of the instruction execution becomes visible).
Out-of-order execution in SPARC64 V contributes to high performance.
SPARC64 V implements a large branch history buffer to predict its instruction path.
The history buffer is large enough to sustain a good prediction rate for large-scale
programs such as DBMS and to support the advanced instruction fetch mechanism
of SPARC64 V. This instruction fetch scheme predicts the execution path beyond the
multiple conditional branches in accordance with the branch history. It then tries to
prefetch instructions on the predicted path as much as possible to reduce the effect
of the performance penalty caused by instruction cache misses.
High Integration
SPARC64 V integrates an on-board, associative, level-2 cache. The level-2 cache is
unified for instruction and data. It is the lowest layer in the cache hierarchy.
This integration contributes to both performance and reliability of SPARC64 V. It
enables shorter access time and more associativity and thus contributes to higher
performance. It contributes to higher reliability by eliminating the external
connections for level-2 cache.
High Reliability and High Integrity
SPARC64 V implements the following advanced RAS features for reliability and
integrity beyond that of ordinary microprocessors.

Release 1.0, 1 July 2002 F. Chapter 1 Overview 3
1. Advanced RAS features for caches
■Strong cache error protection:
■ECC protection for D1 (Data level 1) cache data, U2 (unified level 2) cache data,
and the U2 cache tag.
■Parity protection for I1 (Instruction level 1) cache data.
■Parity protection and duplication for the I1 cache tag and the D1 cache tag.
■Automatic correction of all types of single-bit error:
■Automatic single-bit error correction for the ECC protected data.
■Invalidation and refilling of I1 cache data for the I1 cache data parity error.
■Copying from duplicated tag for I1 cache tag and D1 cache tag parity errors.
■Dynamic way reduction while cache consistency is maintained.
■Error marking for cacheable data uncorrectable errors:
■Special error-marking pattern for cacheable data with uncorrectable errors. The
identification of the module that first detects the error is embedded in the
special pattern.
■Error-source isolation with faulty module identification in the special error-
marking. The identification information enables the processor to avoid
repetitive error logging for the same error cause.
2. Advanced RAS features for the core
■Strong error protection:
■Parity protection for all data paths.
■Parity protection for most of software-visible registers and internal temporary
registers.
■Parity prediction or residue checking for the accumulator output.
■Hardware instruction retry
■Support for software instruction retry (after failure of hardware instruction retry)
■Error isolation for software recovery:
■Error indication for each programmable register group.
■Indication of retryability of the trapped instruction.
■Use of different error traps to differentiate degrees of adverse effects on the
CPU and the system.
3. Extended RAS interface to software
■Error classification according to the severity of the effect on program execution:
■Urgent error (nonmaskable): Unable to continue execution without OS
intervention; reported through a trap.
■Restrainable error (maskable): OS controls whether the error is reported
through a trap, so error does not directly affect program execution.
■Isolated error indication to determine the effect on software

4SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V •Release 1.0, 1 July 2002
■Asynchronous data error (ADE) trap for additional errors:
■Relaxed instruction end method (precise, retryable, not retryable) for the
async_data_error exception to indicate how the instruction should end; depends
on the executing instruction and the detected error.
■Some ADE traps that are deferred but retryable.
■Simultaneous reporting of all detected ADE errors at the error barrier for correct
handling of retryability.
1.3.1 Component Overview
The SPARC64 V processor contains these components.
■Instruction control Unit (IU)
■Execution Unit (EU)
■Storage Unit (SU)
■Secondary cache and eXternal access Unit (SXU)
FIGURE 1-1 illustrates the major units; the following subsections describe them.

Release 1.0, 1 July 2002 F. Chapter 1 Overview 5
FIGURE 1-1 SPARC64 V Major Units
Extended UPA Bus
UPA interface logic
MoveIn buffer MoveOut buffer
SX-Unit
U2$ U2$ data
S-Unit interface
tag 2M 4-way ALUs
FLA
EXA
EXB
FLB
EAGA
EAGB
ALU
Output
Input
Registers
Registers
SX order queue Store queue
SX interface
D-TLB tag data
2048
+ 32
entry
Level-1 D cache
128 KB, 2-way
S-Unit
and
Instruction Instruction
Commit stack entry
Reservation stations
Branch
history
PC
nPC
CCR
FSR
I-Unit
GUB FUB
GPR FPR
E-unit
control
logic
pipeline
fetch buffer
E-Unit
I-TLB tag data
2048
+ 32
entry
Level-1 I cache
128 KB, 2-way

6SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V •Release 1.0, 1 July 2002
1.3.2 Instruction Control Unit (IU)
The IU predicts the instruction execution path, fetches instructions on the predicted
path, distributes the fetched instructions to appropriate reservation stations, and
dispatches the instructions to the execution pipeline. The instructions are executed
out of order, and the IU commits the instructions in order. Major blocks are defined
in TABLE 1-1.
1.3.3 Execution Unit (EU)
The EU carries out execution of all integer arithmetic, logical, shift instructions, all
floating-point instructions, and all VIS graphic instructions. TABLE 1-2 describes the
EU major blocks.
TABLE 1-1 Instruction Control Unit Major Blocks
Name Description
Instruction fetch pipeline Five stages: fetch address generation, iTLB access, iTLB match,
I-Cache fetch, and a write to I-buffer.
Branch history 16K entries, 4-way set associative.
Instruction buffer Six entries, 32 bytes/entry.
Reservation station Six reservation stations to hold instructions until they can
execute: RSBR for branch and the other control-transfer
instructions; RSA for load/store instructions; RSEA and RSEB for
integer arithmetic instructions; RSFA and RSFB for floating-point
arithmetic and VIS instructions.
Commit stack entries Sixty-four entries; basically one instruction/entry, to hold
information about instructions issued but not yet committed.
PC, nPC, CCR, FSR Program-visible registers for instruction execution control.
TABLE 1-2 Execution Unit Major Blocks
Name Description
General register (gr) renaming
register file (GUB: gr update
buffer)
Thirty-two entries, 8 read ports, 2 write ports
Gr architecture register file (GPR) 160 entries, 1 read port, 2 write ports
Floating-point (fr) renaming
register file (FUB: fr update
buffer)
Thirty-two entries, 8 read ports, 2 write ports
Fr architecture register file (FPR)Thirty-twoentries,
6 read ports, 2 write ports
EU control logic Controls the instruction execution stages: instruction
selection, register read, and execution.

Release 1.0, 1 July 2002 F. Chapter 1 Overview 7
1.3.4 Storage Unit (SU)
The SU handles all sourcing and sinking of data for load and store instructions.
TABLE 1-3 describes the SU major blocks.
Interface registers Input/output registers to other units.
Two integer execution pipelines
(EXA, EXB) 64-bit ALU and shifters.
Two floating-point and graphics
execution pipelines (FLA, FLB) Each floating-point execution pipeline can execute floating point multiply, floating point add/sub, floating-point
multiply and add, floating point div/sqrt, and floating-
point graphics instruction.
Two virtual address adders for
memory access pipeline (EAGA,
EAGB)
Two 64-bit virtual addresses for load/store.
TABLE 1-3 Storage Unit Major Blocks
Name Description
Instruction level-1 cache 128-Kbyte, 2-way associative, 64-byte line; provides low latency
instruction source
Data level-1 cache 128-Kbyte, 2-way associative, 64-byte line, writeback; provides
the low latency data source for loads and stores.
Instruction Translation
Buffer 1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages1,
32 entries, fully associative TLB for unlocked 64-Kbyte, 512-
Kbyte, 4-Mbyte1pages and locked pages in all sizes.
1. Unloced 4-Mbyte page entry isstored either in 2-way associative TLB or fully associative
TLB exclusively, depending on the setting.
Data Translation Buffer 1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages1,
32 entries, fully associative TLB for unlocked 64-Kbyte, 512-
Kbyte, 4-Mbyte1pages and locked pages in all sizes.
Store queue Decouples the pipeline from the latency of store operations.
Allows the pipeline to continue flowing while the store waits for
data, and eventually writes into the data level 1 cache.
TABLE 1-2 Execution Unit Major Blocks (Continued)
Name Description

8SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V •Release 1.0, 1 July 2002
1.3.5 Secondary Cache and External Access Unit (SXU)
The SXU controls the operation of unified level-2 caches and the external data access
interface (extended UPA interface). TABLE 1-4 describes the major blocks of the SXU.
TABLE 1-4 Secondary Cache and External Access Unit Major Blocks
Name Description
Unified level-2 cache 2-Mbyte, 4-way associative, 64-byte line, writeback; provides low
latency data source for both instruction level-1 cache and data
level-1 cache.
Movein buffer Sixteen entries, 64-bytes/entry; catches returning data from
memory system in response to the cache line read request. A
maximum of 16 outstanding cache read operations can be issued.
Moveout buffer Eight entries, 64-bytes/entry; holds writeback data. A maximum
of 8 outstanding writeback requests can be issued.
Extended UPA interface
control logic Send/receive transaction packets to/from Extended UPA interface connected to the system.

9
F.CHAPTER 2
Definitions
This chapter defines concepts unique to the SPARC64 V, the Fujitsu implementation
of SPARC JPS1. For definition of terms that are common to all implementations,
please refer to Chapter 2 of Commonality.
committed Term applied to an instruction when it has completed without error and all
prior instructions have completed without error and have been committed. When
an instruction is committed, the state of the machine is permanently changed
to reflect the result of the instruction; the previously existing state is no longer
needed and can be discarded.
completed Term applied to an instruction after it has finished,has sent a nonerror status to
the issue unit, and all of its source operands are nonspeculative. Note:
Although the state of the machine has been temporarily altered by completion
of an instruction, the state has not yet been permanently changed and the old
state can be recovered until the instruction has been committed.
executed Term applied to an instruction that has been processed by an execution unit
such as a load unit. An instruction is in execution as long as it is still being
processed by an execution unit.
fetched Term applied to an instruction that is obtained from the I2 instruction cache or
from the on-chip internal cache and sent to the issue unit.
finished Term applied to an instruction when it has completed execution in a functional
unit and has forwarded its result onto a result bus. Results on the result bus are
transferred to the register file, as are the waiting instructions in the instruction
queues.
initiated Term applied to an instruction when it has all of the resources that it needs (for
example, source operands) and has been selected for execution.
instruction dispatch Synonym: instruction initiation.
instruction issued Term applied to an instruction when it has been dispatched to a reservation
station.