General Standards Corporation PCIe-SIO4BX2 User manual

PCIe-SIO4BX2
User’s Manual
Four Channel PCIe High Performance Serial I/O
Featuring RS422/RS485/RS232 Software Configurable Transceivers
and 32K Byte FIFO Buffers (256K Byte total)
RS-485
RS-422/V.11
RS-232/V.28
General Standards Corporation
8302A Whitesburg Drive
Huntsville, AL 35802
Phone: [phone]
Fax: [phone]
URL: www.generalstandards.com
E-mail: [email protected]
Revision NR

i Rev NR
PREFACE
Revision History
1. Rev NR –Mar 2013 –Original rev from PMC66-SIO4BXR manual.
Additional copies of this manual or other General Standards Corporation literature may be obtained
from:
General Standards Corporation
8302A Whitesburg Drive
Huntsville, Alabama 35802
Telephone: [phone]
Fax: [phone]
URL: www.generalstandards.com
The information in this document is subject to change without notice.
General Standards Corporation makes no warranty of any kind with regard to this material, including,
but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Although
extensive editing and reviews are performed before release to ECO control, General Standards
Corporation assumes no responsibility for any errors that may exist in this document. No commitment is
made to update or keep current the information contained in this document.
General Standards Corporation does not assume any liability arising out of the application or use of any
product or circuit described herein, nor is any license conveyed under any patent right of any rights of
others.
General Standards Corporation assumes no responsibility resulting from omissions or errors in this
manual, or from the use of information contained herein.
General Standards Corporation reserves the right to make any changes, without notice, to this product
to improve reliability, performance, function, or design.
All rights reserved
No parts of this document may be copied or reproduced in any form or by any means without prior written
consent of General Standards Corporation.
Copyright © 2013 General Standards Corporation

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RELATED PUBLICATIONS
ZILOG Z16C30 USC® User’s Manual
ZILOG Z16C30 USC® Product Specifications Databook
ZILOG, Inc.
210 East Hacienda Ave.
Campbell, CA 95008-6600
[phone]
http://www.zilog.com/
PLX PCI 9056 Data Book
PLX Technology Inc.
390 Potrero Avenue
Sunnyvale, CA 4085
[phone]
http://www.plxtech.com/
EIA-422-A –Electrical Characteristics of Balanced Voltage Digital Interface Circuits
(EIA order number EIA-RS-422A)
EIA-485 –Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital
Multipoint Systems
(EIA order number EIA-RS-485)
EIA Standards and Publications can be purchased from:
GLOBAL ENGINEERING DOCUMENTS
15 Inverness Way East
Englewood, CO 80112
Phone: [phone]
http://global.ihs.com/
PCI Local Bus Specification Revision 2.2 December 18, 1998
Copies of PCI specifications available from:
PCI Special Interest Group
NE 2575 Kathryn Street, #17
Hillsboro, OR 97124
http://www.pcisig.com/

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TABLE OF CONTENTS
CHAPTER 1: INTRODUCTION..............................................................................................................................1
1.0 GENERAL DESCRIPTION..................................................................................................................................1
1.1 Z16C30 UNIVERSAL SERIAL CONTROLLER ....................................................................................................2
1.2 DEEP TRANSMIT/RECEIVE FIFOS...................................................................................................................2
1.3 MULTIPROTOCOL TRANSCEIVERS...................................................................................................................3
1.4 PMC/PCI INTERFACE.....................................................................................................................................3
1.5 GENERAL PURPOSE IO ...................................................................................................................................3
1.6 CONNECTOR INTERFACE ................................................................................................................................3
1.7 NEW FEATURES..............................................................................................................................................3
CHAPTER 2: LOCAL SPACE REGISTERS..........................................................................................................4
2.0 REGISTER MAP...............................................................................................................................................4
2.1 GSC FIRMWARE REGISTERS...........................................................................................................................4
2.1.1 FIRMWARE REVISION:LOCAL OFFSET 0X0000..............................................................................................5
2.1.2 BOARD CONTROL:LOCAL OFFSET 0X0004....................................................................................................6
2.1.3 BOARD STATUS:LOCAL OFFSET 0X0008........................................................................................................7
2.1.4 TIMESTAMP:LOCAL OFFSET 0X000C.............................................................................................................7
2.1.5 CHANNEL TX ALMOST FLAGS:LOCAL OFFSET 0X0010 /0X0020 /0X0030 /0X0040....................................7
2.1.6 CHANNEL RX ALMOST FLAGS:LOCAL OFFSET 0X0014 /0X0024 /0X0034 /0X0044....................................8
2.1.7 CHANNEL FIFO: LOCAL OFFSET 0X0018 /0X0028 /0X0038 /0X0048 ..........................................................8
2.1.8 CHANNEL CONTROL/STATUS:LOCAL OFFSET 0X001C /0X002C /0X003C /0X004C....................................8
2.1.9 CHANNEL SYNC DETECT BYTE:LOCAL OFFSET 0X0050 /0X0054 /0X0058 /0X005C..................................9
2.1.10 INTERRUPT REGISTERS...................................................................................................................................9
2.1.11 INTERRUPT CONTROL:LOCAL OFFSET 0X0060............................................................................................10
2.1.12 INTERRUPT STATUS/CLEAR:LOCAL OFFSET 0X0064...................................................................................10
2.1.13 INTERRUPT EDGE/LEVEL:LOCAL OFFSET 0X0068 ......................................................................................11
2.1.14 INTERRUPT HI/LO:LOCAL OFFSET 0X006C.................................................................................................11
2.1.15 CHANNEL PIN SOURCE:LOCAL OFFSET 0X0080 /0X0084 /0X0088 /0X008C............................................11
2.1.16 CHANNEL PIN STATUS:LOCAL OFFSET 0X0090 /0X0094 /0X0098 /0X009C.............................................14
2.1.13 PROGRAMMABLE CLOCK REGISTERS:LOCAL OFFSET 0X00A0 /0X00A4 /0X00A8 /0XAC .......................15
2.1.14 FIFO COUNT REGISTER:LOCAL OFFSET 0X00D0 /0X00D4 /0X00D8 /0X00DC .......................................15
2.1.15 FIFO SIZE REGISTER:LOCAL OFFSET 0X00E0 /0X00E4 /0X00E8 /0X00EC .............................................15
2.1.16 FW TYPE ID REGISTER:LOCAL OFFSET 0X00F8.........................................................................................15
2.1.17 FEATURES REGISTER:LOCAL OFFSET 0X00FC (0X00197AF4)...................................................................16
2.2 UNIVERSAL SERIAL CONTROLLER REGISTERS ..............................................................................................16
2.2.1 USC RESET ..................................................................................................................................................16
2.2.2 8-BIT USC REGISTER ACCESS......................................................................................................................17
2.2.3 USC DATA TRANSFER..................................................................................................................................17
2.2.4 USC REGISTER MEMORY MAP.....................................................................................................................18
CHAPTER 3: PROGRAMMING...........................................................................................................................19
3.0 INTRODUCTION.............................................................................................................................................19
3.1 RESETS.........................................................................................................................................................19
3.2 FIFOS...........................................................................................................................................................19
3.2.1 FIFO FLAGS .................................................................................................................................................19
3.2.2 FIFO COUNTERS ..........................................................................................................................................20
3.2.3 FIFO SIZE ....................................................................................................................................................20

iv Rev NR
3.3 BOARD VS.CHANNEL REGISTERS.................................................................................................................20
3.4 PROGRAMMABLE OSCILLATOR /PROGRAMMABLE CLOCKS .........................................................................21
3.5 CLOCK SETUP...............................................................................................................................................21
3.6 MULTIPROTOCOL TRANSCEIVER CONTROL ..................................................................................................23
3.7 DCE/DTE MODE .........................................................................................................................................23
3.8 LOOPBACK MODES.......................................................................................................................................23
3.9 GENERAL PURPOSE IO .................................................................................................................................24
3.10 INTERRUPTS .................................................................................................................................................24
3.11 PCI DMA.....................................................................................................................................................24
CHAPTER 4: PCI INTERFACE ............................................................................................................................26
4.0 PCI INTERFACE REGISTERS..........................................................................................................................26
4.1 PCI REGISTERS.............................................................................................................................................26
4.1.1 PCI CONFIGURATION REGISTERS..................................................................................................................26
4.1.2 LOCAL CONFIGURATION REGISTERS.............................................................................................................27
4.1.3 RUNTIME REGISTERS....................................................................................................................................27
4.1.4 DMA REGISTERS..........................................................................................................................................27
4.1.4.1 DMA CHANNEL MODE REGISTER:(PCI 0X80 /0X94) .................................................................................27
CHAPTER 5: HARDWARE CONFIGURATION................................................................................................28
5.0 BOARD LAYOUT...........................................................................................................................................28
5.1 BOARD ID JUMPER J2 ..................................................................................................................................28
5.2 TERMINATION RESISTORS.............................................................................................................................29
5.3 LEDS...........................................................................................................................................................29
5.4 INTERFACE CONNECTOR ..............................................................................................................................30
CHAPTER 6: ORDERING OPTIONS...................................................................................................................31
6.0 ORDERING INFORMATION.............................................................................................................................31
6.1 INTERFACE CABLE........................................................................................................................................31
6.2 DEVICE DRIVERS..........................................................................................................................................31
6.3 CUSTOM APPLICATIONS................................................................................................................................31
APPENDIX A: PROGRAMMABLE OSCILLATOR PROGRAMMING .........................................................32
APPENDIX B: FIRMWARE REVISIONS / FEATURES REGISTER ..............................................................35

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CHAPTER 1: INTRODUCTION
1.0 General Description
The PCIe-SIO4BX2 is a four channel serial interface card which provides high speed, full-duplex, multi-protocol
serial capability for PCIe applications. The PCIe-SIO4BX2 combines multi-protocol Dual Universal Serial
Controllers, deep external FIFOs, and software selectable multi-protocol transceivers to provide four fully
independent synchronous/asynchronous serial channels. These features, along with a high performance one lane
PCIe interface engine, give the PCIe-SIO4BX2 unsurpassed performance in a serial interface card.
Features:
One Lane PCI Express (PCIe) Interface
Four Independent RS422/RS485/RS232 Serial Channels
Serial Mode Protocols - Asynchronous, Monosync, Bisync, SDLC, HDLC, Nine-Bit, IEEE 802.3
Synchronous Serial Data Rates up to 10Mbps
Asynchronous Serial Data Rates up to 1Mbps
Independent Transmit and Receive FIFOs for each Serial Channel –32K byte each
Multi-protocol Transceivers support RS422/RS485 and RS232
Parity and CRC detection capability
Programmable Oscillators provide increased flexibility for Baud Rate Clock generation
SCSI type 68 pin front edge I/O Connector
Eight signals per channel, configurable as either DTE or DCE:
3 Serial Clocks (TxC,RxC,AuxC), 2 Serial Data signals (TxD,RxD), CTS, RTS, DCD
Unused signals may be reconfigured as General Purpose IO
Fast RS422/RS485 Differential Cable Transceivers Provide Data Rates up to 10Mbps
RS232 Cable Transceivers Provide Data Rates up to 250kbps
Industry Standard Zilog Z16C30 Multi-Protocol Universal Serial Controllers (USC®)
Standard Cable to four DB25 connectors and Custom Cables available
Available drivers include VxWorks, WinNT, Win2k, WinXP, Linux, and Labview
Industrial Temperature Option Available

2 Rev NR
Functional Diagram:
66MHz
32 bit
PCI
Interface
Control
Logic
32kb
Tx
FIFO
Universal
Serial
Controller
32kb
Rx
FIFO
Prog
Osc
DTE
DCE
Multi-protocol
Transceiver
Chan 1-4
Receiver
Transmitter
PCIe-PCI
Bridge
P1
PCIe Bus
Cable
Interface
68 pin
SCSI
P2
Figure 1-1 Block Diagram of PCIe-SIO4BX2
1.1 Z16C30 Universal Serial Controller
The PCIe-SIO4BX2 is designed around the Z16C30 Universal Serial Controller( USC). The Z16C30 is a dual
channel multi-protocol serial controller which may be software configured to satisfy a wide variety of serial
communications applications. The USC supports most common asynchronous and synchronous serial protocols.
The USC provides many advanced features, including:
Completely independent transmitter and receiver operation
Odd/Even/Space/Mark parity
Two 16-bit or one 32-bit CRC polynomial
Eight Data Encoding methods –NRZ, NRZB, NRZI-Mark, NRZI-Space, Biphase-Mark, Biphase-Space,
Biphase-Level, and Differential Biphase-Level
1.2 Deep Transmit/Receive FIFOs
Data is transferred to/from the serial interface through Transmit and Receive FIFOs. Each of the four serial channels
has an independent Transmit FIFO and a Receive FIFO for a total of eight separate on-board FIFOs. These FIFOs
are always 32k bytes deep. FIFOs allow data transfer to continue to/from the IO interface independent of PCI
interface transfers and software overhead. The required FIFO size may depend on several factors including data
transfer size, required throughput rate, and the software overhead (which will also vary based on OS). Generally,
faster baud rates (greater than 500kbps) will require deeper FIFOs. Deeper FIFOs help ensure no data is lost for
critical systems.

3 Rev NR
The SIO4BX2 provides access to complete FIFO status to optimize data transfers. In addition to Empty and Full
indicators, each FIFO has a programmable Almost Empty Flag and a programmable Almost Full Flag. These FIFO
flags may be used as interrupt sources to monitor FIFO fill levels. In addition, real-time FIFO counters showing the
exact number of words in the FIFO are also provided for each FIFO. By utilizing these FIFO counters, data transfers
can be optimized to efficiently send and receive data.
1.3 Multiprotocol Transceivers
The SIO4BX2 data is transferred over the user interface using high-speed multiprotocol transceivers. These
multiprotocol transceivers are software selectable as RS422/RS485, or RS232 on a per channel basis. Each channel
direction may also be configured as DTE or DCE configuration. This allows for either full duplex or half duplex
configurations.
1.4 PMC/PCI Interface
The control interface to the SIO4BX2 is through the PMC/PCI interface. An industry standard PCI9056 bridge chip
from PLX Technology is used to implement PCI Specification 2.2. The PCI9056 provides the 32bit, 66MHz
(264MBit/sec) interface between the PCI bus and the Local 32 bit bus. It also provides for high-speed DMA
transfers to efficiently move data to and from the board.
1.5 General Purpose IO
Since some signals may not be used in all applications, the SIO4BX2 provides the flexibility to remap unused signals
to be used as general purpose IO. For example, this would allow support for an application requiring DTR/DSR
signals to be implemented on an unused DCD or TxAuxC signals. This also allows signals from unused channels to
be available as general purpose IO.
1.6 Connector Interface
The SIO4BX2 provides a user IO interface through a front-side card edge connector. All four serial channels
interface through this high-density, 68 pin SCSI-3 type connector, and are grouped to simplify separating the cable
into four distinct serial connectors.
Standard cables are available from General Standards in various lengths to adapt the single 68 pin SCSI-3 connector
into four DB25 connectors (one per channel). A standard cable is also available with a single 68 pin SCSI-3
connector on one end and open on the other. This allows the user to add a custom connector (or connect to a
terminal block). General Standards will also work with customers to fabricate custom cables. Consult factory for
details on custom cables.
1.7 New Features
The PCIe-SIO4BX2 has been enhanced with several new features. These include improved receive data status
recording, timestamping of data, flexible FIFO memory allocation, sync/standard channel select, and channel reset.

4 Rev NR
CHAPTER 2: LOCAL SPACE REGISTERS
2.0 Register Map
The SIO4BX2 is accessed through three sets of registers –PCI Registers, USC Registers, and GSC Firmware
Registers. The GSC Firmware Registers and USC Registers are referred to as Local Space Registers and are
described below. The PCI registers are discussed in Chapter 3.
The Local Space Registers are divided into two distinct functional register blocks –the GSC Firmware Registers and
the USC Registers. The GSC Firmware Registers perform the custom board control functions, while the USC
Registers map the Zilog Z16C30 registers into local address space. The register block for each USC channel is
accessed at a unique address range. The table below shows the address mapping for the local space registers.
Local Address Range
Base Address Offset
Register Block Description
0x0000 –0x00FF
0x0000
GSC Firmware Registers
0x0100 –0x013F
0x0100
Channel 1 USC Registers
0x0140 –0x01FF
Reserved
0x0200 –0x023F
0x0200
Channel 2 USC Registers
0x0240 –0x02FF
Reserved
0x0300 –0x033F
0x0300
Channel 3 USC Registers
0x0340 –0x03FF
Reserved
0x0400 –0x043F
0x0400
Channel 4 USC Registers
The GSC Firmware Registers are detailed in Section 2.1. The USC Registers are briefly touched on in Section 2.2 of
this manual, but are described in much greater detail in the Zilog Z16C30 Users Manuals.
2.1 GSC Firmware Registers
The GSC Firmware Registers provide the primary control/status for the SIO4BX2 board. The following table shows
the GSC Firmware Registers.
Offset Address
Size
Access*
Register Name
Default Value (Hex)
0x0000
D32
Read/Write
Firmware Revision
E51001XX
0x0004
D32
Read/Write
Board Control
00000000
0x0008
D32
Read Only
Board Status
000000XX
0x000C
D32
Read/Write
Timestamp
00000000
0x0010
D32
Read/Write
Ch 1 Tx Almost Full/Empty
00070007
0x0014
D32
Read/Write
Ch 1 Rx Almost Full/Empty
00070007
0x0018
D32
Read/Write
Ch l 1 Data FIFO
000000XX
0x001C
D32
Read/Write
Ch 1 Control/Status
0000CC00
0x0020
D32
Read/Write
Ch 2 Tx Almost Full/Empty
00070007
0x0024
D32
Read/Write
Ch 2 Rx Almost Full/Empty
00070007
0x0028
D32
Read/Write
Ch 2 FIFO
000000XX
0x002C
D32
Read/Write
Ch 2 Control/Status
0000CC00
0x0030
D32
Read/Write
Ch 3 Tx Almost Full/Empty
00070007
0x0034
D32
Read/Write
Ch 3 Rx Almost Full/Empty
00070007
0x0038
D32
Read/Write
Ch 3 Data FIFO
000000XX

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0x003C
D32
Read/Write
Ch 3 Control/Status
0000CC00
0x0040
D32
Read/Write
Ch 4 Tx Almost Full/Empty
00070007
0x0044
D32
Read/Write
Ch 4 Rx Almost Full/Empty
00070007
0x0048
D32
Read/Write
Ch 4 Data FIFO
000000XX
0x004C
D32
Read/Write
Ch 4 Control/Status
0000CC00
0x0050
D32
Read/Write
Ch 1 Sync Byte
00000000
0x0054
D32
Read/Write
Ch 2 Sync Byte
00000000
0x0058
D32
Read/Write
Ch 3 Sync Byte
00000000
0x005C
D32
Read/Write
Ch 4 Sync Byte
00000000
0x0060
D32
Read/Write
Interrupt Control
00000000
0x0064
D32
Read/Write
Interrupt Status
00000000
0x0068
D32
Read Only
Interrupt Edge/Level
FFFF7777
0x006C
D32
Read/Write
Interrupt High/Low
FFFFFFFF
0x0070-0x007C
---
--
RESERVED
--------
0x0080
D32
Read/Write
Ch 1Pin Source
00000020
0x0084
D32
Read/Write
Ch 2 Pin Source
00000020
0x0088
D32
Read/Write
Ch 3 Pin Source
00000020
0x008C
D32
Read/Write
Ch 4 Pin Source
00000020
0x0090
D32
Read Only
Ch 1Pin Status
000000XX
0x0094
D32
Read Only
Ch 2 Pin Status
000000XX
0x0098
D32
Read Only
Ch 3 Pin Status
000000XX
0x009C
D32
Read Only
Ch 4 Pin Status
000000XX
0x00A0
D32
Read/Write
Programmable Osc RAM Addr
00000000
0x00A4
D32
Read/Write
Programmable Osc RAM Data 1
00000000
0x00A8
D32
Read/Write
Programmable Osc Control/Status
00000000
0x00AC
D32
Read/Write
Programmable Osc RAM Data 2
00000000
0x00B0-0x00CC
---
--
RESERVED
--------
0x00D0
D32
Read Only
Ch1 FIFO Count
00000000
0x00D4
D32
Read Only
Ch2 FIFO Count
00000000
0x00D8
D32
Read Only
Ch3 FIFO Count
00000000
0x00DC
D32
Read Only
Ch4 FIFO Count
00000000
0x00E0
D32
Read Only
Ch1 FIFO Size
XXXXXXXX
0x00E4
D32
Read Only
Ch2 FIFO Size
XXXXXXXX
0x00E8
D32
Read Only
Ch3 FIFO Size
XXXXXXXX
0x00EC
D32
Read Only
Ch4 FIFO Size
XXXXXXXX
0x00F0-0x00F4
---
--
RESERVED
--------
0x00F8
D32
Read Only
FW Type Register
01010101
0x00FC
D32
Read Only
Features Register
00197AF4
2.1.1 Firmware Revision: Local Offset 0x0000
The Firmware ID register provides version information about the firmware on the board. This is useful for technical
support to identify the firmware version. See Appendix B for more detailed information.
D31:16 HW Board Rev E510 = PCIe-SIO4BX22 Rev NR
D15:8 Firmware Type ID 01 = SIO4B Standard
D7:0 Firmware Revision Firmware Version