General Standards Corporation PCIe-SIO4BX2 User manual

PCIe-SIO4BX2
User’s Manual
Four Channel PCIe High Performance Serial I/O
Featuring RS422/RS485/RS232 Software Configurable Transceivers
and 32K Byte FIFO Buffers (256K Byte total)
RS-485
RS-422/V.11
RS-232/V.28
General Standards Corporation
8302A Whitesburg Drive
Huntsville, AL 35802
Phone: [phone]
Fax: [phone]
URL: www.generalstandards.com
E-mail: [email protected]
Revision NR

i Rev NR
PREFACE
Revision History
1. Rev NR –Mar 2013 –Original rev from PMC66-SIO4BXR manual.
Additional copies of this manual or other General Standards Corporation literature may be obtained
from:
General Standards Corporation
8302A Whitesburg Drive
Huntsville, Alabama 35802
Telephone: [phone]
Fax: [phone]
URL: www.generalstandards.com
The information in this document is subject to change without notice.
General Standards Corporation makes no warranty of any kind with regard to this material, including,
but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Although
extensive editing and reviews are performed before release to ECO control, General Standards
Corporation assumes no responsibility for any errors that may exist in this document. No commitment is
made to update or keep current the information contained in this document.
General Standards Corporation does not assume any liability arising out of the application or use of any
product or circuit described herein, nor is any license conveyed under any patent right of any rights of
others.
General Standards Corporation assumes no responsibility resulting from omissions or errors in this
manual, or from the use of information contained herein.
General Standards Corporation reserves the right to make any changes, without notice, to this product
to improve reliability, performance, function, or design.
All rights reserved
No parts of this document may be copied or reproduced in any form or by any means without prior written
consent of General Standards Corporation.
Copyright © 2013 General Standards Corporation

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RELATED PUBLICATIONS
ZILOG Z16C30 USC® User’s Manual
ZILOG Z16C30 USC® Product Specifications Databook
ZILOG, Inc.
210 East Hacienda Ave.
Campbell, CA 95008-6600
[phone]
http://www.zilog.com/
PLX PCI 9056 Data Book
PLX Technology Inc.
390 Potrero Avenue
Sunnyvale, CA 4085
[phone]
http://www.plxtech.com/
EIA-422-A –Electrical Characteristics of Balanced Voltage Digital Interface Circuits
(EIA order number EIA-RS-422A)
EIA-485 –Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital
Multipoint Systems
(EIA order number EIA-RS-485)
EIA Standards and Publications can be purchased from:
GLOBAL ENGINEERING DOCUMENTS
15 Inverness Way East
Englewood, CO 80112
Phone: [phone]
http://global.ihs.com/
PCI Local Bus Specification Revision 2.2 December 18, 1998
Copies of PCI specifications available from:
PCI Special Interest Group
NE 2575 Kathryn Street, #17
Hillsboro, OR 97124
http://www.pcisig.com/

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TABLE OF CONTENTS
CHAPTER 1: INTRODUCTION..............................................................................................................................1
1.0 GENERAL DESCRIPTION..................................................................................................................................1
1.1 Z16C30 UNIVERSAL SERIAL CONTROLLER ....................................................................................................2
1.2 DEEP TRANSMIT/RECEIVE FIFOS...................................................................................................................2
1.3 MULTIPROTOCOL TRANSCEIVERS...................................................................................................................3
1.4 PMC/PCI INTERFACE.....................................................................................................................................3
1.5 GENERAL PURPOSE IO ...................................................................................................................................3
1.6 CONNECTOR INTERFACE ................................................................................................................................3
1.7 NEW FEATURES..............................................................................................................................................3
CHAPTER 2: LOCAL SPACE REGISTERS..........................................................................................................4
2.0 REGISTER MAP...............................................................................................................................................4
2.1 GSC FIRMWARE REGISTERS...........................................................................................................................4
2.1.1 FIRMWARE REVISION:LOCAL OFFSET 0X0000..............................................................................................5
2.1.2 BOARD CONTROL:LOCAL OFFSET 0X0004....................................................................................................6
2.1.3 BOARD STATUS:LOCAL OFFSET 0X0008........................................................................................................7
2.1.4 TIMESTAMP:LOCAL OFFSET 0X000C.............................................................................................................7
2.1.5 CHANNEL TX ALMOST FLAGS:LOCAL OFFSET 0X0010 /0X0020 /0X0030 /0X0040....................................7
2.1.6 CHANNEL RX ALMOST FLAGS:LOCAL OFFSET 0X0014 /0X0024 /0X0034 /0X0044....................................8
2.1.7 CHANNEL FIFO: LOCAL OFFSET 0X0018 /0X0028 /0X0038 /0X0048 ..........................................................8
2.1.8 CHANNEL CONTROL/STATUS:LOCAL OFFSET 0X001C /0X002C /0X003C /0X004C....................................8
2.1.9 CHANNEL SYNC DETECT BYTE:LOCAL OFFSET 0X0050 /0X0054 /0X0058 /0X005C..................................9
2.1.10 INTERRUPT REGISTERS...................................................................................................................................9
2.1.11 INTERRUPT CONTROL:LOCAL OFFSET 0X0060............................................................................................10
2.1.12 INTERRUPT STATUS/CLEAR:LOCAL OFFSET 0X0064...................................................................................10
2.1.13 INTERRUPT EDGE/LEVEL:LOCAL OFFSET 0X0068 ......................................................................................11
2.1.14 INTERRUPT HI/LO:LOCAL OFFSET 0X006C.................................................................................................11
2.1.15 CHANNEL PIN SOURCE:LOCAL OFFSET 0X0080 /0X0084 /0X0088 /0X008C............................................11
2.1.16 CHANNEL PIN STATUS:LOCAL OFFSET 0X0090 /0X0094 /0X0098 /0X009C.............................................14
2.1.13 PROGRAMMABLE CLOCK REGISTERS:LOCAL OFFSET 0X00A0 /0X00A4 /0X00A8 /0XAC .......................15
2.1.14 FIFO COUNT REGISTER:LOCAL OFFSET 0X00D0 /0X00D4 /0X00D8 /0X00DC .......................................15
2.1.15 FIFO SIZE REGISTER:LOCAL OFFSET 0X00E0 /0X00E4 /0X00E8 /0X00EC .............................................15
2.1.16 FW TYPE ID REGISTER:LOCAL OFFSET 0X00F8.........................................................................................15
2.1.17 FEATURES REGISTER:LOCAL OFFSET 0X00FC (0X00197AF4)...................................................................16
2.2 UNIVERSAL SERIAL CONTROLLER REGISTERS ..............................................................................................16
2.2.1 USC RESET ..................................................................................................................................................16
2.2.2 8-BIT USC REGISTER ACCESS......................................................................................................................17
2.2.3 USC DATA TRANSFER..................................................................................................................................17
2.2.4 USC REGISTER MEMORY MAP.....................................................................................................................18
CHAPTER 3: PROGRAMMING...........................................................................................................................19
3.0 INTRODUCTION.............................................................................................................................................19
3.1 RESETS.........................................................................................................................................................19
3.2 FIFOS...........................................................................................................................................................19
3.2.1 FIFO FLAGS .................................................................................................................................................19
3.2.2 FIFO COUNTERS ..........................................................................................................................................20
3.2.3 FIFO SIZE ....................................................................................................................................................20

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3.3 BOARD VS.CHANNEL REGISTERS.................................................................................................................20
3.4 PROGRAMMABLE OSCILLATOR /PROGRAMMABLE CLOCKS .........................................................................21
3.5 CLOCK SETUP...............................................................................................................................................21
3.6 MULTIPROTOCOL TRANSCEIVER CONTROL ..................................................................................................23
3.7 DCE/DTE MODE .........................................................................................................................................23
3.8 LOOPBACK MODES.......................................................................................................................................23
3.9 GENERAL PURPOSE IO .................................................................................................................................24
3.10 INTERRUPTS .................................................................................................................................................24
3.11 PCI DMA.....................................................................................................................................................24
CHAPTER 4: PCI INTERFACE ............................................................................................................................26
4.0 PCI INTERFACE REGISTERS..........................................................................................................................26
4.1 PCI REGISTERS.............................................................................................................................................26
4.1.1 PCI CONFIGURATION REGISTERS..................................................................................................................26
4.1.2 LOCAL CONFIGURATION REGISTERS.............................................................................................................27
4.1.3 RUNTIME REGISTERS....................................................................................................................................27
4.1.4 DMA REGISTERS..........................................................................................................................................27
4.1.4.1 DMA CHANNEL MODE REGISTER:(PCI 0X80 /0X94) .................................................................................27
CHAPTER 5: HARDWARE CONFIGURATION................................................................................................28
5.0 BOARD LAYOUT...........................................................................................................................................28
5.1 BOARD ID JUMPER J2 ..................................................................................................................................28
5.2 TERMINATION RESISTORS.............................................................................................................................29
5.3 LEDS...........................................................................................................................................................29
5.4 INTERFACE CONNECTOR ..............................................................................................................................30
CHAPTER 6: ORDERING OPTIONS...................................................................................................................31
6.0 ORDERING INFORMATION.............................................................................................................................31
6.1 INTERFACE CABLE........................................................................................................................................31
6.2 DEVICE DRIVERS..........................................................................................................................................31
6.3 CUSTOM APPLICATIONS................................................................................................................................31
APPENDIX A: PROGRAMMABLE OSCILLATOR PROGRAMMING .........................................................32
APPENDIX B: FIRMWARE REVISIONS / FEATURES REGISTER ..............................................................35

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CHAPTER 1: INTRODUCTION
1.0 General Description
The PCIe-SIO4BX2 is a four channel serial interface card which provides high speed, full-duplex, multi-protocol
serial capability for PCIe applications. The PCIe-SIO4BX2 combines multi-protocol Dual Universal Serial
Controllers, deep external FIFOs, and software selectable multi-protocol transceivers to provide four fully
independent synchronous/asynchronous serial channels. These features, along with a high performance one lane
PCIe interface engine, give the PCIe-SIO4BX2 unsurpassed performance in a serial interface card.
Features:
One Lane PCI Express (PCIe) Interface
Four Independent RS422/RS485/RS232 Serial Channels
Serial Mode Protocols - Asynchronous, Monosync, Bisync, SDLC, HDLC, Nine-Bit, IEEE 802.3
Synchronous Serial Data Rates up to 10Mbps
Asynchronous Serial Data Rates up to 1Mbps
Independent Transmit and Receive FIFOs for each Serial Channel –32K byte each
Multi-protocol Transceivers support RS422/RS485 and RS232
Parity and CRC detection capability
Programmable Oscillators provide increased flexibility for Baud Rate Clock generation
SCSI type 68 pin front edge I/O Connector
Eight signals per channel, configurable as either DTE or DCE:
3 Serial Clocks (TxC,RxC,AuxC), 2 Serial Data signals (TxD,RxD), CTS, RTS, DCD
Unused signals may be reconfigured as General Purpose IO
Fast RS422/RS485 Differential Cable Transceivers Provide Data Rates up to 10Mbps
RS232 Cable Transceivers Provide Data Rates up to 250kbps
Industry Standard Zilog Z16C30 Multi-Protocol Universal Serial Controllers (USC®)
Standard Cable to four DB25 connectors and Custom Cables available
Available drivers include VxWorks, WinNT, Win2k, WinXP, Linux, and Labview
Industrial Temperature Option Available

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Functional Diagram:
66MHz
32 bit
PCI
Interface
Control
Logic
32kb
Tx
FIFO
Universal
Serial
Controller
32kb
Rx
FIFO
Prog
Osc
DTE
DCE
Multi-protocol
Transceiver
Chan 1-4
Receiver
Transmitter
PCIe-PCI
Bridge
P1
PCIe Bus
Cable
Interface
68 pin
SCSI
P2
Figure 1-1 Block Diagram of PCIe-SIO4BX2
1.1 Z16C30 Universal Serial Controller
The PCIe-SIO4BX2 is designed around the Z16C30 Universal Serial Controller( USC). The Z16C30 is a dual
channel multi-protocol serial controller which may be software configured to satisfy a wide variety of serial
communications applications. The USC supports most common asynchronous and synchronous serial protocols.
The USC provides many advanced features, including:
Completely independent transmitter and receiver operation
Odd/Even/Space/Mark parity
Two 16-bit or one 32-bit CRC polynomial
Eight Data Encoding methods –NRZ, NRZB, NRZI-Mark, NRZI-Space, Biphase-Mark, Biphase-Space,
Biphase-Level, and Differential Biphase-Level
1.2 Deep Transmit/Receive FIFOs
Data is transferred to/from the serial interface through Transmit and Receive FIFOs. Each of the four serial channels
has an independent Transmit FIFO and a Receive FIFO for a total of eight separate on-board FIFOs. These FIFOs
are always 32k bytes deep. FIFOs allow data transfer to continue to/from the IO interface independent of PCI
interface transfers and software overhead. The required FIFO size may depend on several factors including data
transfer size, required throughput rate, and the software overhead (which will also vary based on OS). Generally,
faster baud rates (greater than 500kbps) will require deeper FIFOs. Deeper FIFOs help ensure no data is lost for
critical systems.

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The SIO4BX2 provides access to complete FIFO status to optimize data transfers. In addition to Empty and Full
indicators, each FIFO has a programmable Almost Empty Flag and a programmable Almost Full Flag. These FIFO
flags may be used as interrupt sources to monitor FIFO fill levels. In addition, real-time FIFO counters showing the
exact number of words in the FIFO are also provided for each FIFO. By utilizing these FIFO counters, data transfers
can be optimized to efficiently send and receive data.
1.3 Multiprotocol Transceivers
The SIO4BX2 data is transferred over the user interface using high-speed multiprotocol transceivers. These
multiprotocol transceivers are software selectable as RS422/RS485, or RS232 on a per channel basis. Each channel
direction may also be configured as DTE or DCE configuration. This allows for either full duplex or half duplex
configurations.
1.4 PMC/PCI Interface
The control interface to the SIO4BX2 is through the PMC/PCI interface. An industry standard PCI9056 bridge chip
from PLX Technology is used to implement PCI Specification 2.2. The PCI9056 provides the 32bit, 66MHz
(264MBit/sec) interface between the PCI bus and the Local 32 bit bus. It also provides for high-speed DMA
transfers to efficiently move data to and from the board.
1.5 General Purpose IO
Since some signals may not be used in all applications, the SIO4BX2 provides the flexibility to remap unused signals
to be used as general purpose IO. For example, this would allow support for an application requiring DTR/DSR
signals to be implemented on an unused DCD or TxAuxC signals. This also allows signals from unused channels to
be available as general purpose IO.
1.6 Connector Interface
The SIO4BX2 provides a user IO interface through a front-side card edge connector. All four serial channels
interface through this high-density, 68 pin SCSI-3 type connector, and are grouped to simplify separating the cable
into four distinct serial connectors.
Standard cables are available from General Standards in various lengths to adapt the single 68 pin SCSI-3 connector
into four DB25 connectors (one per channel). A standard cable is also available with a single 68 pin SCSI-3
connector on one end and open on the other. This allows the user to add a custom connector (or connect to a
terminal block). General Standards will also work with customers to fabricate custom cables. Consult factory for
details on custom cables.
1.7 New Features
The PCIe-SIO4BX2 has been enhanced with several new features. These include improved receive data status
recording, timestamping of data, flexible FIFO memory allocation, sync/standard channel select, and channel reset.

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CHAPTER 2: LOCAL SPACE REGISTERS
2.0 Register Map
The SIO4BX2 is accessed through three sets of registers –PCI Registers, USC Registers, and GSC Firmware
Registers. The GSC Firmware Registers and USC Registers are referred to as Local Space Registers and are
described below. The PCI registers are discussed in Chapter 3.
The Local Space Registers are divided into two distinct functional register blocks –the GSC Firmware Registers and
the USC Registers. The GSC Firmware Registers perform the custom board control functions, while the USC
Registers map the Zilog Z16C30 registers into local address space. The register block for each USC channel is
accessed at a unique address range. The table below shows the address mapping for the local space registers.
Local Address Range
Base Address Offset
Register Block Description
0x0000 –0x00FF
0x0000
GSC Firmware Registers
0x0100 –0x013F
0x0100
Channel 1 USC Registers
0x0140 –0x01FF
Reserved
0x0200 –0x023F
0x0200
Channel 2 USC Registers
0x0240 –0x02FF
Reserved
0x0300 –0x033F
0x0300
Channel 3 USC Registers
0x0340 –0x03FF
Reserved
0x0400 –0x043F
0x0400
Channel 4 USC Registers
The GSC Firmware Registers are detailed in Section 2.1. The USC Registers are briefly touched on in Section 2.2 of
this manual, but are described in much greater detail in the Zilog Z16C30 Users Manuals.
2.1 GSC Firmware Registers
The GSC Firmware Registers provide the primary control/status for the SIO4BX2 board. The following table shows
the GSC Firmware Registers.
Offset Address
Size
Access*
Register Name
Default Value (Hex)
0x0000
D32
Read/Write
Firmware Revision
E51001XX
0x0004
D32
Read/Write
Board Control
00000000
0x0008
D32
Read Only
Board Status
000000XX
0x000C
D32
Read/Write
Timestamp
00000000
0x0010
D32
Read/Write
Ch 1 Tx Almost Full/Empty
00070007
0x0014
D32
Read/Write
Ch 1 Rx Almost Full/Empty
00070007
0x0018
D32
Read/Write
Ch l 1 Data FIFO
000000XX
0x001C
D32
Read/Write
Ch 1 Control/Status
0000CC00
0x0020
D32
Read/Write
Ch 2 Tx Almost Full/Empty
00070007
0x0024
D32
Read/Write
Ch 2 Rx Almost Full/Empty
00070007
0x0028
D32
Read/Write
Ch 2 FIFO
000000XX
0x002C
D32
Read/Write
Ch 2 Control/Status
0000CC00
0x0030
D32
Read/Write
Ch 3 Tx Almost Full/Empty
00070007
0x0034
D32
Read/Write
Ch 3 Rx Almost Full/Empty
00070007
0x0038
D32
Read/Write
Ch 3 Data FIFO
000000XX

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0x003C
D32
Read/Write
Ch 3 Control/Status
0000CC00
0x0040
D32
Read/Write
Ch 4 Tx Almost Full/Empty
00070007
0x0044
D32
Read/Write
Ch 4 Rx Almost Full/Empty
00070007
0x0048
D32
Read/Write
Ch 4 Data FIFO
000000XX
0x004C
D32
Read/Write
Ch 4 Control/Status
0000CC00
0x0050
D32
Read/Write
Ch 1 Sync Byte
00000000
0x0054
D32
Read/Write
Ch 2 Sync Byte
00000000
0x0058
D32
Read/Write
Ch 3 Sync Byte
00000000
0x005C
D32
Read/Write
Ch 4 Sync Byte
00000000
0x0060
D32
Read/Write
Interrupt Control
00000000
0x0064
D32
Read/Write
Interrupt Status
00000000
0x0068
D32
Read Only
Interrupt Edge/Level
FFFF7777
0x006C
D32
Read/Write
Interrupt High/Low
FFFFFFFF
0x0070-0x007C
---
--
RESERVED
--------
0x0080
D32
Read/Write
Ch 1Pin Source
00000020
0x0084
D32
Read/Write
Ch 2 Pin Source
00000020
0x0088
D32
Read/Write
Ch 3 Pin Source
00000020
0x008C
D32
Read/Write
Ch 4 Pin Source
00000020
0x0090
D32
Read Only
Ch 1Pin Status
000000XX
0x0094
D32
Read Only
Ch 2 Pin Status
000000XX
0x0098
D32
Read Only
Ch 3 Pin Status
000000XX
0x009C
D32
Read Only
Ch 4 Pin Status
000000XX
0x00A0
D32
Read/Write
Programmable Osc RAM Addr
00000000
0x00A4
D32
Read/Write
Programmable Osc RAM Data 1
00000000
0x00A8
D32
Read/Write
Programmable Osc Control/Status
00000000
0x00AC
D32
Read/Write
Programmable Osc RAM Data 2
00000000
0x00B0-0x00CC
---
--
RESERVED
--------
0x00D0
D32
Read Only
Ch1 FIFO Count
00000000
0x00D4
D32
Read Only
Ch2 FIFO Count
00000000
0x00D8
D32
Read Only
Ch3 FIFO Count
00000000
0x00DC
D32
Read Only
Ch4 FIFO Count
00000000
0x00E0
D32
Read Only
Ch1 FIFO Size
XXXXXXXX
0x00E4
D32
Read Only
Ch2 FIFO Size
XXXXXXXX
0x00E8
D32
Read Only
Ch3 FIFO Size
XXXXXXXX
0x00EC
D32
Read Only
Ch4 FIFO Size
XXXXXXXX
0x00F0-0x00F4
---
--
RESERVED
--------
0x00F8
D32
Read Only
FW Type Register
01010101
0x00FC
D32
Read Only
Features Register
00197AF4
2.1.1 Firmware Revision: Local Offset 0x0000
The Firmware ID register provides version information about the firmware on the board. This is useful for technical
support to identify the firmware version. See Appendix B for more detailed information.
D31:16 HW Board Rev E510 = PCIe-SIO4BX22 Rev NR
D15:8 Firmware Type ID 01 = SIO4B Standard
D7:0 Firmware Revision Firmware Version

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2.1.2 Board Control: Local Offset 0x0004
The Board Control Register defines the general control functions for the board.
D31 Board Reset
1 = Reset all Local Registers and FIFOs to their default values
Notes: This bit will automatically clear to 0 following the board reset.
Board Reset will NOT reset programmable oscillator.
Following a Board Reset, Reset-In-Progress bit (D31) of the Board Status
Register will remain set until the Board reset is complete;
D30 RESERVED (Debug Test)
D29 FIFO Test (Debug Test)
0 = Normal Mode - FIFO Write to Tx FIFO / FIFO Read from Rx FIFO
1 = Test Mode - FIFO Write to Rx FIFO / FIFO Read from Tx FIFO
D28:27 FIFO Allocation (Unused)
D26 RESERVED
D25 LED D1
1 = Turn on Red LED D1
D24 LED D1
1 = Turn on Green LED D1
D23 Timestamp Clear
0 = timestamp counter is enabled
1 = reset timestamp count to zero
D22 Timestamp Source
0 = timestamp counter runs off internal 1us clock
D21:9 RESERVED
D8 Rx FIFO Stop on Full
1 = If Rx FIFO becomes full, stop receiving data (disable receiver)
D7 Demand Mode DMA Channel 1 Single Cycle Disable
D6:4 Demand Mode DMA Channel 1 Request
000 = Ch1 Rx
100 = Ch1 Tx
010 = Ch2 Rx
110 = Ch2 Tx
001 = Ch3 Rx
101 = Ch3 Tx
011 = Ch4 Rx
111 = Ch4 Tx
D3 Demand Mode DMA Channel 0 Single Cycle Disable
D2:0 Demand Mode DMA Channel 0 Request
000 = Ch1 Rx
100 = Ch1 Tx
010 = Ch2 Rx
110 = Ch2 Tx
001 = Ch3 Rx
101 = Ch3 Tx
011 = Ch4 Rx
111 = Ch4 Tx

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2.1.3 Board Status: Local Offset 0x0008
The Board Status Register gives general overall status for a board. The Board Jumpers (D1:D0) are physical
jumpers which can be used to distinguish between boards if multiple SIO4 boards are present in a system.
D31:9 RESERVED
D8 0 = Standard
1 = Sync
D7:D6 RESERVED
D5:D4 FIFO Size
10 = 256K
D3:D0 Board Jumper (J2)
D3 Board ID4
0=J2:7-J2:8 jumper installed
D2 Board ID3
0=J2:5-J2:6 jumper installed
D1 Board ID2
0=J2:3-J2:4 jumper installed
D0 Board ID1
0=J2:1-J2:2 jumper installed
2.1.4 Timestamp: Local Offset 0x000C
The timestamp will add a 24 bit timestamp value for each data value in the data stream.
D31:24 RESERVED
D23:0 Current timestamp value
2.1.5 Channel TXAlmost Flags: Local Offset 0x0010 / 0x0020 / 0x0030 / 0x0040
Defines the Almost Full and Almost Empty Flags for the Tx FIFO. The Almost Full/Empty Flags are status bits in
the Channel Control/Status Register, and are edge-triggered interrupt sources to the Interrupt Registers.
D31:16 TX Almost Full Flag Value
Number of words from FIFO Full when the Almost Full Flag will be asserted (i.e.
FIFO contains {FIFO Size –Almost Full Value} words or more.)
D15:0 TX Almost Empty Flag Value
Number of words from FIFO Empty when the Almost Empty Flag will be asserted

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2.1.6 Channel RX Almost Flags: Local Offset 0x0014 / 0x0024 / 0x0034 / 0x0044
Defines the Almost Full and Almost Empty Flags for the Tx FIFO. The Almost Full/Empty Flags are status bits in
the Channel Control/Status Register, and are edge-triggered interrupt sources to the Interrupt Registers.
D31:16 RX Almost Full Flag Value
Number of words from FIFO Full when the Almost Full Flag will be asserted
(i.e. FIFO contains {FIFO Size –Almost Full Value} words or more.)
D15:0 RX Almost Empty Flag Value
Number of words from FIFO Empty when the Almost Empty Flag will be asserted
2.1.7 Channel FIFO: Local Offset 0x0018 / 0x0028 / 0x0038 / 0x0048
The Channel FIFO Register passes serial data to/from the serial controller. The same register is used to access both
the Transmit FIFO (writes) and Receive FIFO (reads).
D31:8 RESERVED
D7:0 Channel FIFO Data
2.1.8 Channel Control/Status: Local Offset 0x001C / 0x002C / 0x003C / 0x004C
The Channel Control/Status Register provides the reset functions and data transceiver enable controls, and the FIFO
Flag status for each channel.
D31:24 RESERVED
D23:20 LED Control
Each Channel controls 1 red/green LED on the back of the PCB. See Section 5.3 for
more detailed information about the LEDs.
D19 RESERVED
D18:8 Channel Status Bits
D18 Rx FIFO Underflow
D17 Tx FIFO Overflow (Latched)
D16 Rx FIFO Overflow (Latched)
1= Rx Data was lost due to Rx Overflow.
Note: This bit is latched. Write D16=1 to clear.
D15 Rx FIFO Full Flag Lo (0 = Rx FIFO Full)
D14 Rx FIFO Almost Full Flag Lo (0 = Rx FIFO Almost Full)
D13 Rx FIFO Almost Empty Flag Lo (0 = Rx FIFO Almost Empty)
D12 Rx FIFO Empty Flag Lo (0 = Rx FIFO Empty)
D11 Tx FIFO Full Flag Lo (0 = Tx FIFO Full)
D10 Tx FIFO Almost Full Flag Lo (0 = Tx FIFO Almost Full)
D9 Tx FIFO Almost Empty Flag Lo (0 = Tx FIFO Almost Empty)
D8 Tx FIFO Empty Flag Lo (0 = Tx FIFO Empty)

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D7:0 Channel Control Bits
D7 1 = Reset USC ((Pulsed - will automatically clear to ‘0’)
Notes:
Following a USC Reset, the next access to the USC must be a write of 0x00 to Local
Offset 0x100 (Ch1/2) or Local Offset 0x300 (Ch3/4).
Since two channels share each USC (Ch1 & Ch2, Ch3 & Ch4), resetting a USC will
affect both channel.
D6 1 = Reset Channel (Pulsed - will automatically clear to ‘0’)
D5:D4 RESERVED (FIFO Rx/Tx Allocation )
D3 Receive Status Word Enable
1 = Receive status word (RSR) is saved in data stream with every received data word.
D2 Timestamp Enable
1 = 24-bit timestamp word is saved in data stream with every received data word.
D1 1 = Reset Channel Rx FIFO (Pulsed - will automatically clear to ‘0’)
D0 1 = Reset Channel Tx FIFO (Pulsed - will automatically clear to ‘0’).
2.1.9 Channel Sync Detect Byte: Local Offset 0x0050 / 0x0054 / 0x0058 / 0x005C
The Sync Detect Byte allows an interrupt to be generated when the received data matches the Sync Detect Byte.
D31:8 RESERVED
D7:0Channel Sync Detect Byte
If the data being loaded into the Receive FIFO matches this data byte, an interrupt request
(Channel Sync Detect IRQ) will be generated. The interrupt source must be enabled in
the Interrupt Control Register in order for an interrupt to be generated.
2.1.10 Interrupt Registers
There are 32 on-board interrupt sources (in addition to USC interrupts and PLX interrupts) which may be
individually enabled. Four interrupt registers control the on-board interrupts –Interrupt Control, Interrupt Status,
Interrupt Edge/Level, and Interrupt Hi/Lo. The 32 Interrupt sources are:
IRQ #
Source
Default Level
Alternate Level
IRQ0
Channel 1 Sync Detected
Rising Edge
NONE
IRQ1
Channel 1 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ2
Channel 1 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ3
Channel 1 USC Interrupt
Level Hi
NONE
IRQ4
Channel 2 Sync Detected
Rising Edge
NONE
IRQ5
Channel 2 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ6
Channel 2 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ7
Channel 2 USC Interrupt
Level Hi
NONE
IRQ8
Channel 3 Sync Detected
Rising Edge
NONE
IRQ9
Channel 3 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ10
Channel 3 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ11
Channel 3 USC Interrupt
Level Hi
NONE
IRQ12
Channel 4 Sync Detected
Rising Edge
NONE
IRQ13
Channel 4 Tx FIFO Almost Empty
Rising Edge
Falling Edge

10 Rev NR
IRQ14
Channel 4 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ15
Channel 4 USC Interrupt
Level Hi
NONE
IRQ16
Channel 1 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ17
Channel 1 Tx FIFO Full
Rising Edge
Falling Edge
IRQ18
Channel 1 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ19
Channel 1 Rx FIFO Full
Rising Edge
Falling Edge
IRQ20
Channel 2 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ21
Channel 2 Tx FIFO Full
Rising Edge
Falling Edge
IRQ22
Channel 2 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ23
Channel 2 Rx FIFO Full
Rising Edge
Falling Edge
IRQ24
Channel 3 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ25
Channel 3 Tx FIFO Full
Rising Edge
Falling Edge
IRQ26
Channel 3 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ27
Channel 3 Rx FIFO Full
Rising Edge
Falling Edge
IRQ28
Channel 4 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ29
Channel 4 Tx FIFO Full
Rising Edge
Falling Edge
IRQ30
Channel 4 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ31
Channel 4 Rx FIFO Full
Rising Edge
Falling Edge
For all interrupt registers, the IRQ source (IRQ31:IRQ0) will correspond to the respective data bit (D31:D0) of each
register. (D0 = IRQ0, D1 = IRQ1, …D31 = IRQ31.)
All FIFO interrupts are edge triggered active high. This means that an interrupt will be asserted (assuming it is
enabled) when a FIFO Flag transitions from FALSE to TRUE (rising edge triggered) or TRUE to FALSE (falling
edge). For example: If Tx FIFO Empty Interrupt is set for Rising Edge Triggered, the interrupt will occur when the
FIFO transitions from NOT EMPTY to EMPTY. Likewise, if Tx FIFO Empty Interrupt is set as Falling Edge
Triggered, the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY.
All Interrupt Sources share a single interrupt request back to the PCI9056 PLX chip. Likewise, all USC interrupt
sources share a single interrupt request back to the interrupt controller and must be further qualified in the USC.
2.1.11 Interrupt Control: Local Offset 0x0060
The Interrupt Control register individually enables each interrupt source. A ‘1’ enables each interrupt source; a ‘0’
disables. An interrupt source must be enabled for an interrupt to be generated.
2.1.12 Interrupt Status/Clear: Local Offset 0x0064
The Interrupt Status Register shows the status of each respective interrupt source. If an interrupt source is enabled in
the Interrupt Control Register, a ‘1’ in the Interrupt Status Register indicates the respective interrupt has occurred.
The interrupt source will remain latched until the interrupt is cleared, either by writing to the Interrupt Status/Clear
Register with a ‘1’ in the respective interrupt bit position, or the interrupt is disabled in the Interrupt Control register.
If an interrupt source is not asserted or the interrupt is not enabled, writing a ‘1’ to that bit in the Interrupt
Status/Clear Register will have no effect on the interrupt.
If the interrupt source is a level triggered interrupt (USC interrupt), the interrupt status may still be ‘1’ even if the
interrupt is disabled. This indicates the interrupt condition is true, regardless of whether the interrupt is enabled.

11 Rev NR
Likewise, if a level interrupt is enabled and the interrupt source is true, the interrupt status will be reasserted
immediately after clearing the interrupt, and an additional interrupt will be requested.
2.1.13 Interrupt Edge/Level: Local Offset 0x0068
The Interrupt Edge Register is an information only (read only) register. This register can be used by a generic driver
to determine if the interrupt source is edge or level triggered. Only the USC interrupts are level triggered. All other
interrupt sources on the SIO4BX2 are edge triggered.
2.1.14 Interrupt Hi/Lo: Local Offset 0x006C
The Interrupt Edge Register is an information only register which denotes all interrupt sources as edge triggered.
The Interrupt Hi/Lo Register defines each interrupt source as rising edge or falling edge. For example, a rising edge
of the TX Empty source will generate an interrupt when the TX FIFO becomes empty. Defining the source as falling
edge will trigger an interrupt when the TX FIFO becomes “NOT Empty”.
2.1.15 Channel Pin Source: Local Offset 0x0080 / 0x0084 / 0x0088 / 0x008C
The Channel Pin Source Register configures the Output source for the Clocks, Data, RTS, and DCD outputs.
31
30
29
28
27
26
25
24
Transceiver
Enable
Termination
Disable
Loopback
Enable
DCE/DTE
Mode
Transceiver Protocol Mode
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
TxAuxC
Source
TxD
Source
Unused
DCD
Source
RTS
Source
USC_DCD
Direction
USC_CTS
Direction
TxC
Source
USC_RXC
Source
USC_TxC
Source
LB
X
XD
Pin Source Register
D31 Cable Transceiver Enable
Setting this bit turns on the cable transceivers. If this bit is cleared, the transceivers are tristated.
D30 Termination Disable
For RS422/RS485, the receive signals (RxC, RxD, RxAuxC, CTS, and DCD) have built in
termination at the transceivers. These internal terminations may be disabled to allow external
terminations (or no terminations) to be used. Setting this bit will disable the internal transceiver
termination resistors.
D29 External Loopback Mode
When DCE/DTE Mode is enabled (Bit D31=1), this bit will automatically loopback the TxC/RxC,
TxD/RxD, and RTS/CTS signals at the cable (transceivers enabled). This allows the transceivers
to be tested in a standalone mode.
Notes:
The DCE/DTE mode will select the set of signals (DCE or DTE) to be looped back
Since the transceivers will be enabled in this mode, all external cables should be
disconnected to prevent interference from external sources.

12 Rev NR
D28 DCE/DTE Mode
When DCE/DTE Mode is enabled (Bit D31=1), this bit set the mode to DCE (1) or DTE (0).
DCE/DTE mode changes the direction of the signals at the IO Connector.
D27:24 Transceiver Protocol Mode
D27
D26
D25
D24
Transceiver Mode
0
0
0
0
RS-422 / RS-485
0
0
0
1
RESERVED
0
0
1
0
RS-232
0
0
1
1
RESERVED
0
1
X
X
RESERVED
1
X
X
X
RESERVED
D23 Internal Loopback Mode
When DCE/DTE Mode is enabled (Bit D31=1), this bit will automatically loopback the TxC/RxC,
TxD/RxD, and RTS/CTS signals internal to the board.
D22 Reserved
D21:19 Cable TxD Output Control
Allows TxD output to be used as a general purpose output.
D21
D20
D19
TxD Source
0
0
X
USC_TxD
0
0
0
Output ‘0’
0
1
1
Output ‘1’
1
0
0
Differential Biphase Mark
1
0
1
Differential Biphase Space
1
1
0
Level
1
1
1
Differential Biphase Level
D18:17 Cable TxAuxC Output Control
Defines the Clock Source for the TxAuxC signal to the IO connector.
D18
D17
TxAuxC Source
0
0
Tristate
0
1
On-board Programmable Clock
1
0
Output ‘0’
1
1
Output ‘1’
D16:15 Cable DCD Output Source
D16
D15
Output Source
Notes
0
0
USC_DCD Output
USC_DCD field (D12:D11) must equal ‘11’
0
1
RTS Output
Rx FIFO Almost Full
1
0
‘0’
Drive low
1
1
‘1’
Drive Hi

13 Rev NR
D14:13 Cable RTS Output Source
D14
D13
Output Source
Notes
0
0
USC_CTS Output
USC_CTS field (D10:D9) must equal ‘11’
0
1
RTS Output
Rx FIFO Almost Full
1
0
‘0’
Drive low
1
1
‘1’
Drive Hi
D12:11 USC_DCD Direction Setup
If DCD is used as GPIO, set this field to ‘00’ and set Pin Source Register
D16:D15 for output / Pin Status Register D3 for input.
If set, the DCD direction must agree with the USC DCD setup (USC IOCR
D13:12) to ensure proper operation.
If field set to ‘11’ (Output), DCD Source field (D16:15) must be set to ‘00’.
D12
D11
DCD Buffer Direction
USC IOCR D13:D12 Setup
0
0
Buffer Disabled
XX (Don’t Care)
0
1
Input from IO Connector - DCD
0X (Input)
1
0
Reserved
XX (Don’t Care)
1
1
Output to IO Connector
1X (Output)
D10:9 USC_CTS Direction Setup
If CTS is used as GPIO, set this field to ‘00’ and set Pin Source Register
D14:D13 for output / Pin Status Register D2 for input.
If set, the CTS direction must agree with the USC CTS setup (USC IOCR
D15:14) to ensure proper operation.
If field set to ‘11’ (Output), RTS Source field (D14:13) must be set to ‘00’.
D10
D9
CTS Buffer Direction
USC IOCR D15:D14 Setup
0
0
Tristate
XX (Don’t Care)
0
1
Input from IO Connector –CTS
0X (Input)
1
0
Reserved
XX (Don’t Care)
1
1
Output to IO Connector
1X (Output)
D8:6 Cable TxC Source
D8
D7
D6
TxC Source
0
0
0
Prog Clock
0
0
1
Inverted Prog Clock
0
1
0
‘0’ (Drive Line Lo)
0
1
1
‘1’ (Drive Line Hi)
1
0
0
USC_TxC
1
0
1
USC_RxC
1
1
0
Cable RxC Input
1
1
1
Cable RxAuxC Input

14 Rev NR
D5:3 USC_RxC Source
The clock source must agree with the USC Clock setup (USC I/O Control Reg D5:3) to ensure
the signal is not being driven by both the USC and the FPGA.
D5
D4
D3
USC_RxC Source
USC IOCR D2:D0 Setup
0
0
0
Prog Clock
000 (Input)
0
0
1
Inverted Prog Clock
000 (Input)
0
1
0
‘0’
000 (Input)
0
1
1
‘1’
000 (Input)
1
0
0
Cable RxC Input
000 (Input)
1
0
1
Cable RxAuxC Input
000 (Input)
1
1
0
RESERVED
--------
1
1
1
Driven from USC
IOCR D2:D0 != 000 (Output)
D2:0 USC_TxC Source
Since this signal is bidirectional (it may be used as either an input or output to the USC), the
clock source must agree with the USC Clock setup (USC IO Control Reg D2:0) to ensure the
signal is not being driven by both the USC and the FPGA.
D2
D1
D0
USC_TxC Source
USC IOCR D5:D3 Setup
0
0
0
Prog Clock
000 (Input)
0
0
1
Inverted Prog Clock
000 (Input)
0
1
0
‘0’
000 (Input)
0
1
1
‘1’
000 (Input)
1
0
0
Cable RxC Input
000 (Input)
1
0
1
Cable RxAuxC Input
000 (Input)
1
1
0
RESERVED
--------
1
1
1
Driven from USC
IOCR D5:D3 != 000 (Output)
2.1.16 Channel Pin Status: Local Offset 0x0090 / 0x0094 / 0x0098 / 0x009C
Unused inputs may be utilized as general purpose input signals. The Channel Pin Status Register allows the input
state of all the IO pins to be monitored. Output signals as well as inputs are included to aid in debug operation.
D31:D10 RESERVED
D9 TxAuxC Output
D8 RxAuxC Input
D7 DCD Output
D6 RTS Output
D5 TxD Output
D4 TxC Output
D3 DCD Input
D2 CTS Input
D1 RxD Input
D0 RxC Input

15 Rev NR
2.1.13 Programmable Clock Registers: Local Offset 0x00A0 / 0x00A4 / 0x00A8 / 0xAC
The Programmable Clock Registers allow the user to program the on-board programmable oscillator and configure
the channel clock post-dividers. As GSC should provide software routines to program the clock, the user should
have no need to access these registers. See section 3.6 for more information.
2.1.14 FIFO Count Register: Local Offset 0x00D0 / 0x00D4 / 0x00D8 / 0x00DC
The FIFO Count Registers display the current number of words in each FIFO. This value, along with the FIFO Size
Registers, may be used to determine the amount of data which can be safely transferred without over-running (or
under-running) the FIFOs.
D31:16 Number of words in Rx FIFO
D15:D0 Number of words in Tx FIFO
2.1.15 FIFO Size Register: Local Offset 0x00E0 / 0x00E4 / 0x00E8 / 0x00EC
The FIFO Size Registers display the sizes of the installed data FIFOs. This value is calculated at power-up This
value, along with the FIFO Count Registers, may be used to determine the amount of data which can be safely
transferred without over-running (or under-running) the FIFOs.
D31:16 Size of installed Rx FIFO
D15:D0 Size of installed Tx FIFO
2.1.16 FW Type ID Register: Local Offset 0x00F8
This register allows boards to change functionality on each channel. Currently, a channel can only be defined as
Standard or Sync. For SIO4BX-Sync information, please refer to the PCIe-SIO4BX2-SYNC manual.
D31:D24 Channel 4 FW Type –> 01 = Standard / 04 = Sync
D23:D16 Channel 3 FW Type –> 01 = Standard / 04 = Sync
D15:D8 Channel 2 FW Type –> 01 = Standard / 04 = Sync
D7:D0 Channel 1 FW Type –> 01 = Standard / 04 = Sync