GOWIN DK Motor GW2A-LV55PG484C8I7 V3.0 User manual

DK_Motor_GW2A-LV55PG484C8I7_V3.0
User Guide
DBUG410-1.0.1E, 03/17/2023

Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
is the trademark of Guangdong Gowin Semiconductor Corporation and is
registered in China, the U.S. Patent and Trademark Office, and other countries. All other
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
06/28/2022
1.0E
Initial version published.
03/17/2023
1.0.1E
Chapter 4 “Quick Start” removed.
“Figure 2-4 System Block Diagram” in Chapter 2 “Development
Board Introduction” updated.
“Table 3-3 Ethernet Interface Pinout” in Chapter 3.5.2 "Pinout”
updated.

Contents
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations...........................................................................................2
1.4 Support and Feedback ....................................................................................................... 2
2Development Board Introduction...................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Kit....................................................................................................4
2.3 PCB Components ............................................................................................................... 5
2.4 System Block Diagram ....................................................................................................... 5
2.5 Features..............................................................................................................................6
3Development Board Circuit ............................................................................8
3.1 FPGA Module .....................................................................................................................8
3.2 Download Module ............................................................................................................... 8
3.2.1 Introduction ...................................................................................................................... 8
3.2.2 Pinout...............................................................................................................................9
3.3 Power Supply......................................................................................................................9
3.3.1 Introduction ...................................................................................................................... 9
3.4 Clock and Reset ...............................................................................................................10
3.4.1 Introduction ....................................................................................................................10
3.4.2 Pinout.............................................................................................................................10
3.5 Ethernet ............................................................................................................................ 11

Contents
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3.5.1 Introduction .................................................................................................................... 11
3.5.2 Pinout............................................................................................................................. 11
3.6 FSMC interface.................................................................................................................13
3.6.1 Introduction ....................................................................................................................13
3.6.2 Pinout.............................................................................................................................13
3.7 ELVDS interface ...............................................................................................................15
3.7.1 Introduction ....................................................................................................................15
3.7.2 Pinout.............................................................................................................................15
3.8 Motor Control Interface .....................................................................................................16
3.8.1 Introduction ....................................................................................................................16
3.8.2 Pinout.............................................................................................................................16
3.9 PWM interface ..................................................................................................................18
3.9.1 Introduction ....................................................................................................................18
3.9.2 Pinout.............................................................................................................................18
3.10 GPIO ...............................................................................................................................20
3.10.1 Introduction ..................................................................................................................20
3.11 LED Module ....................................................................................................................20
3.11.1 Introduction .................................................................................................................. 20
3.11.2 Pinout ........................................................................................................................... 20
3.12 Key Module.....................................................................................................................21
3.12.1 Introduction ..................................................................................................................21
3.12.2 Pinout...........................................................................................................................21

List of Figures
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List of Figures
Figure 2-1 DK_Motor_GW2A-LV55PG484C8I7_V3.0 Development Board ......................................3
Figure 2-2 A Development Board Suite .............................................................................................4
Figure 2-3 PCB Components.............................................................................................................5
Figure 2-4 System Block Diagram ..................................................................................................... 5
Figure 3-1 FPGA Download and Configuration Connection Diagram ...............................................9
Figure 3-2 Clock and Reset Connection Diagram ............................................................................. 10
Figure 3-3 FPGA and Ethernet Interface Connection Diagram .........................................................11
Figure 3-4 FPGA and FSMC Interface Connection Diagram.............................................................13
Figure 3-5 ELVDS Interface Diagram ................................................................................................15
Figure 3-6 Connection Diagram of Motor Control Interface............................................................... 16
Figure 3-7 PWM Interface Connection Diagram ................................................................................ 18
Figure 3-8 LED Connection Diagram................................................................................................. 20
Figure 3-9 Key Circuit ........................................................................................................................21

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................2
Table 3-1 FPGA Download and Configuration Pinout........................................................................9
Table 3-2 Clock and Reset Pinout......................................................................................................10
Table 3-3 Ethernet Interface Pinout ...................................................................................................11
Table 3-4 FSMC Interface Pinout....................................................................................................... 13
Table 3-5 ELVDS Interface Pinout .....................................................................................................15
Table 3-6 Motor Control Interface Pinout ...........................................................................................16
Table 3-7 PWM Interface Pinout ........................................................................................................ 18
Table 3-8 LED Pinout .........................................................................................................................20
Table 3-9 Key Module Pinout .............................................................................................................21

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_Motor_GW2A-LV55PG484C8I7_V3.0 development board
(hereinafter referred to development board) user guide consists of following
three parts:
A brief introduction to the features of the development board;
An introduction to the development board system architecture and
hardware resources;
An introduction to the functions, circuits, and pinouts of each module;
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com/en:
DS102, GW2A series of FPGA Products Data Sheet
UG113, GW2A-55 Pinout
UG111, GW2A series of FPGA Products Package and Pinout User
Guide
UG290, GW1N series of FPGA Products Programming and
Configuration User Guide
SUG100, Gowin Software User Guide

1 About This Guide
1.3 Terminology and Abbreviations
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1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Abbreviations and Terminology
Terminology and Abbreviations
Meaning
BSRAM
Block Static Random Access Memory
DDR
Double Data Rate
DSP
Digital Signal Processing
FLASH
Flash Memory
FPGA
Field Programmable Gate Array
GPIO
Gowin Programmable Input/Output
LDO
Low Dropout Regulator
LUT4
Four-input Look-up Table
LVDS
Low-voltage Differential Signaling
SSRAM
Shadow Static Random Access Memory
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Introduction
2.1 Overview
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2Development Board Introduction
2.1 Overview
Figure 2-1 DK_Motor_GW2A-LV55PG484C8I7_V3.0 Development Board
The development board uses the GW2A- LV55PG484 FPGA device,
which is the first generation product of Gowin Arora family. The GW2A
series of FPGA products offer abundant resources like high-performance
DSP, high-speed LVDS interface and BSRAM. These embedded resources
combine a streamlined FPGA architecture with a 55nm process to make
the GW2A series of FPGA products ideal for high-speed and low-cost
applications.
The development board integrates three Ethernet interfaces,
supporting 10M/100M industrial Ethernet communication; It also provides
abundant external interfaces, including ELVDS, PWM, PSMC, Ethernet,

2 Development Board Introduction
2.2 A Development Board Kit
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motor communication, and GPIO interface. External FLASH chip is used to
store FPGA configuration programs; There are keys and LEDs that you can
use to debug.
2.2 A Development Board Kit
The development board kit includes the following items:
1. DK_Motor_GW2A-LV55PG484C8I7_V3.0 development board
2. 5V power (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A)
3. USB Mini B Cable
Figure 2-2 A Development Board Suite
1
2 3
①DK_Motor_GW2A-LV55PG484C8I7_V3.0 development board
②5V power (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A)
③USB Mini B data cable

2 Development Board Introduction
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
5V IN
Ethernet
Interface
Ethernet
Interface
Ethernet Interface
PWM
Ethernet
PHY Chip
Ethernet
PHY Chip
Ethernet
PHY Chip
Power Switch1.2VKEY
1V3.3V
USB
Motor
Interface
Motor
Interface
RS422
RS422
RS485
RS485
PWM
ELVDS
FSMC
FPGA
Flash
2.4 System Block Diagram
Figure 2-4 System Block Diagram
FPGA
GW2A-LV55PG484
EEPROM Flash CLK LED
KEY
PHY1
PHY2
PHY3
KSZ8081
KSZ8081
KSZ8081
FSMC
Motor1
Motor2
422/485
422/485
PWM
1PWM 2GPIO
USBFT232HL
Power
ELVDS ELVDS ELVDS

2 Development Board Introduction
2.5 Features
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2.5 Features
The key features are as follows:
1. The FPGA device
Gowin GW2A-LV55PG484 FPGA
319 Max. user I/O
2. Download and Boot
Integrate download module on the board, download through Mini B
cable
External Flash boot
3. Power
External DC 5V 2A
The green POWER light is on after power on
The development board can generate 3.3V, 1.2V, 1.0V
4. Clock system
25MHz crystal oscillator input
5. Memory Device
32Kbit EEPROM
64Mbit FLASH
6. Ethernet interface
Three Ethernet interfaces
Adopt KSZ8081MNXCA-TR chip and supports MII interface
RJ45 connector with built-in transformer
7. ELVDS interface
Three ELVDS interfaces, including six pairs of differential signals
8. FSMC interface
One FSMC interface for the communication between FPGA and
MCU
9. PWM interface
Two PWM interfaces for transmitting PWM signal
10. Motor control interface
Two motor control interfaces
Each motor interface is connected to one RS422 transceiver and
two RS485 transceiver chips
11. USB interface
For downloading test program
12. GPIO Interface
There are 40 PIN double-row pins, including 36 GPIOs. I/O Bank
voltage is 3.3V, leading to two 3.3V voltage and two ground pins.

2 Development Board Introduction
2.5 Features
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Two 24 PIN double-row pins, each including 19 GPIOs. I/O Bank
voltage is 3.3V, leading to three ground pins.
13. Debug module
Four keys
Four green LEDs

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW2A-LV55PG484 FPGA products, please refer
to DS102, GW2A Series of FPGA Products.
I/O BANK Introduction
For the I/O BANK, package, and pinout information, see UG111,
GW2A Series of FPGA Products Package and Pinout User Guide for more
details.
3.2 Download Module
3.2.1 Introduction
The development board provides a USB downloading interface
realized by channel A of FT232HL USB conversion chip. You can set the
MODE value to download the programs to the on-chip SRAM or external
Flash. When downloaded to SRAM, the bitstream file will be lost if the
device powers down. When downloaded to Flash, the bitstream file will not
be lost if the device powers down.
The MODE value configuration is as follows:
1. In any mode, you can download the bitstream file to the on-chip SRAM
and run it immediately.
2. Set MODE as "011" to download the bitstream file to the external Flash.
Set MODE to "000" and power on again. The device will read the FPGA
configuration data from the Flash automatically.
The connection diagram of download and configuration is as shown in
Figure 3-1：

3 Development Board Circuit
3.3 Power Supply
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Figure 3-1 FPGA Download and Configuration Connection Diagram
FLASH_SPI_MISO
FLASH_SPI_MOSI
FLASH_SPI_CS_N
FLASH_SPI_CLK
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TMS
USB-JTAG
Chip
USB_D+
USB_D-
Configuration
FLASH
3.2.2 Pinout
Table 3-1 FPGA Download and Configuration Pinout
Signal Name
FPGA Pin No.
BANK
I/O Level
Description
JTAG_TCK
N20
2
3.3V
JTAG Signal
JTAG_TDO
M22
2
3.3V
JTAG Signal
JTAG_TDI
M20
2
3.3V
JTAG Signal
JTAG_TMS
N22
2
3.3V
JTAG Signal
FLASH_SPI_MISO
P19
3
3.3V
Configure
FLASH Signal
FLASH_SPI_MOSI
P20
3
3.3V
Configure
FLASH Signal
FLASH_SPI_CS_N
N18
3
3.3V
Configure
FLASH Signal
FLASH_SPI_CLK
P18
3
3.3V
Configure
FLASH Signal
3.3 Power Supply
3.3.1 Introduction
The development board is powered via a power adapter. The input
parameter is 100-240V~50/60MHz 0.5A, and the output is DC +5V 2A.
The input 5V power can generate 3.3V, 1.2V, and 1.0V via the power
supply chip on the development board.
Adopt two NCP3170ADR2G DC-DC power chips to generate 3.3V and
1.2V, and the maximum output current is 3A.

3 Development Board Circuit
3.4 Clock and Reset
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Adopt one FP6165ADXR-G1 DC-DC power supply chip to generate
1.0V, and the maximum output current is 3A.
3.4 Clock and Reset
3.4.1 Introduction
The development board offers a 25MHz oscillator connecting to the
global clock pins.
The reset circuit of the development board adopts the key reset design.
Press the key to reset FPAG.
Figure 3-2 Clock and Reset Connection Diagram
D11
U1
KEY1
25MHz
RST_N
CLK_G
3.4.2 Pinout
Table 3-2 Clock and Reset Pinout
Signal Name
FPGA Pin No.
BANK
I/O Level
Description
CLK_G
D11
1
3.3V
25MHz crystal oscillator
Input
RST_N
U1
6
3.3V
Reset signal, active-high

3 Development Board Circuit
3.5 Ethernet
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3.5 Ethernet
3.5.1 Introduction
The development board is equipped with three KSZ8081MNXCA-TR
chips, supporting MII interface.
Figure 3-3 FPGA and Ethernet Interface Connection Diagram
TXD[3:0]
RXD[3:0]
CRS,COL
RXER,RXC,RXDV
TXER,TXC
CLK,RST_N
MDC
MDIO
TXD[3:0]
RXD[3:0]
CRS,COL
RXER,RXC,RXDV
TXER,TXC
CLK,RST_N
TXD[3:0]
RXD[3:0]
CRS,COL
RXER,RXC,RXDV
TXER,TXC
CLK,RST_N
Ethernet
PHY Chip
KSZ8081MNXCA
Ethernet
PHY Chip
KSZ8081MNXCA
Ethernet
PHY Chip
KSZ8081MNXCA
GbE1
GbE2
GbE3
3.5.2 Pinout
Table 3-3 Ethernet Interface Pinout
Signal Name
FPGA Pin No.
BANK
I/O Level
Description
PHY1_CRS
E16
1
3.3V
MII carrier sense
PHY1_COL
C15
1
3.3V
MII collision test
PHY1_TXD0
D12
1
3.3V
MII transmitting data
PHY1_TXD1
D10
0
3.3V
MII transmitting data
PHY1_TXD2
C11
1
3.3V
MII transmitting data
PHY1_TXD3
D14
1
3.3V
MII transmitting data
PHY1_TXEN
E12
1
3.3V
MII transmitting error
PHY1_TXC
D16
1
3.3V
MII transmitting clock
PHY1_RXER
E13
1
3.3V
MII receiving error
PHY1_RXC
A15
1
3.3V
MII receiving clock
PHY1_RXDV
B15
1
3.3V
MII receiving data, valid

3 Development Board Circuit
3.5 Ethernet
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Signal Name
FPGA Pin No.
BANK
I/O Level
Description
PHY1_RXD0
A14
1
3.3V
MII receiving data
PHY1_RXD1
A13
1
3.3V
MII receiving data
PHY1_RXD2
C12
1
3.3V
MII receiving data
PHY1_RXD3
A12
0
3.3V
MII receiving data
PHY_MDC
C20
2
3.3V
MII clock input
PHY_MDIO
C8
0
3.3V
MII data input/output
PHY1_CLK
M4
6
3.3V
Clock input
PHY1_RST_n
F16
1
3.3V
Chip select
PHY2_CRS
A9
0
3.3V
MII collision test
PHY2_COL
A8
0
3.3V
MII carrier sense
PHY2_TXD0
D5
0
3.3V
MII transmitting data
PHY2_TXD1
B7
0
3.3V
MII transmitting data
PHY2_TXD2
A7
0
3.3V
MII transmitting data
PHY2_TXD3
B8
0
3.3V
MII transmitting data
PHY2_TXEN
D4
0
3.3V
MII transmitting error
PHY2_TXC
A6
0
3.3V
MII transmitting clock
PHY2_RXER
B6
0
3.3V
MII receiving error
PHY2_RXC
A5
0
3.3V
MII receiving clock
PHY2_RXDV
C4
0
3.3V
MII receiving data, valid
PHY2_RXD0
A4
0
3.3V
MII receiving data
PHY2_RXD1
A3
0
3.3V
MII receiving data
PHY2_RXD2
A2
0
3.3V
MII receiving data
PHY2_RXD3
A1
0
3.3V
MII receiving data
PHY2_CLK
B11
0
3.3V
Clock input
PHY2_RST_n
A11
0
3.3V
Chip select
PHY3_CRS
F2
7
3.3V
MII collision test
PHY3_COL
F1
7
3.3V
MII carrier sense
PHY3_TXD0
D3
7
3.3V
MII transmitting data
PHY3_TXD1
H2
7
3.3V
MII transmitting data
PHY3_TXD2
G1
7
3.3V
MII transmitting data
PHY3_TXD3
G2
7
3.3V
MII transmitting data
PHY3_TXEN
E4
7
3.3V
MII transmitting error
PHY3_TXC
H1
7
3.3V
MII transmitting clock
PHY3_RXER
J1
7
3.3V
MII receiving error
PHY3_RXC
K1
7
3.3V
MII receiving clock

3 Development Board Circuit
3.6 FSMC interface
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Signal Name
FPGA Pin No.
BANK
I/O Level
Description
PHY3_RXDV
L2
7
3.3V
MII receiving data, valid
PHY2_RXD0
L1
7
3.3V
MII receiving data
PHY2_RXD1
M2
7
3.3V
MII receiving data
PHY2_RXD2
M1
7
3.3V
MII receiving data
PHY2_RXD3
P1
7
3.3V
MII receiving data
PHY2_CLK
R1
7
3.3V
Clock input
PHY2_RST_n
D1
7
3.3V
Chip selected
3.6 FSMC interface
3.6.1 Introduction
There is one FSMC interface on the development board for the
communication between FPGA and MCU. These pins can be used as
GPIOs. The connection diagram is as follows:
Figure 3-4 FPGA and FSMC Interface Connection Diagram
FSMC_D[15:0]
FSMC_A[9:0]
FSMC_INT[1:0]
FSMC_NBL[1:0]
FSMC_CLK
FSMC_NWAIT
FSMC_NOE
FSMC_NWE
FSMC_NADV
FSMC_NE1
FSMC
3.6.2 Pinout
Table 3-4 FSMC Interface Pinout
Signal Name
FPGA Pin No.
BANK
I/O Level
Description
FSMC_D0
Y18
4
3.3V
Data
FSMC_D1
Y19
4
3.3V
Data
FSMC_D2
AB19
4
3.3V
Data
FSMC_D3
AA20
4
3.3V
Data
FSMC_D4
W19
4
3.3V
Data
FSMC_D5
L22
2
3.3V
Data