GOWIN GW1NR Series User manual

GW1NR series of FPGA products
Package & Pinout User Guide
UG119-1.5E, 02/02/2021

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Revision History
Date
Version
Description
04/03/2018
1.04E
Initial version Published.
06/25/2018
1.05E
MG81 package info. Added.
09/13/2018
1.06E
The pins distribution view and package outline of
MG81added.
12/12/2018
1.07E
LVDS paris added in Table 2-1;
Packages of the devices embedded with PSRAM added.
01/09/2019
1.08E
QN88 of GW1NR4 embedded with PSRAM added;
View of pin distribution and I/O bank description updated.
07/09/2019
1.09E
The GW1NR-9 MG100 package added.
04/16/2020
1.1E
GW1NR-9c added.
05/18/2020
1.1.1E
GW1NR-9 MG100PF added.
06/12/2020
1.1.2E
GW1NR-9C revised to GW1NR-9.
06/30/2020
1.2E
GW1NR-1 added.
07/28/2020
1.3E
GW1NR-9 MG100PD added.
09/27/2020
1.4E
GW1NR-9 MG100PA, MG100PT, and MG100PS added;
GW1NR-9 MG100PD removed.
02/02/2021
1.5E
GW1NR-2 MG49P/MG49PG/MG49G added.

Contents
UG119-1.5E
i
Contents
Contents.................................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................2
1.4 Support and Feedback ....................................................................................................... 2
2Overview ........................................................................................................3
2.1 PB-Free Package ...............................................................................................................3
2.2 Package and Max. User I/O Information ............................................................................ 3
2.3 Power Pin ........................................................................................................................... 4
2.4 Pin Quantity........................................................................................................................4
2.4.1 Quantity of GW1NR-1 Pins..............................................................................................4
2.4.2 Quantity of GW1NR-2 Pins..............................................................................................5
2.4.3 Quantity of GW1NR-4 Pins..............................................................................................6
2.4.4 Quantity of GW1NR-9 Pins..............................................................................................8
2.5 Pin Definitions.....................................................................................................................8
2.6 Introduction to the I/O BANK ............................................................................................ 12
3View of Pin Distribution..............................................................................13
3.1 View of GW1NR-1 Pins Distribution .................................................................................13
3.2 View of GW1NR-2 Pins Distribution.................................................................................14
3.2.1 View of MG49P Pins Distribution (PSRAM Embedded)................................................14
3.2.2 View of MG49PG Pins Distribution (PSRAM and Flash Embedded)............................15
3.2.3 View of MG49G Pins Distribution (Flash Embedded) ...................................................16
3.3 View of GW1NR-4 Pins Distribution .................................................................................17
3.3.1 View of MG81P Pins Distribution (PSRAM Embedded)................................................17
3.3.2 View of QN88P Pins Distribution (PSRAM Embedded) ................................................18
3.3.3 View of QN88 Pins Distribution (SDRAM Embedded) ..................................................19

Contents
UG119-1.5E
ii
3.4 View of GW1NR-9 Pins Distribution .................................................................................20
3.4.1 View of QN88 Pins Distribution .....................................................................................20
3.4.2 View of QN88P Pins Distribution...................................................................................21
3.4.3 View of MG100P Pins Distribution.................................................................................22
3.4.4 View of MG100PF Pins Distribution ..............................................................................23
3.4.5 View of LQ144P Pins Distribution..................................................................................24
3.4.6 View of MG100PA Pins Distribution...............................................................................25
3.4.7 View of MG100PS Pins Distribution ..............................................................................26
3.4.8 View of MG100PT Pins Distribution ..............................................................................27
4Package Diagrams ......................................................................................28
4.1 QN88/QN88P Package Outline (10mm x 10mm).............................................................29
4.2 LQ144/LQ144P Package Outline (20mm x 20mm)..........................................................30
4.3 MG49P/ MG49PG/MG49G Package Outline (3.8mm x 3.8mm)...................................... 31
4.4 MG81P Package Outline (4.5mm x 4.5mm)..................................................................... 32
4.5 MG100P/MG100PF/MG100PA/MG100PT MG100PS Package Outline (5mm x 5mm)...33
4.6 FN32G Package Outline (4mm x 4mm)........................................................................... 34

List of Figures
UG119-1.5E
iii
List of Figures
Figure 3-1 View of GW1NR-1 FN32G Pins Distribution (Top View) ..................................................13
Figure 3-2 View of GW1NR-2 MG49P Pins Distribution (Top View, PSRAM Embedded).................14
Figure 3-3 View of GW1NR-2 MG49PG Pins Distribution (Top View, PSRAM and Flash Embedded) 15
Figure 3-4 View of GW1NR-2 MG49G Pins Distribution (Top View, Flash Embedded)....................16
Figure 3-5 View of GW1NR-4 MG81P Pins Distribution (Top View, PSRAM Embedded)................. 17
Figure 3-6 View of GW1NR-4 QN88P Pins Distribution (Top View, PSRAM Embedded)................. 18
Figure 3-7 View of GW1NR-4 QN88 Pins Distribution (Top View, SDRAM Embedded)...................19
Figure 3-8 View of GW1NR-9 QN88 Pins Distribution (Top View).....................................................20
Figure 3-9 View of GW1NR-9 QN88P Pins Distribution (Top View).................................................. 21
Figure 3-10 View of GW1NR-9 MG100P Pins Distribution (Top View).............................................. 22
Figure 3-11 View of GW1NR-9 MG100PF Pins Distribution (Top View)............................................ 23
Figure 3-12 View of GW1NR-9 LQ144P Pins Distribution (Top View)...............................................24
Figure 3-13 View of GW1NR-9 MG100PA Pins Distribution (Top View)............................................25
Figure 3-14 View of GW1NR-9 MG100PS Pins Distribution (Top View) ...........................................26
Figure 3-15 View of GW1NR-9 MG100PT Pins Distribution (Top View)............................................27
Figure 4-1 Package Outline QN88/QN88P........................................................................................29
Figure 4-2 Package Outline LQ144/LQ144P..................................................................................... 30
Figure 4-3 Package Outline MG49P/ MG49PG/MG49G...................................................................31
Figure 4-4 Package Outline MG81P ................................................................................................... 32
Figure 4-5 Package Outline MG100P/MG100PF/MG100PA/ MG100PT .........................................33
Figure 4-6 Package Outline FN32G .................................................................................................. 34

List of Tables
UG119-1.5E
iv
List of Tables
Table 1-1 Abbreviations and Terminologies .......................................................................................2
Table 2-1 Package and Max. User I/O Information, LVDS Pairs ....................................................... 3
Table 2-2 Other Pins in the GW1NR Series.......................................................................................4
Table 2-3 Quantity of GW1NR-1 Pins................................................................................................4
Table 2-4 Quantity of GW1NR-2 Pins................................................................................................5
Table 2-5 Quantity of GW1NR-4 Pins (SDRAM embedded) .............................................................6
Table 2-6 Quantity of GW1NR-4 Pins (PSRAM embedded).............................................................. 7
Table 2-7 Quantity of GW1NR-9 Pins................................................................................................8
Table 2-8 Definition of the Pins in the GW1NR series of FPGAproducts.......................................... 9
Table 3-1 Other pins in GW1NR-1 FN32G ........................................................................................13
Table 3-2 Other pins in GW1NR-2 MG49P (PSRAM Embedded).....................................................14
Table 3-3 Other pins in GW1NR-2 MG49PG (PSRAM and Flash Embedded) .................................15
Table 3-4 Other pins in GW1NR-2 MG49G (Flash Embedded)......................................................... 16
Table 3-5 Other pins in GW1NR-4 MG81P (PSRAM Embedded).....................................................17
Table 3-6 Other pins in GW1NR-4 QN88P (PSRAM Embedded) .....................................................18
Table 3-7 Other pins in GW1NR-4 QN88 (SDRAM Embedded)........................................................ 19
Table 3-8 Other pins in GW1NR-9 QN88........................................................................................... 20
Table 3-9 Other pins in GW1NR-9 QN88P ........................................................................................21
Table 3-10 Other pins in GW1NR-9 MG100P.................................................................................... 22
Table 3-11 Other pins in GW1NR-9 MG100PF.................................................................................. 23
Table 3-12 Other pins in GW1NR-9 LQ144P..................................................................................... 24
Table 3-13 Other pins in GW1NR-9 MG100PA..................................................................................25
Table 3-14 Other pins in GW1NR-9 MG100PS ................................................................................. 26
Table 3-15 Other pins in GW1NR-9 MG100PT..................................................................................27

1 About This Guide
1.1 Purpose
UG119-1.5E
1(34)
1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NR series of FPGA
products together with a definition of the pins, list of pin numbers,
distribution of pins, and package diagrams.
1.2 Related Documents
The latest user guidelines are available on the Gowin website at
www.gowinsemi.com:
1. DS117, GW1NR series of FPGA Products Data Sheet
2. UG290, Gowin FPGA Products Programming and Configuration User
Guide
3. UG119, GW1NR series of FPGA Products Package and Pinout
4. UG805, GW1NR-2 Pinout
5. UG116, GW1NR-4 Pinout
6. UG803, GW1NR-9 Pinout

1 About This Guide
1.3 Abbreviations and Terminology
UG119-1.5E
2(34)
1.3 Abbreviations and Terminology
The abbreviations and terminologies that are used in this manual are
delineated in Table 1-1.
Table 1-1 Abbreviations and Terminologies
Abbreviations and Terminology
Full Name
FPGA
Field Programmable GateArray
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
PSRAM
Pseudo Static Random Access Memory
GPIO
Gowin Programmable IO
QN88
QFN88
MG49P
MBGA 49P
MG49PG
MBGA 49PG
MG49G
MBGA 49G
MG81
MBGA81
MG100P
MBGA100P
MG100PF
MBGA100PF
MG100PA
MBGA100PA
MG100PT
MBGA100PT
MG100PS
MBGA100PS
LQ144
LQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
UG119-1.5E
3(34)
2Overview
The GW1NR series of FPGA Products are the first-generation
products of GOWINSEMI®(LittleBee®) family. They are available in
various forms that offer high I/O compatibility and flexible usage.
2.1 PB-Free Package
The GW1NR series of FPGA products are PB free in line with the EU
ROHS environmental directives. The substances used in the GW1NR
series of FPGA products are in full compliance with the IPC-1752
standards.
2.2 Package and Max. User I/O Information
Table 2-1 Package and Max. User I/O Information, LVDS Pairs
Package
Pitch(mm)
Size (mm)
GW1NR-1
GW1NR-2
GW1NR-4
GW1NR-9
FN32G
0.4
4 x 4
26
-
-
-
MG49P
0.5
3.8 x 3.8
–
30（8）
–
–
MG49PG
0.5
3.8 x 3.8
–
30（8）
–
–
MG49G
0.5
3.8 x 3.8
–
30（8）
–
–
QN88
0.4
10 x 10
–
–
70(11)
70（19）
QN88P
0.4
10 x 10
–
–
70(11)
70（18）
MG81P
0.5
4.5 x 4.5
–
–
68(10)
-
MG100P
0.5
5 x 5
–
–
-
87（16）
MG100PF[1]
0.5
5 x 5
–
–
-
87（16）
MG100PA
0.5
5 x 5
–
–
–
87（17）
MG100PT
0.5
5 x 5
–
–
–
87（17）
MG100PS
0.5
5 x 5
–
–
–
87（17）
LQ144P
0.5
20 x 20
–
–
-
120（20）
Note!
[1]MG100PF: The pinout of ball C1/C2/D2/F1/F9/A7/A6 adjusted on the basis of
MG100P;

2 Overview
2.3 Power Pin
UG119-1.5E
4(34)
In this manual, abbreviations are employed to refer to the package types. See 1.3
Abbreviations and Terminology;
See GW1NR series Pinouts for more details;
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data
noted in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are
used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI,
TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus
one.
2.3 Power Pin
Table 2-2 Other Pins in the GW1NR Series
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCX
VSS
NC
2.4 Pin Quantity
2.4.1 Quantity of GW1NR-1 Pins
Table 2-3 Quantity of GW1NR-1 Pins
Pin Type
GW1NR-1
FN32G
I/O Single
end/Differential pair[1]
BANK0
8/4
BANK1
5/2
BANK2
6/2
BANK3
8/3
Max. User I/O[2]
27
Differential Pair
11
VCC
1
VCCO2
1
VCCO3
1
VCCO0/VCCO1[3]
1
VSS
1
MODE0
0
MODE1
0
MODE2
0
JTAGSEL_N
0
Note!
[1]Quantity of single end/ differential/LVDS I/O include CLK pins, and download pins;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max.
I/O noted in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS)
are used as I/O.
[3]Pin multiplexing.

2 Overview
2.4 Pin Quantity
UG119-1.5E
5(34)
2.4.2 Quantity of GW1NR-2 Pins
Table 2-4 Quantity of GW1NR-2 Pins
Pin Type
GW1NR-2
MG49P
MG49PG
MG49G
I/O
Single
end/Diff
erential
pair[1]
BANK0
14/7/4
14/7/4
14/7/4
BANK1
0/0/0
0/0/0
0/0/0
BANK2
8/4/2
8/4/2
8/4/2
BANK3
4/2/1
4/2/1
4/2/1
BANK4
4/2/1
4/2/1
4/2/1
BANK5
0/0/0
0/0/0
0/0/0
BANK6
10/5/0
10/5/0
10/5/0
Max. User I/O[2]
40
40
40
Differential Pair
20
20
20
True LVDS output
8
8
8
VCC
1
1
1
VCCX
1
1
1
VCCO0
1
1
1
VCCO1
1
1
1
VCCO2/VCCO3/V
CCO4/VCCO5[3]
1
1
1
VCCD
1
1
1
VCCOD
1
1
1
VSS
2
2
2
MODE0
0
0
0
MODE1
0
0
0
MODE2
0
0
0
JTAGSEL_N
0
0
0
Note!
[1]Quantity of single end/ differential/LVDS I/O include CLK pins, and download pins;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max.
I/O noted in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS)
are used as I/O.
[3]Pin multiplexing.

2 Overview
2.4 Pin Quantity
UG119-1.5E
6(34)
2.4.3 Quantity of GW1NR-4 Pins
Table 2-5 Quantity of GW1NR-4 Pins (SDRAM embedded)
Pin Type
GW1NR-4
QN88
I/O Single
end/Differential pair[1]
BANK0
18/5/0
BANK1
15/6/2
BANK2
23/9/7
BANK3
12/4/2
Max. User I/O[2]
70
Differential Pair
24
True LVDS output
11
VCC
4
VCCX
0
VCCO0
0
VCCO1
1
VCCO2
2
VCCO3
1
VCCX/VCCO0[3]
3
VSS
6
MODE0
1
MODE1
1
MODE2
0
JTAGSEL_N
1

2 Overview
2.4 Pin Quantity
UG119-1.5E
7(34)
Table 2-6 Quantity of GW1NR-4 Pins (PSRAM embedded)
Pin Type
GW1NR-4
MG81P
QN88P
I/O Single
end/Differential
pair/LVDS[1]
BANK0
13/6/0
18/5/0
BANK1
17/3/0
15/6/2
BANK2
21/10/10
23/9/7
BANK3
17/2/0
12/4/2
Max. User I/O[2]
68
70
Differential Pair
21
24
True LVDS output
10
11
VCC
3
4
VCCX
1
0
VCCO0
1
0
VCCO1
1
1
VCCO2
1
2
VCCO3
1
1
VCCX/VCCO0[3]
0
3
VSS
4
6
MODE0
0
1
MODE1
1
1
MODE2
0
0
JTAGSEL_N
1
1
Note!
[1]Quantity of single end/ differential/LVDS I/O include CLK pins, and download pins;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max.
I/O noted in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS)
are used as I/O.
[3]Pin multiplexing.

2 Overview
2.5 Pin Definitions
UG119-1.5E
8(34)
2.4.4 Quantity of GW1NR-9 Pins
Table 2-7 Quantity of GW1NR-9 Pins
Pin Type
GW1NR-9
QN88
QN88P
LQ144
P
MG100
P
MG100
PF
MG100
PA
MG100
PT
MG100
PS
I/O Single
end/Differ
ential
pair/LVD
S[1]
BANK0
0/0/0
0/0/0
18/9/0
12/6/0
12/6/0
12/6/0
12/6/0
12/6/0
BANK1
25/11/4
25/11/4
32/12/4
22/5/1
22/6/1
22/6/1
22/5/1
22/6/1
BANK2
23/11/1
1
23/11/1
1
40/19/1
4
32/15/1
4
32/15/1
4
32/15/1
4
32/15/1
4
32/15/1
4
BANK3
22/8/4
22/6/3
30/8/2
21/4/1
21/6/1
21/6/2
21/4/2
21/6/2
Max. User I/O[2]
70
70
120
87
87
87
87
87
Differential Pair
30
28
48
30
33
33
30
33
True LVDS output
19
18
20
16
16
17
17
17
VCC
4
4
4
3
3
3
3
3
VCCX
0
0
2
1
1
1
1
1
VCCO0
0
0
2
1
1
1
1
1
VCCO1
1
1
2
1
1
1
1
1
VCCO2
2
2
2
1
1
1
1
1
VCCO3
1
1
2
1
1
1
1
1
VCCX/VCCO0[3]
3
3
0
0
0
0
0
0
VSS
6
6
9
4
4
4
4
4
MODE0
1
1
1
0
0
0
0
0
MODE1
1
1
1
1
1
1
1
1
MODE2
0
0
0
0
0
0
0
0
JTAGSEL_N
1
1
1
1
1
1
1
1
Note!
[1]Quantity of single end/ differential/LVDS I/O include CLK pins, and download
pins;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The
data in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS)
are used as I/O.
[3]Pin multiplexing.
2.5 Pin Definitions
The location of the pins in the GW1NR series of FPGA products
varies according to the different packages.
Table 2-8 provides a detailed overview of user I/O, multi-function
pins, dedicated pins, and other pins.

2 Overview
2.5 Pin Definitions
UG119-1.5E
9(34)
Table 2-8 Definition of the Pins in the GW1NR series of FPGA products
Pin Name
I/O
Description
User I/O Pins
IO[End][Row/Column
Number][A/B]
I/O
[End] indicates the pin location, including L (left) R
(right) B (bottom), and T (top)
[Row/Column Number] indicates the pin
Row/Column number. If [End] is T (top) or B
(bottom), the pin indicates the column number of
the corresponding CFU. If [End] is L (left) or R
(right), the pin indicates the Row number of the
corresponding CFU.
[A/B] indicates differential signal pair information.
Multi-Function Pins
IO[End][Row/Column Number][A/B]/MMM
/MMM represents one or more of the other
functions in addition to being general purpose user
I/O. These pins can be used as user I/O when the
functions are not used.
D0
I/O
Data port D0 in CPU mode.
D1
I/O
Data port D1 in CPU mode.
D2
I/O
Data port D2 in CPU mode.
D3
I/O
Data port D3 in CPU mode.
D4
I/O
Data port D4 in CPU mode.
D5
I/O
Data port D5 in CPU mode.
D6
I/O
Data port D6 in CPU mode.
D7
I/O
Data port D7 in CPU mode.
RECONFIG_N
I, internal weak
pull-up
Start new GowinCONFIG mode when low pulse
READY
I/O
When high level, the device can be programmed
and configured
When low level, the device cannot be programmed
and configured
DONE
I/O
High level indicates successful program and
configure
Low level indicates incomplete or failed to program
and configure
FASTRD_N
I/O
In MSPI mode, FASTRD_N is used as Flash
access speed port. Low indicates high-speed Flash
access mode; high indicates regular Flash access
mode.
MCLK
I/O
Clock output MCLK in MSPI mode
MCS_N5
I/O
Enable signal MCS_N in MSPI mode, active-low
MI
I/O
MI in MSPI mode: Master data input
MO
I/O
MO in MSPI mode: Master data output
SSPI_CS_N
I/O
Enable signal SSPI_CS_N in SSPI mod,
active-low, Internal Weak Pull Up
SO
I/O
SO in SSPI mode: Slave data output
SI
I/O
SI in SSPI mode: Slave data input
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode

2 Overview
2.5 Pin Definitions
UG119-1.5E
10(34)
Pin Name
I/O
Description
TCK
I
Serial clock input in JTAG mode, which needs to be
connected with 4.7 K drop-down resistance on
PCB
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
TDO
O
Serial data output in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Select signal in JTAG mode, active-low
SCLK
I
Clock input in SSPI, SERIAL, and CPU mode
DIN
I, internal weak
pull-up
Input data in SERIAL mode
DOUT
O
Output data in SERIAL mode
CLKHOLD_N
I, internal weak
pull-up
High level, SCLK will be connected internally in
SSPI mode or CPU mode
Low level, SCLK will be disconnected from SSPI
mode or CPU mode
WE_N
I
Select data input/output of D[7:0] in CPU mode
GCLKT_[x]
I
Pins for global clock input, T(True), [x]: global clock
No.
GCLKC_[x]
I
Differential comparation input pin of GCLKT_[x],
C(Comp), [x]: global clock No.[1]
LPLL_T_fb/RPLL_T_fb
I
L/R PLL feedback input pin, T(True)
LPLL_C_fb/RPLL_C_fb
I
L/R PLL feedback input pin, C(Comp)
LPLL_T_in/RPLL_T_in
I
L/R PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in
I
L/R PLL clock input pin, C(Comp)
MODE2
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is
not bonded, it's internal grounded.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is
not bonded, it's internal grounded.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is
not bonded, it's internal grounded.
SDA
I/O
I2C serial data line
SCL
I
I2C serial clock line
Other Pins
CKP
DIO[2]
Clock channel input pin for MIPI_DPHY_RX,
T(True)
CKN
DIO[2]
Differential comparison input pin of clock channel
for MIPI_DPHY_RX, C(Comp)
RX0P
DIO[2]
Data channel 0 input pin for MIPI_DPHY_RX,
T(True)
RX0N
DIO[2]
Differential comparison input pin of data channel 0
for MIPI_DPHY_RX, C(Comp)
RX1P
DIO[2]
Data channel 1 input pin for MIPI_DPHY_RX,
T(True)
RX1N
DIO[2]
Differential comparison input pin of data channel 1
for MIPI_DPHY_RX, C(Comp)
RX2P
DIO[2]
Data channel 2 input pin for MIPI_DPHY_RX,
T(True)
RX2N
DIO[2]
Differential comparison input pin of data channel 2
for MIPI_DPHY_RX, C(Comp)

2 Overview
2.5 Pin Definitions
UG119-1.5E
11(34)
Pin Name
I/O
Description
RX3P
DIO[2]
Data channel 3 input pin for MIPI_DPHY_RX,
T(True)
RX3N
DIO[2]
Differential comparison input pin of data channel 3
for MIPI_DPHY_RX, C(Comp)
NC
NA
Reserved.
VSS
NA
Ground pins
VCC
NA
Power supply pins for internal core logic.
VCCO#
NA
Power supply pins for the I/O voltage of I/O
BANK#.
VCCX
NA
Power supply pins for auxiliary voltage.
Note!
[1] When the input is not single-ended, the GLKC_[x] pin is not a global clock pin.
[2] DIO is a dedicated pin.

2 Overview
2.6 Introduction to the I/O BANK
UG119-1.5E
12(34)
2.6 Introduction to the I/O BANK
GW1NR-1/4/9 includes four I/O Banks.
GW1NR-2 MG49P/MG49PG/MG49G includes seven I/O Banks.
This manual provides an overview of the distribution view of the
pins in the GW1NR series of FPGA products. Please refer to 3 View of
Pin Distribution for further details. Different IO Banks in the GW1NR
series FPGA products are marked with different colors.
User I/O, power, and ground are also marked with different symbols
and colors. The various symbols and colors used for the various pins are
defined as follows:
“ ” denotes I/Os in BANK0.
” ” denotes I/Os in BANK1.
” ” denotes I/Os in BANK2.
” ” denotes I/Os in BANK3.
” ” denotes I/Os in BANK4.
” ” denotes I/Os in BANK5.
” ” denotes I/Os in BANK6.
“ ” denotes VCC, VCCX, and VCCO. The filling color does not
change.
” ” denotes VCC. The filling color does not change.
“ ” denotes NC.

3 View of Pin Distribution
3.1 View of GW1NR-1 Pins Distribution
UG119-1.5E
13(34)
3View of Pin Distribution
3.1 View of GW1NR-1 Pins Distribution
Figure 3-1 View of GW1NR-1 FN32G Pins Distribution (Top View)
Table 3-1 Other pins in GW1NR-1 FN32G
VCC
9
VCCO0/VCCO1
13
VCCO2
5
VCCO3
4
VSS
10