HighPoint HPT366 Installation and user guide

HIGHPOINT
TECHNOLOGIES,INC.
HPT366 DATA MANUAL
www.highpoint-tech.com

The products described in this publication are products of HighPointTechnologies.
Copyright 1999
By HighPointTechnologies, Inc.
AllRights Reserved
Printed in U.S.A.

HPT366 Data Manual
Thismanual assumessome priorknowledge ofcurrent andinformation ofHPT366 Standard.
Thedata manualorganized intothe followingchapter :
Chapter1- Overview,
Chapter2- SignalDescription,
Chapter3- Registers.
Chapter4- Electrical Parameters,
Chapter5-Timing,
AppendixA- MechanicalDimensions.
AppendixB- Diagrams.
Please give us your advice after you read it.
Preface
Preface
i
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Chapter 1
Overview
Introduction ...................................................................................................................................1-1
1.1HPT366 BlockDiagram ...........................................................................................................1-2
1.2Features .................................................................................................................................. 1-3
HPT366 Data Manual
Table of Contents
Contents
Chapter 2
Signal Description
IntroductionPins ............................................................................................................................2-1
2.1 144 Pins Signal Description...................................................................................................... 2-2
2.2 144 Pins Listing .......................................................................................................................2-3
System Pins............................................................................................................................ 2-3
PowerandGround Pins ........................................................................................................... 2-3
InterfaceControl Pins ..............................................................................................................2-4
ArbitrationPins ........................................................................................................................2-4
PCI Interrupt Pins ....................................................................................................................2-5
Address/DataPins................................................................................................................... 2-5
IDE Interface Pins ................................................................................................................... 2-6
EPROM Interface Pins ............................................................................................................ 2-7
OtherPins ...............................................................................................................................2-8
Chapter 3
Registers
Introduction ....................................................................................................................................3-1
3.1 Registers Listing ............................................................................................................... 3-2,3-3
3.2PCI ConfigurationRegisters .....................................................................................................3-4
Vendor ID and Device ID .......................................................................................................... 3-4
CommandRegister ...................................................................................................................3-4
StatusRegister......................................................................................................................... 3-5
RevisionIdentification Register ................................................................................................ 3-5
ClassCode Register.................................................................................................................3-6
LatencyTimerRegister............................................................................................................. 3-6
HeaderType Register................................................................................................................ 3-7
CommandBlock Register .........................................................................................................3-7
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Contents
HPT366 Data Manual
Chapter 4
ElectricalParameters
Introduction.....................................................................................................................................4-1
4.13.3V SignalingEnvironment ......................................................................................................4-1
DCSpecifications..................................................................................................................... 4-2
AC Specifications.....................................................................................................................4-3
Chapter 5
Timing
Introduction.....................................................................................................................................5-1
5.1TimingParameters ....................................................................................................................5-2
5.2 ClockTiming .............................................................................................................................5-3
5.3ReadTransaction.......................................................................................................................5-4
5.4WriteTransaction .......................................................................................................................5-5
5.5 IDETiming ....................................................................................................................5-6,5-7,5-8
ControlBlock Register..............................................................................................................3-8
I/O Space Base Register.......................................................................................................... 3-8
CardBusCIS Pointer Register...................................................................................................3-8
SubsystemVendorID Register .................................................................................................3-9
Subsystem ID Register.............................................................................................................3-9
ExpansionROM BaseRegister ................................................................................................ 3-9
InterruptLine Register ............................................................................................................ 3-10
InterruptPin Register.............................................................................................................. 3-10
IDETiming0Register.............................................................................................................. 3-11
IDETiming1Register.............................................................................................................. 3-12
MISC.Control1 Register ......................................................................................................... 3-13
MISC.Control2 Register ......................................................................................................... 3-14
MISC.Control3 Register ......................................................................................................... 3-15
MISC.Control4 Register ......................................................................................................... 3-15
Bus Status1 Register ............................................................................................................. 3-16
Bus Status2 Register ............................................................................................................. 3-17
Cable Select Register ............................................................................................................. 3-17
3.3 I/O Space Registers............................................................................................................... 3-18
Bus Master CommandRegister .............................................................................................. 3-18
Bus Master Status Register.................................................................................................... 3-18
Bus Master Scatter GatherTable Base Register ..................................................................... 3-19
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HPT366 Data Manual
Contents
Appendix A
Mechanical Dimensions
Introduction ....................................................................................................................................A-1
A.1 144 Pins LQFP ........................................................................................................................ A-2
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Appendix B
Diagrams
Introduction ....................................................................................................................................B-1
B.1Schematic DiagramsFor Add-OnCard .................................................................................... B-2
B.2Layout ForAdd-On Card ..........................................................................................................B-3
B.3 Schematic Diagrams For Main Board................................................................................ B-4,B-5

Chapter 1
Overview
Overview/Introduction
HPT366 Data Manual
Thischapter willcombinesinformation andfeatures forthe HPT366.
HPT366has beendesigned tolet youadd additionalhigh performancedevice(s) to
yourcurrent computersystem.
Introduction
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HPT366 Data Manual
Overview/Block Diagram
1.1 Block Diagram
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Timing
Control1
Timing
Control2
Decoder
Primary
Master
Primary
Slave
Secondary
Master
Secondary
Slave
PCI Bus
E2PROM
IF
IDE IF
FIFO
FIFO
PCI IF
PCI IF IDE IF
Timing
Control1
Timing
Control2
Serial EPROM
Parallel EPROM
Decoder

There is one packages. It is 144 Pin.
HPT366 Data Manual
Overview/Features
1.2 Features List
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•UltraDMA 66MB/soperation.
•Two PCI functions in a single chip.
•Twoindependent ATAchannels(one channelper PCIfunction).
•DedicatedATA Bus
•256 Byte FIFO per ATA channel.
•LargeFIFOindependent
•Supports all ATAPI CD-ROM, DVD-ROM, CD-R, CD-RW, LS-120, MO,Tape and ZIP devices.
•EasyPlug-and-Play feature.
•Supports up to 4 devices IDE devices. (Coexist with on-board IDE)
•Supports Hard Drive capacity large than 8.4 GB.
•Supports MS-DOS,Windows3.x,Windows95,Windows98,WindowsNT,OS2WARP,
NovellNetware andSCO UNIX.
•Supports booting function with Flash Memory interface.
•Automatically fine tunes to the best performance for each individual IDE/ATAPI device.
•BackwardCompatible
•Concurrent PIO and bus master access (ATA port accessible during DMA transfer).
•Total ATA bus tri-state by external control and Supports Hotswap (Low signal Current)
•ReloadablePCI configurationusing parallelEPROM or2 wireserial EPROM.
•(Loadingaddress 0for serialsize EPROM,loading address400H forparallel EPROM.)
•144Pin LQFP(DedicatedParallel EPROMpins).
•Small foot print 144 pin LQFP
•Up to 44MHz PCI bus Clock.
•Multifunction
•Embeded serial resistor on chip for ATA spec.

Signal Descriptions
Chapter 2
Signal Description
HPT366 Data Manual
Introduction Pins
This chapter will introduction all pins for you.
Theinterface signalsare organizedinto thefollowing functionalgroups:
* System Pins,
* Powerand GroundPins,
* InterfaceControl Pins,
* ArbitrationPins,
* PCI Interrupt Pins,
* Address/DataPins,
* IDE Interface Pins,
* EPROM Interface Pins,
* Other Pins.
Thereare threesignaltype definitions:
I Input,a standardinput-onlysignal.
O TotemPole Output,a standardoutput driver.
I/O Input andOutput.
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Signal Descriptions/144 Pins Signal Descriptions
HPT366 Data Manual
2.1 144 Pins Signal Descriptions
MD2 109
SD12/MA4 110
MA4 111
SD3/MD3 112
MD3 113
SD11/MA3 114
MA3 115
SD4/MD4 116
MD4 117
SD10/MA2 118
MA2 119
SD5/MD5 120
VDD 121
MD5 122
gndado 123
SD9 124
SD6/MD6 125
MD6 126
SD8 127
SD7/MD7 128
MD7 129
SRST_ 130
SDA/EFM_WE_ 131
SCL/EFM_OE_ 132
INTA_ 133
INTB_ 134
PCIRST_ 135
PCICLK 136
gndado 137
GNT_ 138
PCIREQ_ 139
AD31 140
AD30 141
AD29 142
AD28 143
VDD 144
72 VDDI
71 gndado
70 PD4
69 PD11
68 PD3
67 PD12
66 PD2
65 PD13
64 PD1
63 PD14
62 PD0
61 PD15
60 PDRQ
59 PIOW_
58 PIOR_
57 PIORDY
56 PDACK_
55 IRQ14
54 PA1/MA14
53 PCBLID/MA16
52 PA0/MA13
51 PA2/EFMCS_
50 PCS0_/MA0
49 PCS1_/MA1
48 AD0
47 AD1
46 gndado
45 AD2
44 AD3
43 AD4
42 AD5
41 AD6
40 gndado
39 AD7
38 C_BE_0
37 AD8
VDD 1
AD27 2 AD26 3 AD25 4 AD24 5
C_BE_3 6
IDSEL 7
AD23 8 AD22 9 AD21 10 AD20 11 AD19 12
gndado 13
AD18 14 AD17 15 AD16 16
VSS 17 VSS 18 VSS 19
C_BE_2 20
FRAME_ 21
IRDY_ 22
TRDY_ 23
DEVSEL_ 24
vddado 25
STOP_ 26
PAR 27
C_BE_1 28
AD15 29 AD14 30 AD13 31 AD12 32 AD11 33 AD10 34
VDD 35 AD9 36
108 SD2/MD2 107 MA5 106 SD13/MA5 105 MD1 104 SD1/MD1 103 MA6 102 SD14/MA6 101 MD0 100 SD0/MD0
99 MA7 98 VDD 97 SD15/MA7 96 SDRQ 95 SIOW_ 94 SIOR_ 93 SIORDY 92 VSSI 91 VSSI 90 VSSI 89 SDACK_ 88 IRQ15 87 SA1/MA9 86 SCBLID/MA15 85 SA0/MA8 84 SA2/MA10 83 SCS0_/MA11 82 SCS1_/MA12 81 TRI_ 80 PRST_ 79 PD7 78 PD8 77 PD6 76 PD9 75 PD5 74 PD10 73 VDDI
HPT366
144 Pins
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Pin 1

HPT366 Data Manual
Signal Descriptions/144 Pins Listing
2.2 144 Pins Listing
System Pins
Pin Number Pin Name Type Description
135 PCIRST_ I Reset PCI Bus
Pin Number Pin Name Type Description
Power and Ground Pins
17,18,19 VSS Groundreference powersupply IC,input andoutput.
90,91,92 VSSI Groundreference powersupply onput,inputandIC.
1,25,35, VDD Positive power supply output.
98,121,144
72,73 VDDI Positive power supply output and IC.
136 PCICLK I Clock provides timing for all transactions on the PCI bus and is
an input to every PCI device. All other PCI signals are sampled
on the rising edge of CLK, and other timing parameters are
defined with respect to this edge. Clock can optionally serve as
the SCSI core clock, but this may effect Fast SCSI transfer
rates.
13,40,46, gndado GroundOutput
71,123,137
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Signal Descriptions/144 Pins Listing
HPT366 Data Manual
PinNumber Pin Name Type Description
Arbitration Pins
139 PCIREQ_ O Request indicates to the system arbiter that this agent desires
use of the PCI bus.
PinNumber Pin Name Type Description
24 DEVSEL_ I/O Device Select indicates that the driving device has decoded its
address as the target of the current access. As an input, it indi-
cates to a master whether any device on the bus has been
selected.
26 STOP_ I/O Stop indicates that the selected target is requesting the master
to stop the current transaction.
7 IDSEL I Initialization Device Select is used as a chip select in place of
theupper 24address linesduring configurationread andwrite
transactions.
Interface Control Pins
21 FRAME_ I/O Cycle Frame is driven by the current master to indicate the
beginning and duration of an access.FRAME_ is asserted to
indicate that a bus transaction is beginning.While FRAME_ is
deasserted, either the transaction is in the final data phase or
the bus is idle.
22 IRDY_ I/O Initiator Ready indicates theinitiating agents(busmasters)
ability to complete the current data phase of the transaction.
IRDY_ is used withTRDY_ A data phase is completed on any
clockwhenboth IRDY_andTRDY_ sampledasserted.During
a write, IRDY_ indicates that valid data is present on AD(31-0).
During a read, it indicates that master is prepared to accept
data.Wait cycles are inserted until both IRDY_ andTRDY_ are
assertedtogether.
23 TRDY_ I/O Target Ready indicates thetarget agents(selecteddevices)
ability to complete the current data phase of the transaction.
TRDY_ is used with IRDY_.A data phase is completed on any
clock when used with IRDY_.A data phase is completed on any
clockwhenbothTRDY_ andIRDY_ aresampled asserted.
During a write,TRDY_ indicates that the target is prepared to
accept data. During a read,it indicates that valid data is present
on AD(31-0).Wait cycles are inserted until both IRDY_ and
TRDY_areasserted together.
138 GNT_ I Grant indicates to the agent that access to the PCI bus has
beengranted.
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HPT366 Data Manual
Signal Descriptions/144 Pins Listing
PCI Interrupt Pins
Pin Number Pin Name Type Description
133 INTA_ O Interrupt A is used to request an interrupt.
Address/Data Pins
Pin Number Pin Name Type Description
27 PAR I/O Parity is the even parity bit that protects the AD(31-0) and
C_BE_(3-0)lines. Duringaddress phase,boththe addressand
commandbits arecovered. Duringdata phase,both dataand
byteenables arecovered.
140,141,142, AD(31-0) I/O Physical longwordAddress and Data are multiplexedon the
143,2,3,4,5, same PCI pins. During the first clock of a transaction, AD(31-0)
8,9,10,11,12, contain a physical byte address. During subsequent clocks,
14,15,16,29, AD(31-0) contain data. A bus transaction consists of an address
30,31,32,33, phase followed by one or more data phase.PCI supports both
34,36,37,39, read and write bursts. AD(7-0) define the least significant byte,
41,42,43,44, and AD(31-24) define the most significant byte.
45,47,48
6,20,28,38 C_BE_(3-0) I/O Bus command and byte enables are multiplexed on the same
PCIpins. Duringthe addressphase ofa transaction,C_BE_(3-0)
definethe buscommand. Duringthedataphase,C_BE_(3-0)
are used as byte enables.The byte enables determine which
byte lanes carry meaningful data. C_BE_0 applies to byte 0,
and C_BE_3 to byte 3.
134 INTB_ O Interrupt B is used to request an interrupt and only has meaning
on a multi-function device.
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HPT366 Data Manual
Signal Descriptions/144 Pins Listing
IDE Interface Pins
Pin Number Pin Name Type Description
84,87,85 SA(2-0)/ O IDE Device Address
MA(10-8)
97,102,106, SD(15-0) I/O IDE Data
110,114,118, They are also used as Memory Data Bus and Memory Address
124,127,128, Bus signal.
125,120,116,
112,108,104,
100
89 SDACK_ O SecondaryIDEDMA Acknowledge
56 PDACK_ O PrimaryIDE DMAAcknowledge
93 SIORDY I SecondaryIDE ChannelI/O Ready
57 PIORDY I PrimaryIDE ChannelI/O Ready
96 SDRQ I SecondaryIDE DMARequest
60 PDRQ I Primary IDE DMA Request
61,63,65,67, PD(15-0) I/O Primary IDE Data
69,74,76,78,
79,77,75,70,
68,66,64,62
51,54,52 PA(2-0) O Primary IDE Device Address
Them are also used as EFMCS_ and Memory Address Bus
signal.
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Pin Number Pin Name Type Description
HPT366 Data Manual
Signal Descriptions/144 Pins Listing
132 SCL/ O EPROM Output Enable.This pin is used as an output enable
EFM_OE_ signal to an external EPROM or flash memory during read
operations. It is also used as a SCL signal.
131 SDA/ O EPROMWrite Enable.This pin is used as a write enable signal
EFM_WE_ to an external flash memory.When system reset, this signal will
be latched on rising edge of PCIRST_ signal. If latched values
of SDA/EFM_WE_ &TRI signals are both high-LEV, the
configurationwill beloaded fromparallelEPROMautomatically.
It is also used as a SDA signal.
EPROM Interface Pins
53,86,54,52, MA(16-0) O Memory Address Bus.This bus is used in conjunction with
82,83,84,87, the memory address strobe pins and external address latches
85,97,99,102, to assemble up to a 20-bit address for an external EPROM or
103,106,107, flash memory.This bus puts out the least significant byte first
110,111,114, and finishes with the most significant bits. It is also used to
115,118,119, write data to a flash memory or read data into the chip from
49,50 external EPROM/flash memory.They are also use as PCBLID,
SCBLID, PA(1-0),SCS1_,SCS0_,SA(2-0),SD(15-10), PCS1_
and PCS0_ signal. (Please refer to Other Pins for MA7.)
51 PA2/ O EPROM Chip Select. It is also used as a Primary IDE Device
EFMCS_ Addresssignal.
129,128,126, MD(7-0)/ I/O Memory Data Bus.This bus is used in conjunction with the
125,122,120, SD(7-0) memory address strobe pins and external address latches to
117,116,113, assemble up to a 20-bit address for an external EPROM or
112,109,108, flash memory.This bus puts out the least significant byte first
105,104,101, and finishes with the most significant bits. It is also used to
100 write data to a flash memory or read data into the chip from
external EPROM/flash memory.All MD pins have internal
pull-downresistors.Theyare alsoused Secondary IDE Data
signal.
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Other Pins
Pin Number Pin Name Type Description
82 SCS1_/MA12 O SecondaryDevice ChipSelect1.
83 SCS0_/MA11 O SecondaryDevice ChipSelect0.
HPT366 Data Manual
Signal Descriptions/144 Pins Listing
49 PCS1_/MA1 O Primary Device Chip Select 1.
50 PCS0_/MA0 O Primary Device Chip Select 0.
88 IRQ15 I Interrupt Request 15.This pin is used to rquest an interrupt for
secondary IDE port in PCI IDE Legacy Mode.(PC-AT compati-
ble.) IRQ15 is tri-stated when IDE port 1 is in Native Mode.
55 IRQ14 I Interrupt Request 14.This pinis usedto requestan interrupt
in PCI IDE Legacy Mode.(For PC-AT compatibles.) IRQ 14 is
tri-stated when IDE port 0 is in Native Mode.
94 SIOR_ O SecondaryI/O Read.
58 PIOR_ O PrimaryI/ORead.
95 SIOW_ O Secondary I/OWrite.
59 PIOW_ O Primary I/OWrite.
80 PRST_ O PrimaryReset
86 SCBLID/MA5 O SecondaryCableAssemblyTypeIdentifier.
53 PCBLID/MA16 O PrimaryCableAssemblyType Identifier.
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130 SRST_ O SecondaryReset
81 TRI I When system reset, theTRI signal will be latched on rising
edge of PCIRST_ signal.If the latched value ofTRI is 0, the
configuration will be loaded from serial EPROM automatically.
When the system works normally andTRI signal is low-LEV,
the outputs of ATA BUS are high- impedance.
94 MA7 I/O When system reset, the MA7 signal will be latched on rising
edge of PCIRST_ signal. If the value is 1, the IC is packaged
of 144 Pins.The MA7 pin must have a external pull_up
resistor(<5K).

Chapter 3
Registers
HPT366 Data Manual
Registers/Introduction
This chapter will introduction PCI Configuration Registers and I/O Space Registers.
HPT366 have two functions.In this chapter, there just list the registers of most same
as PCI function 0, expect a few registers which have been listed at the same location.
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Introduction

HPT366 Data Manual
Registers/Registers Listing HighPoint Technologies,Inc
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3.1 Registers Listing
HeaderTypeRegister
NO. NAME PAGE ATTRIBUTE
1 Vendor ID and Device ID 3-4
2 Command Register 3-4
3 Status Register 3-5
4 Revision Identification Register 3-5
5 Class Code Register 3-6
63-6
7 3-7 PCI Configuration
8 Command Block Register 3-7 Registers
9 Control Block Register 3-8
10 I/O Space Base Register 3-8
11 CardBus CIS Pointer Register 3-8
12 Subsystem Vendor ID Register 3-9
13 3-9
14 Expansion ROM Base Register 3-9
15 3-10
16 3-10
LatencyTimerRegister
Subsystem ID Register
InterruptLine Register
InterruptPin Register

HPT366 Data Manual
Registers/Registers Listing
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NO. NAME PAGE ATTRIBUTE
17 IDE Timing0 Register 3-11
18 IDE Timing1 Register 3-12
19 MISC.Control1 Register 3-13
20 MISC.Control2 Register 3-14 PCI Configuration
21 MISC.Control3 Register 3-15 Registers
22 3-15
23 3-16
24 Bus Status2 Register 3-17
25 Cable Select Register 3-17
26 Bus Master Command Register 3-18 I/O Space Registers
27 Bus Master Status Register 3-18
28 Bus Master Scatter Gather Table Base Register 3-19
MISC.Control4Register
Bus Status1 Register