hilscher netX 90 User manual

Design-In Guide
netX 90
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public

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netX 90 | Design-In Guide
DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018
Table of contents
1Introduction.............................................................................................................................................4
1.1 About this document ......................................................................................................................4
1.2 List of revisions...............................................................................................................................5
1.3 References to documents ..............................................................................................................5
2Basic concepts.......................................................................................................................................6
2.1 netX 90 – introduction ....................................................................................................................6
2.2 netX 90 – use cases.......................................................................................................................7
2.3 Design checklist .............................................................................................................................8
3Basic circuits........................................................................................................................................10
3.1 Power supply................................................................................................................................10
3.1.1 Integrated core voltage regulator..................................................................................................... 10
3.2 Brown-Out Detector (BOD)..........................................................................................................11
3.3 Power-on reset and reset in.........................................................................................................12
3.4 System clock................................................................................................................................13
3.5 Boot sequence .............................................................................................................................14
3.5.1 Configuration pins ........................................................................................................................... 14
3.5.1.1 Console mode ................................................................................................................ 15
3.5.1.2 Alterative boot mode....................................................................................................... 15
3.5.1.3 System RDY/RUN LED .................................................................................................. 16
3.6 External memory..........................................................................................................................17
3.6.1 Serial memory interface................................................................................................................... 18
3.6.1.1 QSPI Flash..................................................................................................................... 18
3.6.2 Parallel memory interface................................................................................................................ 19
3.6.2.1 SDRAM........................................................................................................................... 19
3.7 Host interface...............................................................................................................................21
3.7.1 Dual-port memory............................................................................................................................ 22
3.7.1.1 8/16-bit data width and dual-port memory size............................................................... 22
3.7.1.2 Control lines.................................................................................................................... 22
3.7.1.3 Non-multiplexed mode.................................................................................................... 23
3.7.1.4 Multiplexed mode ........................................................................................................... 26
3.7.1.5 Ready/Busy signal.......................................................................................................... 27
3.7.2 Serial port memory (SPI/QSPI access to DPM) .............................................................................. 28
3.8 PIO signals...................................................................................................................................29
3.8.1 External pull-ups/pull-downs, unused signals.................................................................................. 29
3.9 Multiplexed IO matrix (MMIO)......................................................................................................30
3.10 General purpose IOs....................................................................................................................32
3.11 Serial interfaces ...........................................................................................................................33
3.11.1 UARTs............................................................................................................................................. 33
3.11.2 SPI................................................................................................................................................... 34
3.11.3 SQI.................................................................................................................................................. 34
3.11.4 I2C................................................................................................................................................... 35
3.11.5 CAN................................................................................................................................................. 35
3.12 IO-Link..........................................................................................................................................36
3.13 Motion control...............................................................................................................................36
3.14 Analog to digital converter............................................................................................................37
3.15 Encoder interfaces .......................................................................................................................37
3.16 Fieldbus interfaces.......................................................................................................................38
3.16.1 CANopen interface.......................................................................................................................... 38
3.16.2 CC-Link interface............................................................................................................................. 39
3.16.3 DeviceNet interface......................................................................................................................... 39
3.16.4 PROFIBUS interface ....................................................................................................................... 40
3.16.5 Fieldbus status LEDs....................................................................................................................... 40
3.17 Real-time Ethernet (RTE) interface..............................................................................................41
3.17.1 Twisted pair..................................................................................................................................... 41
3.17.2 Unused Ethernet PHYs ................................................................................................................... 44
3.17.3 Ethernet status LEDs....................................................................................................................... 45
3.17.3.1 Ethernet communication status LEDs............................................................................. 45
3.17.3.2 Real-time Ethernet protocol status LEDs........................................................................ 46
3.17.4 Real-Time Ethernet synchronization signals ................................................................................... 47
4Debug and test interfaces ...................................................................................................................48

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4.1 Legacy 20-pin JTAG interface......................................................................................................48
4.2 JTAG and TPIU interface (20-pin)................................................................................................49
4.3 JTAG interface (10-pin)................................................................................................................50
4.4 Boundary scan test ......................................................................................................................50
5Firmware overview and resources .....................................................................................................51
5.1 Firmware variants and use cases ................................................................................................51
5.2 Firmware programming and update.............................................................................................51
6General design considerations...........................................................................................................52
6.1 Thermal behavior .........................................................................................................................52
6.1.1 Basics.............................................................................................................................................. 52
6.1.2 Estimates......................................................................................................................................... 52
6.1.3 Recommendations........................................................................................................................... 52
6.1.4 Rules of thumb................................................................................................................................ 52
6.2 EMC behavior...............................................................................................................................53
6.2.1 Layer stack...................................................................................................................................... 53
6.2.2 Decoupling capacitors..................................................................................................................... 54
6.2.3 Reset lines....................................................................................................................................... 55
6.2.4 Clock circuits................................................................................................................................... 55
6.2.5 Ethernet interface............................................................................................................................ 56
6.2.6 Memory bus..................................................................................................................................... 58
6.2.7 Planes ............................................................................................................................................. 58
6.2.8 VIAs and signal fan out under netX 90............................................................................................ 59
7Appendix ...............................................................................................................................................60
7.1 List of tables.................................................................................................................................60
7.2 List of figures................................................................................................................................61
7.3 Legal notes...................................................................................................................................62
7.4 Registered trademarks.................................................................................................................65
7.5 Contacts .......................................................................................................................................66

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1 Introduction
1.1 About this document
This document is directed to hardware developers who intend to create a hardware design with a
netX 90 communication controller of the Hilscher netX family.
This Design-In Guide describes the standard circuitry around all netX interfaces like memory
interface (SDRAM, FLASH) USB, UARTs, XMACs (Ethernet and fieldbus), LCD, power supply,
reset, and clock circuits along with the standard netX I/O resources (PIOs, GPIOs) that have been
assigned a default functionality at Hilscher. These resources include status LEDs, control signals,
and sync signals for RTE applications. For explanations of netX 90 technology and features, see
reference [1].
Although the system designers are at liberty to select any available I/Os for I/O purposes, it is
important that they comply with the standard port definitions whenever loadable Hilscher firmware
(LFW) is to be used, since this kind of firmware necessarily assumes compliance with Hilscher
standard assignments.
Note: Designers should be aware that not all components supported by netX hardware (e.g.
parallel FLASH) are necessarily also supported by existing software/firmware or tools
from Hilscher! Thus, we strongly recommend you to consult the feature table of the
following chapter to make sure that the firmware to be used really supports all desired
hardware features of your planned design. This applies not only, but particularly to
customers who intend to use loadable Hilscher firmware (LFW) instead of developing
their own firmware.
Resources that are currently not supported by loadable firmware (LFW) or that are not yet
available with drivers/codes may still be supported by existing Hilscher devices (e.g. Gateways).
We therefore recommend you to check with Hilscher Sales if there is already a solution for your
problem. Moreover, Hilscher offers several custom design services for netX hardware and
software, as well as manufacturing services, providing an easy way to your custom product. For
detailed information and quotes, please contact Hilscher Sales.
Hilscher also offers a schematic review service allowing your hardware design to be checked by
experienced netX hardware engineers. Hilscher Sales will be happy to provide an individual quote
for this service after receiving your schematics (PDF format).
Note: Before starting a design, we strongly recommend you to consult the latest Errata
Sheets (available on the Hilscher website www.hilscher.com) of the netX controllers!

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1.2 List of revisions
Rev Date Name Chapter Revision
1 2018-08-17 NMA,
HHE all Document created.
2 2018-09-04 HHE 3.2 Section Brown-Out Detector (BOD): Figure 4 updated.
3.4 Section System clock: Figure 6 updated.
3.17.1,
3.17.2 Sections Twisted pair and Unused Ethernet PHYs: VDDC and VDDIO corrected in Figure 29, Figure 30, and Figure 31.
Table 1: List of revisions
1.3 References to documents
This document refers to the following documents:
[1] Hilscher Gesellschaft für Systemautomation mbH: Technical Data Reference Guide, netX 90,
Revision 2, English, 2018.
[2] Hilscher Gesellschaft für Systemautomation mbH: Getting started, netX Studio CDT, netX 90
development, Revision 4, English, 2018.
Table 2: References to documents

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2 Basic concepts
2.1 netX 90 – introduction
The netX 90 is housed in a 144-pin BGA package and includes two Arm Cortex-M4 cores, on-chip
Flash memory, Fast Ethernet PHYs, and a DC/DC converter with POR circuit to reduce the BOM
costs for the hardware interface to a few passive components.
LVDS
LED
netX 90
PHY LVDS PHY
LED
iDPM
ARM Cortex-M4
100 MHz
xPIC
100 MHz D-TCM 8 KB
I-TCM 8 KB
xC 0
xC 1
Memory
Flash
1024 KB ECC
RAM
576 KB ECC
ROM
128 KB
Slave
Host Interface
DPM
SPM0-1
DMA0-3
SysTime
WDC0-1
System / Timer
CAN0-1
I2C0-1
SPI0-3
IO-Link0-7
EnDat2.20-1
SSI/BiSS0-1
UART0-1
Interface
Flash
512 KB ECC
RAM
64 KB ECC
Memory
ARM Cortex-M4 FPU
100 MHz
D-TCM 8 KB
I-TCM 8 KB
xPIC
100 MHz
CPU
DMA0-3
SysTime0-1
WDC0-1
System / Timer
TempSensor
CryptoCore
Shared
Memory I/F
Extension Bus
ETH MAC
SQI XIP
2x ADC0-1
TPIU
JTAG/SWD
BOD
POR
DC/DC
OSC/PLL
RC-OSC
Communication Application
CPU
GPIO0-3/Timer
MLED0-3
I2C0-1
Interface
Data Switch
10 mm x 10 mm 144-pin BGA
Data Switch
UART
PIO0-28
ClockSup
MPWM0-5
QuadDec0-1
2x ADC0-7
MLED0-7
SQI0-1
GPIO0-7/Timer
BD-NX90-V7
Figure 1: netX 90 Block diagram
Figure 1 shows the netX 90 block diagram. The chip architecture is composed of a communication
subsystem (left-hand side), a block of shared functions (bottom, center), and an application host
(right-hand side).
The communication segment features two flexible communication (xC) channels with switch and
IEEE 1588 support for all widely used industrial real-time communication protocols. Moreover, the
programmable xC architecture allows the software to flexibly adapt to emerging standards and
future network requirements.
The application segment uses a separate Cortex-M4 at 100 MHz with DSP and FPU support,
enhanced by a feature-rich set of on-chip peripherals with connectivity. Target applications include
motion control, sensors, actuators, encoders, remote I/O, etc. without being limited to them.
The block of shared functions serves both segments of the chip. Integrated firewalls in front of
each shared peripheral regulate access rights.
One of the highlights of the internal architecture is the logical separation between both segments.
This separation restricts software access to on-chip peripherals on either side and provides a layer
of protection against the impact of network attacks to the application. The built-in security features
enable developers to implement layers of security (as outlined in standard IEC 62443) coupled with
built-in diagnostics to monitor operating conditions for IIoT-enabled cloud services.

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2.2 netX 90 – use cases
You can use the netX 90 as
a single chip for standalone applications or
a companion chip with host interface
Hilscher provides the range of software protocol stacks for communication tasks as a prebuilt
firmware that is generally the same for both use cases apart from the user configuration. A
communication firmware consists of three parts:
1. Flash device label (FDL):
Includes device configuration data such as device ID, MAC addresses, etc.
2. Hardware configuration (HWC):
Includes hardware configuration data for either companion chip or single chip
3. Loadable firmware (LFW):
Includes the software protocol stack with the generic communication interface
The firmware configuration requires netX Studio CDT V1.0400 onwards. This is an Eclipse-based
Integrated Development Environment (IDE) from Hilscher that includes all components required to
configure, develop, and debug embedded applications. For a description, see reference [2].
Note: The Cortex-M4 of the application side is held in reset and clock gated after power-up.
The ROM integrated bootloader enables the application CPU during the boot sequence
if selected by the user’s hardware configuration (HWC).
The communication firmware creates a software layout in the dual-port memory (DPM). The virtual
DPM comprises up to 32 Kbytes SRAM with handshake cell registers accessible via the internal
DPM (iDPM) interface or the external host interface (HIF). As a result, the data exchange with the
protocol stack interface using the DPM provides a consistent API, independent of the use case.

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2.3 Design checklist
Hilscher supplies the software stacks for all widely used communication protocols, including OPC
UA and MQTT for IIoT connectivity, as a loadable firmware (LFW) as explained in section
Firmware overview and resources on page 51. LFW variants differ in terms of functionality,
protocols, and memory resources. For instance, the number of communication channels (created
by the LFW as a software layout in the DPM) ranges from one to three.
A typical LFW variant for traditional fieldbuses features one communication channel and requires
no additional external memory. In contrast to that, an LFW variant for real-time Ethernet protocols
with full webserver and IIoT functionality features three communication channels and requires
external SDRAM and SQI Flash.
Note: Hilscher has prepared a preliminary overview of LFW variants for which external
memory is recommended but not all software components have been implemented yet.
This means that technical details and memory requirements will be subject to change
until the release. The Hilscher knowledge base provides preliminary information. If you
cannot access this information, contact the netX Support.
Initially, Hilscher recommends considering SQI Flash memory as an assembly option in
embedded designs. SQI XIP is a dedicated interface that is not shared with any other
peripheral unit. If SDRAM is required, the memory capacity can be independent of
embedded hardware designs by considering SDRAM assembly options that are
compatible with pin and package.
If an LFW variant (communication side) requires SQI Flash, we recommend you not to
use this SQI Flash via the application side. Should the application software exceed the
on-chip memory, the ROM resident bootloader ensures that the full application
firmware is loaded after power-up (SQI Flash to SDRAM). The SDRAM interface can
operate in split mode which equally splits the memory between communication and
application side (same addressing in split and non-split mode).

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Figure 2 shows the design flow chart with a checklist. Special attention should be paid to the UART
console mode (see section Boot sequence on page 14).
Companion or
single chip?
netX 90 design
SQI Flash
required?
Required:
SDRAM circuit
Limitation:
Internal Ethernet PHYs only
No 3rd standard ETH MAC
Required:
25 MHz crystal
COM status LEDs
SYS LED at RDY/RUN
LC circuit on-chip DC/DC
Single power supply 3.3V
SDRAM required? SDRAM required?
Companion chip Single chip
Required:
SQI Flash circuit
Remark:
Assembly option?
Real - time Ethernet
(RTE) or Fieldbus
(FB)?
Required:
RJ45, LEDs, magnetics
Remark:
Voltage mode driver
RTE
Yes
Yes
Required:
SDRAM circuit
Limitation:
Internal Ethernet PHYs only
No Parallel DPM interface
Yes
UART console mode
required?
Required:
UART interface
Remark:
Review mode pins
Yes
Required:
Transceiver circuit
Not required:
No SDRAM/SQI Flash
FB
Unused components:
Check details for ADC, BOD,
and Ethernet PHY if unused
Finish
Figure 2: Checklist for a netX 90 design

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3 Basic circuits
3.1 Power supply
The netX 90 requires a single 3.3 V supply for VDDIO and the on-chip DC/DC buck converter which
generates the 1.2 V core voltage for VDDC.
In the worst case, the 3.3 V supply should be able to deliver a current of up to 350 mA for the netX
part and external memory.
Lower maximum currents may be sufficient for certain applications that do not use the Ethernet
ports or external memory. For details about power consumptions, see reference [1].
3.1.1 Integrated core voltage regulator
The integrated DC/DC step-down converter requires an external coil and capacitor as shown in
Figure 3. A recommended standard component is the inductor from Würth Elektronik, part number
74438323100. The capacitor is a ceramic type (X5R/X7R).
The selected 10 µH inductor and 10 µF output capacitor ensure that the integrated DC/DC delivers
supported output currents for the core voltage of the netX 90 only. Should other parts of the
embedded system require 1.2 V, we recommend you to implement a separate voltage supply.
Note: The VDDC power domain requires low ESR capacitors (e.g. 100 nF ceramic) close to
power pins connected in parallel with the larger 10 μF capacitor (no special “Ultra-Low-
ESR” required for the larger capacitor).
V
DDIO
V
SS
DCDC_LX_OUT
V
DDC
+3V3
GND
GND
1.2 V
netX 90
10µH
10µF
BS-NX90CoreVoltageRegulator-V1
Figure 3: netX core voltage

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3.2 Brown-Out Detector (BOD)
The BOD (Brown-Out Detector) is an analog input to which you can connect an external resistor
divider in order to monitor a high voltage (HV) supply, e.g. 10 V or 24 V. For adjusting the
threshold, choose the respective division factor of the resistors.
+24V
GND
netX 90
R
1a
BS-NX90BOD-USED-V2
R
1b
R
2
C
1 opt
V
DDIO
D
1 opt
BOD
vref_pw_bod
-
+
glitch filter
Figure 4: netX 90 Brown-Out Detector
The BOD pin
has a special ESD structure,
can be driven while VDDIO is not supplied,
is not HV-tolerant.
Depending on the division factor and the max. value of the monitored voltage, additional clamping
may be required. The example above uses an external diode to VDDIO for this purpose.
Note: If the BOD function is not used, connect it to +3.3V. Do not leave this pin unconnected!
BOD
netX 90
BS-NX90BOD-UNUSED-V1
V
DDIO
Figure 5: netX 90 Brown-Out Detector not used

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3.3 Power-on reset and reset in
The netX 90 has an integrated Power-On Reset (POR) circuit and optionally provides a Reset
Input (RST_INn) pin.
Parameter Conditions Min Typ Max Unit
Supply voltage VDDIO - 3.0 3.3 3.6 V
POR level Ramp from 0 to 3.3 V 2.73 2.8 2.87 V
POR hysteresis - 70 85 100 mV
Pulse length to pass the POR glitch filter - 5 20 µs
Release pulse extension of POR glitch filter - 150 300 µs
Table 3: POR device specification
External application hosts connected at the host interface or debug tools connected to the JTAG
interface typically use RST_INn to perform a hardware reset without going through a power cycle.
RST_INn is a Schmitt-trigger input with an internal pull-up resistor (nominal 50 kΩ) which can be
left open if not used. However, we recommend you to connect it to VDDIO (+3.3V) to improve EMC
behavior.
When placing the components during PCB design, position the reset source(s) near the reset
inputs of the netX to keep the traces of the reset signals short. Routing reset signals all over the
PCB may result in bad EMC behavior of the design since ESD may cause undesired resets of the
chip. We therefore recommend you to connect a 1 nF ceramic capacitor to GND close to the
RST_INn pin.
Section Legacy 20-pin JTAG interface on page 48 shows the reset circuit in combination with the
JTAG interface.

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3.4 System clock
The netX 90 uses an internal oscillator with an external crystal to generate the 25 MHz base clock.
A PLL generating all chip-internal clocks will stabilize this clock. Figure 6 shows the circuit of the
system clock generation:
netX 90
OSC_XTO
+1V2
GND
OSC_XTI
VDD_PLL
VSS
25MHz
10pF Rd
BS-NX90Oscillator-V2
10pF
100n
Figure 6: netX 90 system oscillator circuit
The values of the capacitors (C1and C2) and the damping resistor (Rd) depend on the crystal used.
For the Q 25.0-JXS32-12-10/30-T1-FU-LF from Jauch, C1= C2= 10 pF and Rd= 1 kΩ.
The load capacitance (CL) provided in the data sheet of the crystal can be used to estimate the
additional external load: C1= C2= CL- (Cin x Cout) / (Cin + Cout). For details on the pin capacitance
(Cin and Cout), see reference [1].
Rdrepresents the damping resistor that helps increase stability, save power, and suppress the gain
in the high frequency area. Rdis recommended by the crystal supplier or estimated on the basis of
the values given in the data sheet of the crystal (i.e. ESR, shunt capacitance, and drive level).
Before using a different crystal, always consult the data sheet or supplier of the crystal to
determine the appropriate values.
Note: If you want to use a different crystal, this crystal must have a frequency of 25 MHz and
a max. tolerance of +/- 100 ppm across the entire temperature range the design is
specified for!
The values for the Jauch crystal have been determined using the prototype chip of the
netX 90. These values still require confirmation for the final chip version.
Q1: We already have crystals of a different frequency or a higher tolerance in store. Can we
use them for the system oscillator?
A1: No. The 25 MHz clock is the basis for all other netX clocks. It influences any timing
around the netX, like SDRAM timing, Baud rates, Ethernet timing, etc. Deviating from
the specified frequency will most likely result in a system that does not work properly.

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3.5 Boot sequence
Every reset cycle starts by executing the built-in ROM code responsible for booting the device in a
secure and reliable manner. The ROM code features an integrated bootloader that recognizes the
mode pin settings and the state of the device. The ROM resident bootloader also offers a console
mode and an alternative boot mode that enable the handling of firmware programming. The boot
sequence starts automatically after either:
a software reset initiated by the firmware
a power cycle after turning on the device
a hardware reset via device pin RST_INn
For details about the ROM code boot sequence, see reference [1].
3.5.1 Configuration pins
The SYS LED at RDY and RUN indicate the operating status of the netX 90. To enter the console
mode or the alternative boot mode, the ROM code uses the following ways:
After a software reset cycle if the firmware initiated the mode before
After a hardware reset while the mode pin RDY / RUN is set before
After a hardware reset cycle if no valid firmware image was found
Note: Hardware reset means either a power cycle or the chip reset pin.
Figure 7shows the mode pins for both ROM code enabled modes.
SYS LED
Console mode
Alternative boot mode
Optional
SQI Flash
CS
DI(IO0) DO(IO1)
HOLD(IO3)
WP(IO2)
GND
VCC
CLK
GREEN
YELLOW
+3.3 V+3.3 V
+3.3 V
RUN
RDY
netX 90
SQI_CLK
SQI_CS0
SQI_SIO1/MISO
SQI_SIO0/MOSI
SQI_SIO2
SQI_SIO3
GND
GND
GND
270 270
1k
1k
10k 10k10k
Console mode
interface options
BS-NX90BootOption-V1
Figure 7: netX 90 RDY/RUN circuit

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3.5.1.1 Console mode
The console mode interface is determined by pin configuration settings at SQI_SOI0, SQI_SIO1,
and SQI_SOI2 after power-up (see Figure 7). If the pin configuration is left open (see Table 4),
internal pull-up resistors ensure that the default console mode is selected.
Console mode Chip interface SIO2 SIO1 SIO0
Default UART and Ethernet Open Open Open
TBD TBD TBD TBD TBD
7 UART Close Close Close
Table 4: Pin configuration console modes
The console mode interface based on UART or Ethernet enables the handling of firmware
programming using utility tools integrated in the netX Studio CDT.
Note: The ROM code provides an Ethernet switch and a webserver for firmware updates.
The documentation will be completed after the verification of the ROM code using final
silicon chips.
Q: Is the console mode interface for the UART mandatory in embedded designs?
A: The netX 90 chip can be programmed via JTAG/SWD as long as the debug interface is
not locked down by chip level security settings. If the debug interface is locked by the
user configuration, the user can optionally unlock the device again via a secure UART
connection using his private key.
For your information, the communication firmware provided by Hilscher optionally offers
a Marshaller functionality for diagnostic purposes which uses the same UART interface
as the console mode enabled by the ROM code. This particular UART is a shared
peripheral used by the communication or application software upon release of the ROM
code.
3.5.1.2 Alterative boot mode
The alternative boot bode starts a maintenance firmware used for:
Firmware update procedures:
A new firmware received via the web server or the host interface is stored either on-chip in
INTFLASH1 or off-chip in an externally connected SQI Flash. A software reset cycle initiated
by a software command starts the maintenance firmware which programs the new firmware.
Multiple firmware versions:
The netX 90 has a maintenance firmware stored in INTFLASH1 and holds multiple firmware
versions for different real-time Ethernet protocols in an externally connected SQI Flash. The
maintenance firmware programs the firmware selected by the system integrator, e.g. via a
rotary DIP-switch (or other ways).

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3.5.1.3 System RDY/RUN LED
A SYS LED (dual LED or two single LEDs) is defined for displaying the system status:
SYS LED Basic description
Green Communication firmware is running
Yellow ROM code active
Table 5: RDY / RUN LED colors
Designers can use LEDs with other colors, but we recommend using the Hilscher definition.
Especially when interpreting blink codes for troubleshooting, it is helpful if customer and Support
see the same colors.

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3.6 External memory
To connect external memory, the netX 90 provides 2 different interfaces that work independently:
Serial memory interface available for QSPI/SPI Flash
QSPI with the Execution-in-Place (XiP) function can also directly run
the program code for some low priority background tasks.
Parallel memory interface available for Flash/SRAM/SDRAM
Mostly used with a cost-effective 8 MB/16-bit SDRAM to improve the
overall performance of the internal memory.
When connecting memory components to the external parallel memory interface, designers should
always recalculate the capacitive load of these interface signals. The limitations are:
Parallel memory interface 20 pF and pad_ctrl set to high drive strength
As standard you can connect one memory device only.
The capacitive load directly influences the signal timing (the higher the load, the longer the signal
delay) whose scope with SDRAMs is limited. Since the allowed range of operating conditions
(min./max. voltage, min./max. temperature) additionally influences signal timing, capacity limits
need to be defined that ensure a safe operation across the entire voltage and temperature range.
If these capacity limits are exceeded, this may, to a certain extent, be compensated by two clock
phase parameters of the SDRAM interface. Such “out-of-spec-designs” are imaginable, but require
careful evaluation!
Note: Hilscher recommends using external memory components that have successfully
passed Hilscher’s component verification flow. The list of components:
https://kb.hilscher.com/display/NETX/Supported+hardware+components
The list of recommended components for the netX 90 will be updated at a later date.
Until further notice, follow the recommendations of this document or contact our netX
Support.
Only after successfully evaluating and testing a memory that is not listed, can you use
this memory together with the LFW version (communication firmware provided by
Hilscher) which requires external memory. For details, contact our netX Support!

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3.6.1 Serial memory interface
The netX 90 has a dedicated SPI/QSPI controller which supports execute in place (XiP), is not
shared with any other peripheral pin functions, and thus to be used for external serial flashes.
Depending on the use case, the SPI/SQI controller can serve the communication or application
side of the chip.
Additional SPI/QSPI controllers are available by predefined pin sharing options. They can also be
mapped to MMIO signals that are to be used with external peripheral devices.
SPI/QSPI uses high clock rates. This means: Keep the traces short.
Note: The terms QSPI (Quad SPI) and SQI (Serial Quad Interface) are used interchangeably.
netX 90 BGA pinout and REGDEF descriptions use the term SQI which is the more
appropriate term because the “quad” operates in 4-bit half-duplex mode and not as a
typical SPI in full-duplex mode with MOSI and MISO data lines.
3.6.1.1 QSPI Flash
The supported Flash type is a W25Q32V from Winbond Electronics.
XImportant:
Do not use any other Flash memories without the prior consent of Hilscher!
Table 6 shows the pin connection for netX 90:
- SPI_CS0n
SQI_CS0n SPI_CLK SQI_CLK SPI_MOSI SQI_MOSI (SQI_SIO0) SPI_MISO SQI_MISO (SQI_SIO1) SQI_SIO2 SQI_SIO3
netX 90 G1 H2 H1 G2 G3 H3
Table 6: SQI pin assignment netX 90
Figure 8 shows how to connect this Flash to netX 90:
netX 90 W25Q32V
CS
DO(IO1)DI(IO0)
HOLD(IO3)
WP(IO2)
+3.3V
GND
GND
VCCCLK
100n
SQI_MISO
SQI_MOSI
SQI_CLK
SQI_CS0
SQI_SIO2
SQI_SIO3
BS-NX90SQI-V1
10K
+3.3V
Figure 8: netX 90 with SQI Flash

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3.6.2 Parallel memory interface
The netX 90 contains two external parallel memory interface controllers that are mapped to the
same signal pins. The extension bus connects to external parallel Flash or SRAM. The SDRAM
controller connects to either 8-bit or 16-bit SDRAM.
Note: As explained previously, a block of shared peripherals serves both segments of the
chip. Both external parallel memory interfaces are shared peripherals equipped with
on-chip firewalls. In future, Hilscher will provide a special tool integrated in the netX
Studio CDT which will enable users to configure the on-chip firewalls. These settings
will be included in the hardware configuration file (*.hwc) to initialize the firewalls by the
ROM code during the boot sequence.
3.6.2.1 SDRAM
The SDRAM controller can operate in split mode equally dividing the memory in two halves: The
lower SDRAM half is accessible via the COM side, the upper half via the APP side. From a
software point of view, in split mode as well as non-split mode, the internal addressing is the same,
only the memory capacity is cut in half.
The SDRAM controller interfaces all types of Single-Data-Rate (SDR) SDRAM. The address range
is 0x10000000 to 0x1FFFFFFF (up to 256 Mbytes). The following parameter set is supported:
Parameter Option
Number of banks 2 or 4
Number of rows 2 K, 4 K or 8 K
Number of columns 256, 512, 1 K, 2 K or 4 K
Data widths 8-bit or 16-bit
Refresh-mode High or low priority
Power save mode SDRAM-self-refresh-mode with disabled clock switch on/off
Table 7: SDRAM controller parameter options
Note: The configuration of bank, row, and column is independent of the data widths. The
SDRAM controller can be configured using the hardware configuration tool integrated
in the netX Studio CDT.
The supported SDRAM type is a IS42/45S81600F or IS42/45S16800F from ISSI.
XImportant:
Do not use any other Flash memories without the prior consent of Hilscher!

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The following table shows a list of SDRAM types with memory size and organization. Note that this
list is incomplete and just represents possible examples, e.g. the IS42/45S16800F is organized in
4 K rows x 512 columns x 16-bits data widths x 4 banks, which is 8 Mbit x 16.
SDRAM memory size Organization Configuration Total memory size
64 Mbit 4 Mbit x 16 1 x 16 8 Mbytes
128 Mbit
8 Mbit x 16
1 x 16
16 Mbytes
16 Mbit x 8 1 x 8 16 Mbytes
256 Mbit 16 Mbit x 16 1 x 16 32 Mbytes
512 Mbit 32 Mbit x 16 1 x 16 64 Mbytes
Table 8: SDRAM memory size and organization examples
netX 90
SD_CSN
MEMDR_WEN
SD_CKE
SD_CLK
SD_RASN
SD_CASN
SD_DQM0
SD_D0-15
SD_A0-11
SD_BA0
SD_BA1
SD_DQM1 DQMH
A0-11
BA0
BA1
RAS
CAS
CS
WE
DQML
CLK
CKE
D0-15
netX 90
SD_CSN
MEMDR_WEN
SD_CKE
SD_CLK
SD_RASN
SD_CASN
SD_DQM0
SD_D0-7
SD_DQM1 NC
RAS
CAS
CS
WE
DQM
CLK
CKE
D0-7
SDRAM 8 Mbit x 16 (2M x16 x4 Banks) SDRAM 16 Mbit x 8 (4M x8 x4 Banks)
BS-NX90SDRAM-V1
SD_A12 NC
SD_A0-11
SD_BA0
A0-11
BA0
SD_A12 NC
SD_BA1 BA1
Figure 9: netX 90 SDRAM 1x 16-bit, 1x 8-bit
Q1: In the meantime DDR-3 RAM or higher is state of the art. Why are the netX chips
equipped with an outdated SDRAM interface only?
A1: Well, SDRAM isn’t really outdated. DDR RAM technology was invented for the short-
lived PC market on which it is commonly accepted that components have extremely
short life cycles, a limited operating condition range, as well as substantial power
consumption. Since DDR RAMs work with internal PLLs, they cannot be used on older
(slower) memory interfaces. DDR RAM technology is not suitable for the embedded /
industrial market where customers usually look for an availability of several years.
Moreover, even powerful embedded processor technology like ARM cannot necessarily
compete with common PC processors in terms of processing power. Thus, it would
make little sense to connect such processors to DDR RAMs anyway.