Hitachi MB-6890 User manual

HITACHI PERSONAL COMPUTER
MB’6890 SERVICE MANUAL
I
R0.3012 98
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HITACHI PERSONAL COMPUTER
MB-6890 SERVICE MANUAL
ev. O, 30.1.2.1
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Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
a
0
a
o
0
Q
U
0
Q
u
o
0
0
0
0
»
9
General .2
Features .2
Specification ........ 1,2
The name of each block .. .6
Function of I.C’s used ........ »»3
10
Explanation of the circuit .. ..
Memory map ..Q ....¢iii@;i== .. 31
Adjustment ..... ... 82
Service points ................. .. 85
The usage of inbuilt switches .. ... 87
Trouble shootings ............ ... 91
Operation check method ... ...102
Basic circuit diagram
Basic P.C.B. layout
Waveform of each block
Parts list
1
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(Y4
l. General
MB-6890 is the multi purpose personal computer, having BASIC high
language for programming.
The h i g h d ‹ m ‹ H d
and requirement from the users can be achieved by
built in interfaces for future expansion of the system.
2. Features
-Seven colour graphic display with separate command for the char
acters and their background colour.
-High resolution colour display up to 640 x200 pixels
is used for graphics and the combination of characters and gra-
phics can be used at the same time.
-Powerful "Extended BASIC" and "Monitor program" is stored in ROM.
-Standard interface for cassette tape recorder, printer and
Light pen is attached as standard.
-Built in interface connectors for future system expansion.
3. Specification
3.1. General specification
iIC Wl43pcs(CPU), 4pcs(Power unit)
Transistor 7pcs(CPU)[ 8pcs(Power unit) p
Diode lOpcs(CPU), 25pcs(Power unit)
Speaker output O.4W
_Speaker 6x9cm(l6 ohm) _.l pcs
I
Input/Output Cassette tape recorder connector(CASSETTE)
Light pen connector (L/PEN)
Colour display connector(COLOR)
Monocrome display connector(B/W)
RS-232C connector(RS-232C)
Printer connector(PRINTER)
*
C
Built in expansion connectors(I/F-l**I/F-6)
connector Memory expansion connectors(RAM3,RAM4)
__ ,
A
Power AClOOV(5O/60 Hz)
.g g_
.C
,
r
Power consumption 3OW( without any expansion of memory OT
interface card)
_
_
Dimension 45.0(W) x12.5(H) x5l.5(D) cm
W e i g h t
A
7kg
level
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3-2_ Connector pin signal.
(1) Cassette Tape Recorder(CASSETTEL
’W |
direction Signal pin pin Signal direction
(CPU -out) No. NO. (CPU -out
--~ remote 12GUD +--~
* - - * record 34lremote * - ’ *
1* - ‘ |Play 561_
(2) Light Penn./PEN)
direction Signal pin pin Signal direction
(CPU -Out) NO. NO. (CPU -Out)
--- 7675? 12f137§vV _ -
------ +5V 34LP VCMP ‘
----
--1* GND 5
(3) Colour displav(COLOR)
direction .pin pin .direction
(CPU -out) Slgnal No. No. Signal (CPU -out)
---» +I2V 12GND #-~~»
-- T>‘§‘13§TT 34QW --
-- T565 5
’
6R---»
-- G1 s B--»
(4) Rs-232C Int rfacems-232c)
direction _pin pin .direction
(CPU -out) Signal No. No. Signal (CPU -out),
‘
*- 12TxD ---*
*--- RxD 3 4 RTS --~*
--- CTS se-
i
r-- GND 78DCD - -
- 9 10 --
;n4|1
-11 g12 -
-~ 13 14 --
’- 15 16 --
-- 17 18 --
-- 19 20 --
-- 21 22 --
-- 23 24 --
}-- 25 -
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(5) PRINTER INTERFACE(PRINTER)
directien .min Qpin _
1direction V
(CPU -out) S3151
filo. No. Signal (CPU -out) 1
--~ STRB 12D,, -_-
--» D, 3
_
4D, ~_-~
---» D, Q5’_ 5D. -_»
--~ D, _
7QsD. --»
-- D,
_
9
’
10 A i ; T < --
--- BUSY
_
11 Q12 -
QQ-
,13 QL4 ,
-
II
-
_
15 15 GND --»
-17
0
18 -
Q
-19 20 1 -
-21 22 1 -
-23 24 -
-25
26 -
-27 QI 28 -
-\29 Q)
30 -
-31 Q32 -
»-_- GND 33 Q34
_
-
-
0
as Qas -
(5) Memory expansion (RAM3, RAM4 )
direction *Z *1 p i 1 1 Q
in *I *Z directicn
(CPU _QU_tI_ RAM4 RAM3 NO_ QO_ _
RAM3 RA114 _(CPU wut,
----» +12v Q+12v 1QQ
2GND QGND »---
-_» +sv Q+sv 3
‘
4‘ -sv Q-sv ---
--» D0 QD0 5Qe
’
D, DQ Q--
--- D, QD, 73QD1 D, Q---
--~ D. QD. 910 QD, D, --
---~» D. D. 11 QQ
12 QD, D, Q---
»----- A R QARD 13 Q14 QAR, AR, --
---» AR, QAR, Q15 16 QAR, AR, --
--~ -AR. QAR. _
I7 LE 18 1AR, AR,
_
»--
V-» AR, 3AR, 19 ’Q20 Qmis RAS ~-»
--» CASQHZ §CAS’/52 21 22 Q1?/E1 WEE Q2- --»
*_-~~
-» ROSFKIL fR 0 1 1 - ‘ 1 ‹ i ’ E
23 z24 QRuw 0UT§ww DUTQ -s--~»
_
--
___ 1 1 g D s E 1 ; e
A 8 5 - A S E I _ . _
25 .f 26 FA,11§"sE1I;
AE SEL Q’---
_i;N11;*Q_‘GND
0
2 7 Q _ _
28 Q»12v Q»12v ~--~-»
*l, £143 is for the address (58000
*2. RAM4 is for the address (SCOOO SEFFF)
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75 Ihterface expansion (I/F-I I/F-6)
i
direction
i
_ipinppin ,direction
(CPU -out) t
Signal No. Signal (cPU- out)
-4-_~ +5v 112 GND ---
-~-» iD.. 34D, ---»
-- D, 5i5D, --»
---» D. 1
1
sD5 ---
--» D1 9
’
10 D, »--»
--~ A,, 11
‘
12 A, ----
1---A
A{A, Q13 Q14 A, |--- ~{
---» A. 15 16 A. --»
--- A., 17 18 A, --»
4--» A. 19 20 A. ---
---- A . 21
A
22 A,, ---
--- A., 23 24 A,, --»
--» A,. 25 26 A,, --»
-_- BA 27
’
28 BS -~
---
‘
E555
‘
29
"
so EXROM-KIL --~
--- 11/w IN 31
‘
32 E356 --~
---» R/w OUT 33
A
34 VMA our --»
--» 1-: as as Q---»
1
--- ‘1§‘§ 37 38 FH ----
--- T55 as 40 mi ---
EXE4142WTTEE.--- EXE 41 42 WTTEE. ---
-- ETA’ 43 44 §XN‘1FSW ---
--» HALT ACK 45 46 SOUND IN ---
---»
‘
ISMCK 47 48 GND f--»
--- 2Mc1< 49 so GND 1--»
--~ -5V 51- 52 ‘}§;‘§‘{ffR)"§" --->
-1- -12v 53 54 +12V ---»
---- GND 55 56 +5v --
5
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4. Explanation of the each part
*Operation panel
._ ~»,‘
_. .,.., :_ __._
~"’"T M_‘ _ - »-=
’
V" f_ _’
"
I
*operation panel
~ W " C 5 G 5 ? ? 7 i W i ~
EI /<@@fafi'H switches
"fHfi@ ~
__ _
~are inside the cover)
.,’i’;i;@;_:_
N
_
-
_
’i
_
V
keyboard
*
\
(Q
eowsfz S W 5 - C C h i
votufvia j!MopE5wj_tC1q=?
RESET Switch
0} O
_O,,,¢¢- if \: ..;¢¢ msn asssr
WN MIX
POWER VOLUME MODE RESET
Powaaon display light
l) Power switch;
Push the switch then power is on with red light on. Push the
switch again then power is off.
2)VOLUME :
Control the loudness of the Click sound of the keyboard and
speaker volume.
3) MODE switch;
This switch selects characters/line mode ("1"=80 CH./line;
"o"=ao CH./line).
4) RESET switch;
RESET is triggered by this switch, and stops executing the
BASIC program, and returns to command level.
A
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*Rear, Connectors
Following six different interfaces are built in as
standard in M -6890.
1
*
p. mm .H~mi»;_ __‘_ _,_ ,
_
{_~ ,
~ . ’ + = .
’ . ’ Q ~ ’ z ~ : ‹ :
’_ ; ~ » ~ - =_f- :""’ ~’;» n " ¢ ’ 1 ~
‘’»-
> ’ ~ 1 ; . " 1 ’ - : F i - k c ’ - ’ AE§»:.-»;_ _V T _ » " j ! , , 2 5 f " ‘
;-¢_ ,_ . , ‘?’
g’ gf =
_ : i 2 , [ § » ; : i ; ’ § ’ + - ; § M ; i ? , ; @ 5 ’ , 2 f + l ; , 5 = i ! " 3 3 Z ’ § i : f 1 a a : H t l r f . " -
M; i ? , ; @ 5 ’ , 2
f+l; , 5 = i ! " 3 3 Z ’ § i : f 1 a a
:Htl rf."-
, f
-if » ¢ ~ f = t . = , \ 1 g f f , . ; - ~ - - , » f ’ ~ q ’ - .V ’
~~_ "F ~’
$Cassette tape recorder
(CASSETTE) ,
@Interface. /W
ex asion _
(I/F -1~»,$-513 \/
Qlight pen
(DPW)
__ Light pen
(BAP-3700)
fiCblour monitor """i -
(coLoR>
colour monitor
(c14-2170>
@MonochromeMonitor’ H
(ww) B
Green monitor
(KIZZDSSP)
5
ins-zazc.
Rs~z32c ..
()Other equipment which
has RS-232C interface.
isprinter
(PMNTER)
The six pairs of interface expansion connectors and two
’
connectors are inside the MB-6890.
pairs of memory expansion
7
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5. IC’s in use.
Type No.
Q
circuit no. function
Mpu HDeso9P/MCeao9L 1C1 central Pf C@SSif19 Unit
Hmssossp rcse CRTC
L.Sl HD4ea21P Q
LCSS Q PIA Q
HD4sssoP ICS4 ACIA
Icse, 1Cs1 Icss 1Cs9
1Cso,1Cs1 xcsz [css
RAM HM4716AP-1 IC54’ IC65’ IC66 IC57
RAM
ICss,1Cs9 Icvo IC71
IC12, IC73, IC14, IC75
1C1s,
/mnzsasc-ssc Qrcs BASIC Rom Q
ROM uPD2364C-331 IC4 BASIC Rom Q
uPD2364C-332 I C S BASIC, monitoraom
yPD2332C-328 IClO7 \characters,graphic ROM
HDHLSODP 1C2s, rczs, IC47, IC12s
2_
IC129, IC145 lnput NAND gate
Icaa, IC34, 1C4e, ICQ4
" D 7 L S " 2 P
[C142 2input NOR gate
HDNLSMP IC23, IC31, IC44, 1C91
inverter
IC100
HD74LS05P IC22, lC95, ICIOS open collector inverter
xczs, Icas, xC49, IC92
HD74LS08P IC96, IC136, IC143 2 input NAND gate
1C14s
HD74LS1OP 1C21 rC4s 3input AND gate
HD74LS11P Qrclss 3input AND gm? Q
H D 7 4 ~ 5 1 4 P [Cm Q
Stghmitt trigger inverter
V
HD74LS30P rcso, ICIO4 Sinput AND gate Q
HDm.S32P 1C29, 1C3z, IC97, 1Cl44] 2input NOP- gate
IC14, IC1s, ICI7, IC1s
HD14Ls74AP Icso, xCs3, xC93, IC99 Dtype flop flip
1C1o3 IC126. ICl30
Q
HD14LSseP Azcss, [C131 eX_Or qate Q
1C1s, IC101. rC1o2 Q
HD74LS93P ‘ICl22 1C123, rC124 4bit 2decimalcounter Q
IC\34
’
!
HD74LSI25AP ICQ4, me bus buffer gate Q
HD14LS13sP Q1C12.
IC13
_d&m’dQr_Q/demltiplexer
HD14LS139P ICU. IC137 -» »~ Q
Hm4LS1sw Q
xC9o
’
deselecwr/multiplexer
Q
HD74LS1_53P Q1C112
QQ
.» ~ 1
3
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Na type no. circuit no. function
i
Icas, IC51, IC111
28 HD74LSl57P
ICI" de-selector/rfzultiplexer
IHD74LSI58P Icus -- --
__§g_ HD14LS1e4P IC42 8bit parallel ahlft req!
31 sN14Ls1seP xcm 3bit shift reg.
""
1ca91c11, IC81, xcsz
32 HD74LSl74P rcse, ICIOS, XC109 Dtype flip flop
Icus
_:ET gate HD74LSl75P Icue "-’
T a sN741.s245N arcs bus tranceiver
EHD74LS257P IC113, IC114 data Seleeterhultiplexe-
__§§_a HD?"-5283? 1C4 4bit Qdecimal adder
1c1, ics, rcs, Iclo
37 HD74LS367AP xcle, Iczo, IC41, lcvs bus driver
IC79, Icso, Icsa, IC139
1c14o
Vi? HD74S04P IC43 inverter
EH - 3 7 4 5 0 5 IIC132 Jopen collector inverter
40 SN74S163N IC37 4bit counter
’T Hrmosp IC135 open collector inverter
ZHm41s3P 1C52, xcsa, IC54, IC55 data Selecter/multiplØxe
43 HD74159P IC86 decade):/demultiplexer
44 HD75l08AP IC128 duel line receiver
’Teena HD751saP IC119 quad line receiver
E; HD75189P IC120 " "
47 LMSGSCN lC127 FSK sig. demodulation PL
9
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Address DUS(AOA¢Al5)
*HD6809P/MC6809L
MTU: Micro Processing Unit
(1) Pin arrangement
GND------~-----V" ll E51HA|_r’-._--._ ..-. __ H,"
Non-Mukabln lnwrum ----- - ------ NMI ExYAL_ _____ ___ _____ __ G y m
| \ ¢ " U 9 K
RMIUMI ~"’ - ’-"~~ IRQ Bgg] SXTAL _______ _____En Icwnd
Pm Immun: Request -~--~~~--~- FIRQ ¢-| gig ___ ____ _____R___t
=~= B5 nss Mm-,Y ........ -.-..M.m.,, ,.,,_,,
Bus Avlxiauiq -- -------- BA BQ_ _ _ _ _ _ _ _ _ _ _ __ __ uu______w_
B15 ---~-------- ,.. ._
*
‘V)
___ "’ ’Z """ " " " " ’"" Enabh
HD6809p ommanso- -~--DumMemoryAmer/au.Requen
~--Dum Memory Amer/au. Requen
A2 IE 3|
(MPU) _Do W
A3 mEE Dv
A4 D2
A5 D3
Addrusi eu! <A. mD. Dua nu,
A ’B Ds
AU EEDs
‘A9" E!o1)
AW @@AIS
A" mmA14 AddrnuEus
\A’1EE n|Au
(2) The function of each pin.
Two pins
’
*
*Power ground (Vcc,Vss)
are used to supply power to the part; Vss is ground or
Ovolts,while Vcc is +5.0 V+/- 5%.
dto out ut address information Sixteen pins are use p
onto the Adress Bus. When the processor does not require the bus for
ttddress FFFF R/W- High,and BS=Lowadata transfer, it will ou pu__a 16,
-
This is the "dummy access" or VMA cycle. Address are valid on the
rising edge ofQ. All address bus drivers are made high impedance when
c * * " = i l a b l e ( B A ) is High. Each pin will drive one Shottky
\.J\.L\-bJ\4l¢ LJIJJ FXVQL
TTL load or four LS TTL loads, and typically 9OpF.
’d nication with the system bi-directional
*Data Bus (D-o/D7)
These eiggt pins provi ecommu
data bus. Each pin will drive one Schottky TTL load or four LS TTL
loads, and typically l3OpF.
*Read/Write(R/W)
This signal indicates e
bus. ALow indicates that the MPU is writing data onto the data bus.
R/W is made high impedance when BA is High. R/W is valid on the
th direction of data transfer on the data
rising edge of Q.
*R ‹ S ‹ t ( R E S ;
A Low level on this Schmitt trigger input for greater than one bus
cycle will reset the MPU. The Reset vectors are fetched from locations
‘’_
-Din
TFSEl6and
FFFFl6 when Interrupt Acknowledge is true,(BA.BS-l). ur g
initial power on, the Reset line should be held Low until the clock
oscillator is fully operational.
Because the HD6809 Reset pin has aSchmitt trigger input with a
threshold voltage higher than that of standard peripherals,
1YD
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\’k
asimple R/C network may be used to reset the entire system.This
higher threshold voltage ensures that all peripherals are out of
the reset state before the Processor.
*HALT
A Low level on this input pin will cause the MPU to stop running at
the end of the present instruction and remainhelted indefinitely
without loss of data. When halted, the BA output is driven High indicat-
ing the buses are high impedance. BS is also High which indicates the
processor is in the Halt or Bus Grant state.
*HALT
ALow level on this input will cause the MPU to stop running at the
end of the present instruction and remain halted indefinitelywithout
loss of data. When halted, the BA output is driven High indicating
the buses are high impedance. BS is also High which indicates
the processor is in the Halt or Bus Grant State,
Bus Available, Bus Status(BA,BS)
The BA output is an indication of an internal control signal which
makes the MOS buses of the MPU high impedance. This signal does not
imply that the bus will be available for more than one cycle. when BA goes
Low, an additional dead cycle will elapse before the MPU acquires the bus.
The BS output signal, when decoded with BA, representing the MPU
state(valid with leading edge of Q).
MPU State Definition
BA |as MPU stare
00Normal (Running)
01Interrupt or RESET Acknowledge
10SYNC Acknowledge
11HALT or Bus Grant
interrup Acknowledge is th§_indicated during both cycle of ahardware
vector fetch(RES,NMI,FIRQ,IRQ,SWI,SWI2,SWI3). This signal, plus decod-
ing of the lower four address lines,can provide the user with an
indication of which interru tlevel ‘b
by device.
Sync Acknowledge is indicated whi
synchronization on an interrupt line.
Halt/Bus Grant is true when the HD6809 is in aHalt or Bus Grant
condition.
pis eing served and allow vectoring
le the MPU is waiting for external
11
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*Non Maskable Interrupt (NMI)
Anegative edge on this input requests that anonmaskable interrupt
sequence be generated. Anon-maskeble interrupt cannot be inhibited
by the program, and also has ahigher priority than E I R Q , I R Q
or software
interrupt.
*Fast-Interrupt Request(FIRQ)
ALow level on this input pin will initiate
provided its mask bit(F) in the CC is_§lear.
over the standard Interrupt Request(IRQ),and
it stacks only the contents of the condition
program counter.
*Interrupt Request(I§Q)
A Low level input on this pin will initiate
provided the mask bit(I) in the CC is clear.
afast interrupt sequence
This sequence has priority
is fast in the sense that
code register and the
an interrupt Request sequence
Since IRQ stacks the entire
machine state it provides aslower response to interrupt than FIRQ,IRQ
also has alower priority than FIRQ.
*E, Q
Eis similar to theHD468OO bus timing signal §Z52;Q
is aquadrature
clock signal which leads E.Address from the MPU will be valid with
the leading edge of Q. Data is latched on the falling edge of E.
*MRDY
This input control signal allows stretching of Eand Qto extend data
access time.
*DMA/BREQ _
The DMA/BREQ input provides fa method of suspending execution and
acquiring the MPU bus for another use. Typical uses include DMA and
dynamic memory refresh. When BA goes Low, the DMA device should be
taken off the bus.
~HD45821E
(PIA 3Peripheral Interface Adapter) *PIA INTERFACE SIGNALS FOR MPU
(U pin arrangement _,___ __ __. ._ __ _ ._ _.
KFLA aleuirectional uataLD»~jU7)
(GNDHM CA’ The bi-directional data Qines
PM CM (D6’D7)allow the transfer of
PM WOT data between the MPU and the PIA.
PM %§ The data bus output drivers are
PM R50 three state devices that remain
PM RS, in the high impedance(off) state
,As m exception when the MPU performs
PM 0 aPIA read operation.
PA1 32 D1
no HD46821P nz *PIA Enable(E)
Pm (Pm) DJ The enable pulse,E, is the only
N215 FED#
Itiming signal that is supplied
P91 05 to the PIA. Timing of all other
PB* D6 signals is referenced to the leading
:Es Z and trailing edges of the Epulse. 6
Q *PIA Read/wri§;e
C82 CSD This signal is generated by the
(5\/WEE:
: RM MPU to control the direction of
T2
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data transfers on the Data Bus. ALow state on
input buffers and data is transferred from the
signal if the device has been selected. AHigh
the PIA for atransfer of data to the bus. The
the PIA line enables the
MPU to the PIA on the E
on the R/W line sets up
PIA output buffers are
enabled when the proper address and the and the enable pulse Eare present
*Reset(RES)
The active Low RES line is used to reset all register bits in the
PIA to alogical zero Low. This line can be used as a power on reset
and as amaster reset during system operation.
*PIA Chip se1e
These three input signals are used to select the PIA. CS and CS
rn1~|a{- kr: Uifvln an/4 PC m11c+- Ha Tr\v.1 Fnr cc1c>/
ma-- -t nigh and e-2 mu-. be ao" lor -election
transfers are then performed under the control
of the devgce. Dat;
of the Eand R/W signals.
The chip select lines must be stable for the duration of the Epulse.
*PIA Register Select(RSOand RS1)
The two register lines are used to select the various registers inside
the PIA. These two lines are used in conjunction with internal Control
Registers to select aparticular register that is to be written or read.
The register and chip select lines should be stable for the duration
of the Epulse while in the read or write cycle.
*Interrupt Request(IRQA and IRQB)
The active Low Interrupt Request lines(IRQA and IRQB) act to interrupt
the MPU either directly or through interrupt priority circuitry. These
lines are open drain(no load device) .This permits all interrupt requ-
est lines to be tied together in awire QR_configuration and accept
up to 1.6 mA curret from outside. gagh IRQ line has two internal inter-
rupt flag bits that can cause the IRQ line to go Low. Each flag
bit is associated with aparticular peripheral interrupt line. Also
four interrupt enable bits are provided in the PIA which may be used
to inhibit aparticular interrupt from aperipheral device.
Servicing an interrupt by the MPU may be accomplished by asoftware
routine that,on aprioritized basis,seqentially reads and tests the
two control registers in each PIA for interrupt flag bits that are set.
The interrupt flags are cleared(zeroed) as a result of an MPU Read
Peripheral Data Operation of the corresponding data register. When
these lines are used as interrupt inputs at least one Epulse must
occur from the inactive edge to the active edge of these interrupt
input signal to condition the edge sense network. If the interrupt flag
has been enabled and the edge sense circuit has been properly
conditioned,the interrupt flag will be set on the next active transition
of the interrupt input pin.
*PIA PERIPHERAL INTERFACE LINES
The PIA provides two 8bit bi-directional data bused and four
interrupt/control lines for interfacing to peripheral devices.
*Section APeripheral Data(PA’~PA7)
Each of the peripheraldata lines can be programmed to act as an
input or output. This is accomplished by setting alin the correspond-
ing Data Direction Register bit for those lines which are to be outputs.
AOin abit of the Data Direction Register causes the corresponding
peripheraldata line
Operation, the data
appears directly on
The d a t a i n Output
to act as aninput. During an MPU Read Peripheral Data
on the peripheral lines programmed to act as input
the corresponding MPU Data Bus lines.
Register Awill appear on the data lines that
are programmed to be outputs. Alogical lwritten into the register
will cause aHigh on the corresponding data line while aOresults in
T3
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*
aLow. Data in Output Register Amay be read by an M?U "Read Peripheral
Data A" operation when the corresponding lines are programmed as outputs.
This data will be read properly if the voltage on the peripheral data
lines is greater than 2.0 volts for alogic loutput and less than
0.8 volt for alogic 0output. Loading the output lines such that the
voltage on these lines does not reach full voltage causes the data
transferred into the MPU on aRead operation to differ from that contained
in the respective bit of Output Register A.
Section BPeripheral Data (PBSPB7)
The peripheral data lines on the BSection of the PIA can be programmed
to act as either inputs or outputs on a similar manner to P A P A 7 .
However, the output buffers driving these lines differ from Qhosedriving
lines P A 5 P A 7 .
They have three state capability,allowing them to enter
ahigh impedance state when the peripheral data line is used as ainput.
In addition, data on the peripheral data lines PB6»PB7
will be read
properly from those lines programmed as outputs. As outputs, these
lines are compatible with standard TTL and may also be used as a
source of up to 2.5 milliampere(typ.) at 1.5 volts to directly drive
the base of atransistor switch.
*Interrupt Input(CA1andCB1)
Peripheral Input lines CAl and CA2are input only lines that set the
interrupt flag of the control registers, The active transition for these
signals is also programmed by the two control registers.
*Peripheral Control (te2)
TheD91‘iDh91‘controllineCAcanbeprogrammedtoactasan
control line CA can be programmed to act as an
interrupt input or asa D9fiDh9%5l
control output. As an output, this
line is compatible with standard TTL. The function of this signal line
is programmed with Control Register A.
*Peripheral Control(CB2)
Peripheral COntrol line CB2may also be programmed to act as an inter-
rupt input or peripheral control output. As an input,this line has
High input impedance and is compatible with standard TTL. As an output it
is compatible with standard TTL and may also be used of up to 2.5 mill-
iampere(typ.) at 1.5 volts to directly drive the base of atransistor
switch. This line is controlled by Control Register B.
(ACIA 3Asynchronous Communication
Interface Adapter)
W) Pin arrangement
(GND) Vss
Rx Dafa
RICLK
TxCLK
EE
Tx Dau
EE
Gm
as
(31
M
(5V)V¢c
2
7
HD4685OP
MCM)
2;
23
E5
E5
Do
D1
D7
DJ
D4
Ds
D7
/W
||
|| ll
|$ EE
El
E5
|| I5
El Ds
IE
@~
E
R
SIGNAL FUNCTION
*Interface Signal for MPU
*Bi- Directional Data Bus(DO\D7)
The bi-directional data bus(DOf
D7) allow for data transfer
between the ACTA and the MPU.
The data bus output drivers are
three state devices that in the
high impedance(off) state ;xC9Dt
when the MPU perform an ACIA
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*Enable(E)
The Enable signal,E, is ahigh impedance TTL compatible input that
the bus input/output data buffers and clocks data to and from
the ACIA.
*Read/Write(R/W)
The R/W line is ahigh impedance input that is TTL compatible and
is used to control the direction of data flow through the ACIA’s
input/output data bus interface, When R/W is High(MPU Read cycle),
ACIA output drivers are turned on and aselected register is read.
when it is Low,the ACIA output drivers are turned off and the MTU
writes into aselected register. Therefore, the R/W signal is used
to select read only or write only registers within the ACIA.
*chip Select(CSO,CSl552)
These three high impedance TTL compatible input lines are used
to address the ACIA. The ACIA is selected when CSOandCS1 are High
and CS2 is Low.
*Register Select(RS)
The RS line is ahigh impedance input that is TTL compatible.
AHigh level is used to select the Transmit/Receive Data Registers
and aLow level the ControVStatusRegisters. The R/W signal line
is used in conjunction with Register Select to select the read
only register in each register pair.
*Interrupt Request(TR5)
IRQ is aTTL compatible,open drain(no internal_pullup),active Low
output that is used to interrupt the MPU. The IRQ output remains
Low as long as the cause of the interrupt is present and the app-
ropriate enable within the ACIA is set.
*Clock INputs
Separate high impedance TTL compatible inputs are provided
for clocking of transmitted and received data. Clock frequencies
of l, 16 or 64 times the data rate may be selected.
*Transmit Clock(Tx CLK)
The Tx CLK input is used for the clocking of transmitted
data. The transmitter initiates data on the negative transition of
the clock.
*Receive Clock(Rx CLK)
The Rx CLK input is used for synchronization of received data.
(In the Ølmode, the clock and data must be synchronized extern-
ally.) The receiver samples of the data on the positive transition
of the clock.
*Serial Input/Output Lines
*Receive Data(Rx Data)
The Rx Data line is ahigh impedance TTL compatible input through
which data is received in aserial format. Synchronization with
aclock for detection of data is accomplished internally when clock
rate are in the range of Oto SOO kbps when external synchroniza-
tion is utilized.
*Transmit Data(Tx Data)
The Tx Data output line’transfers serial data to amodem or other
peripheral. Data rates in the range of O to 500 kbps when external
synchronization is utilized.
N
T5
enables
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Modem CC>ntrol
The ACIA includes severa
aperipheral or modem. The functions included are CTS,RTS andDCD.
lfunctions that permit limited control of
Clear to Send(CTS)
This high impedance TTL compatible input provides automatic control
of the transmitting end of acommunications link via the modem CTS
active Low output by inhibiting the Transmit Data Register Empty(TDRE)
atatus bit.
Request to Send(RTS)
The RTS output enables the MPU to control aperipheral or modem via
the data bus. The RTF; output corresponds to the state of the Control
Register bits CRS and CR6. When CR6=O or both CR5 and CR6=l, the RTS
output is Low(the actiire state). This output can also be used for
Data Terminal R e a d y ( D 1 R ) t
Data Carrier Detect(DCD)
This high impedance TTL compatible input provides automatic control,
such as in_the receivingirld of acommunications link by means of
amodem DCD output. The DCD input inhibits and initializes the rec-
eiver section of the ACIA when High. A Low to High transition of the
DCD initiates an interrupt to the MPU to indicate the occurrence of
aloss of carrier when the Receiver Interrupt Enable bit is set.
(U p i n
arrangement
(GND) Vss
RES
LPSTB
MAG
MAI
MA2
A4
MAS
As
MAT
MAB
A9
MA10
MAH
MAI 2
MAI]
DISPTMG
CUDISP
(5VI Voc
_
E
E-E
HD46505SP
(CRTC)
EE vsvnc
Hsvmc
nm
nm
RA2
mu
cn
oz
I
I
l
IDs
I
Es‘
,
l
IEE mw
Ell CLK
(CRTC 3CRT Controller)
ll
4
5
BEH
MAJ RAA
MEl Do
E] EE
MIE gn
Ill so D3
’2 29 D4
MIl] as os
IB 27
S25 D1
Eas
if zas
23 E
IFUNCTION OF SIGNAL LINE
The CRTC provides 13 int f’
al
interface signals to CRT d i s p l a y .
ace sign Sto MPU and 25
0Interface Signals to MPU .
Bi-directional Data Bus (D0~D.,)
bt B ! ‘ d ’ e C £ I n 3 l
data b U 5 ( D o " D 1 )
are used for data transfer
br;/een
ide
CRTC and Ub;1PU.
The data bus outputs are 3-state
ers an remain in ehigh-impedance
state exce twhen
MPU performs aCRTC read operation.
P
Read/Write (R/W) /
R/W signal controls the direction of data transfer between
the CRTC
and MPU. When R/W is at H i g h
level, data of
CRTC IS transfered to MPU. When R/W is at L o w
level data
of MPU is transfered to CRTC.
’
Chip Select (C_§)
_ChipSelect signal (CS) is used to address the CRTC, When
CSIIS
at L o w
level, it enables R/W operation to CRTC inremaj
ff¢5I5i¢f5-
N o f m a u l
this Signal is derived from decoded address
signal of MPU under the condition that VMA sigial ot‘MPU is at
H i g h
level.
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Register Select (RS)
Register Select signal (RS) is used to select the address’
register and 18 control registers of the CRTC. When RS is at
L o w
level, the address register is selected and when RS is at
H i g h
level, control registers are selected. This signal is
normally aderivative of the lowest bit (AO) of MPU address bus.
Enable(El
Enable signal (E) is used as strobe signal in MPU Rfw
operation with the CRTC intemal registers. This signal is
normally aderivative of the HMCSSSOO System 95;clock.
Reset (lil ___
Reset siglal (RES) is an input signalused to reset the CRTC.
When RES is at L o w level, it forces the CRTC into the
following status. ~
_____
1) All the counters in the CRTC are cleared and the device
stops the display operation.
2) All the outputs go down to L o w
level;
3) Control registers in the CRTC are not affected and remain
unchanged.
This signal is different from other HMCS6800 family LSls in the
following functions and has restrictions for usage.
1) RES signal has capability of reset tiinction only when
LPSTB is at L o w
level.
2) The CRTC starts the display operation immediately after
RTS signal goes H i g h " .
0lnterfageSignals to CRT Display Device
Character Clock. QCLK)
CLK is astandard clock input signalwhich defines character
timingfor the CRTC display operation. This signal is normally
derived from the external high-speeddot timing logic.
Horizontal Sync (HSYNC)
HSYNC is an active H i g h
level signal which provides
horizontal synchronization for display device.
Vertical Sync NSYNC)
VSYNC is an active H i g h
level signalwhich provides verti-
cal synchronization for display device.
Display Timing (DISPTMG)
DISPTMG is an active H i g h
level signal which defines the
display period in horizontal and vertical raster scanning. It is
necessary to enable video signal only when DISPTMG is at
l ’ l i g h "
level.
Refresh Memory Address (MA0~MA13) _
MA0~MA,, are refresh memory address signals which are
used to access to refresh memory in order to refresh the CRT
screen periodically. These outputs enables 16k words max.
refresh memory access. So, for instance, these are applicable up
to 2000 characters/screen
and 8-pagesystem.
Raster Address (FlA0~RA4)
RA4,~RA., are raster address signalswhich are used to select
the raster of the character generator or graphic pattem
generator etc.
Cursor Display (CUDISP)
CUDISP is an active H i g h
level video signal which is used
to display the cursor on the CRT screen. ’This output is in-
hibited while DISPTMG is at l o w level. Normally this output
is mixed with video signal and provided to the CRT display
device.
Light_Pen Strobe (LPSTB)
LPSTB is an active H i g h
level input signal which accepts
strobe pulse detected by the light pen and control circuit. When
this signal is activated, the refresh memory address (MA,,~
MAH) which are shown in Fig. 2are stored in the 14-bit light
pen register. The stored refresh memory address need to be
corrected in software, taking the delay time of the display
device, light pen, and light pen control circuits into account.
(16,384 BIT DYNAMIC RAM)
’iff’ 255; Dan Ag A, A. A, H
*Direct access of l6l memory by 7
EEl Elj Baddress line(A6~A6) can not be done.
For that reason, select one line in
2=l28 under RASmode, then select
one row from 2=l23 under CAS mode.
IE] E1 E) Bthus_select one from l28xl28=l6,384
vu_o___
Dm wg nag A0 A; A__\;o_c: COlllblI’lB.l11Ol.’l..
U... ..... galqrnw
*The corresponding state of each signal
Dom -»-Dave OovWY
N>A6~
E"-Wf’9?11 El\UDl9’
FMS --~~# Fon Amress Seleul
U3--~Cc|um Address Selecn
pin is as follows;
RAS... Low level; line selection mode
CAS... Low level; row selection mode
’V~lE_..
Low level; write mode, the data from D. is written in RAM.
High level.. read mode, the data from l i l - I M
is read through Dout
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(8,\92 BYTE MASK Rom)
(5v)
V.-C A9 A9 Aszgmo Arr D1 D6 D5 D4 D3
& @BE B
BBEBB BEBN
I
Ar As A5 A4 A3 A2 An Ao Do Du Oz GND
A.»~Aw-» Address Bus
m~D~- Data Bus _
----- ChipSelect
----- Chip Select
Fig. 5-6
PD2364C is SK Byte Mask Rom (Read Only Memory) _The System Program is
written in this ROM.
I3 8192 B te is selected by 13 address line
1. The Memory Address of 2=
,y
(AO-Al2) .
2. The content of the Memory is outputted by 8lines of data line (DO-D7)
3. Chip Select (EE) is Low active and content of the memory is outputted
to data line .
Basic and Monitor System Program is written in three pieces of ROM
(uPD2364C-331, pPD2363C-332) in MB-6890. The Address is allocated by ROM
Address decoder as shown table 5-2.
TABLE 5-2
ROM IAddress
/1PD2se4c-aao |$Aoo o~sBFFF
,,PDz3e4c-331 1scooo ~sn1=z=1=
i»~ v- ~ - - A--Q-QQ
u P D 2 3 6 4 C 3 3 2
L"UU 5bb"
sFFF o~sFFFF
The block diagram of the ROM is shown at Fiq 5-7.
212 Output
M2 Buffer
A0 -> 31
A» o-Ag _.Q YYSelector
A2 o-+3 -. 3.
A5 o-_~$ _.L_f1D_ _______
CS
MQ_..H _.r-’ PrOqra;r
A5 S33 _>
A6 fi E; Memory A
AT
m3CS
Aao->C.’ _>O’ (8,l92>
A9 _.’S2 __ E1 5P W C
.. O_.2 ,Q Buffer
\
A||;¢-L i.._..¥
¥7§~ E-1
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