HP HP 16500B User manual

User’s Guide
Publication number 16500-97007
First Edition, February 1994
For Safety information, Warranties, and Regulatory
information, see the pages behind the index
© Copyright Hewlett-Packard Company 1987, 1990, 1993, 1994
All Rights Reserved
HP 16500B /16501A Logic
Analysis System

ii
HP 16500B—At a Glance
A systemof measurement modules
The HP 16500B is the mainframe ofthe
Hewlett-Packard Logic Analysis System.
It offers a modular structure for plug-in
cards with a wide range of state,timing,
oscilloscope, and pattern generator
capabilities.
A powerful, easy-to-use interface
The touchscreen interface offers pop-
up menus and color graphics to lead
you through measurement
configurations without having to
remember lots of steps. You can add a
keyboard or mouse to speed data input
and measurement configuration.

iii
The HP 16501A expands module
capacity
The HP 16501A is the add-on mainframe
for expanding the module capacity of
the HP 16500B. When the two are
connected, they forma single ten-card
system that is turned on and controlled
by the HP 16500B.
Intermodule measusurement capability
The HP 16500B offers intermodule
measurement features that allow you to
capture complex system activity.
Modules can
•be armed by an external instrument,
•be armed by another module in the
HP16500B or HP16501A frames, or
•be used to arm an external
instrument.

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Install measurement modules in any
slot
Single card analyzers, oscilloscopes,
and other options can go in any slot of
the HP16500B or HP16501A. Youshould
generally begin installing cards starting
withthe bottom-mostslot and working
up.
Some measurement modules have
multiple cards. A multiple-card module
must be installed into adjacentslotsin
the same mainframe—that is, you
cannot install one card of the module
into the HP 16500B and the other into
the HP16501A.
Calibrate measurement modules after
installation
Some measurement modules are
sensitive to temperature and voltage
variations between different
mainframes. Thus, when you install
such a module in the mainframe, you
should calibrate it before using it to
ensure maximum measurement
precision and accuracy.
See the Service Guide for each
measurement module for installation
and calibration procedures.

In This Book
This User’s Guide shows you how to use
the HP 16500B Logic Analysis System in
your everyday debugging work.
Chapter 1, “Triggering,” shows you how to
set up the analyzer to trigger on the
various kinds of events present in your
system. Advanced triggering capability
allows you to look at only the program
states of interest when you are solving a
particular problem.
Chapter 2, “Intermodule Measurements,”
shows you how to configure multiple
HP 16500 modules and external
measurement instruments into a single
measurement system in which modules
trigger each other.
Chapter 3, “File Management,” shows you
how to transfer files to and from the
HP 16500B using flexible disks, LAN
interfaces, and other interfaces.
Chapter 4,“Concepts,” gives you a brief
introduction to the ideas underlying the
trigger sequencer and the inverse
assembler, two important components of
sophisticated logic analysis.
Chapter 5, “Solving Problems,” shows you
how to diagnose and correct the more
common types of problems that might
occur while you are making a
measurement.
Chapter 6, “Application Notes,” lists the
various application notes that HP has
published regarding the HP 16500B and
other similar HP logic analyzers. These
v
Triggering
1
Intermodule Measurements
2
File Management
3
Concepts
4
Solving Problems
5
Application Notes
6
Glossary
Index

notes will give you more information about specific application problems and
how to solve them using an HP logic analyzer.
See Also For general information on setup and operation of the HP 16500B, see the
HP 16500B /16501A Logic Analysis System User’s Reference.
For information on programming the HP 16500B using a computer controller
such as a workstation or personal computer, see the HP 16500B/16501A
Logic Analysis System Programmer’s Guide.
For information on logic analyzers, oscilloscopes, preprocessors, and other
logic analysis system options, see the User’s Reference manual for those
options.
vi

Contents
1Triggering
To store and time the execution of a subroutine 1–3
To trigger on the nth iteration of a loop 1–5
To trigger on the nth recursive call of a recursive function 1–7
To trigger on entry to a function 1–9
To capture a trace of activity associated with a write of known bad data to a
particular variable 1–11
To trigger on a loop that occasionally runs too long 1–12
To verify that all stacks and registers are restored correctly before exiting a
subroutine 1–13
To trigger after all status bus lines finish transitioning 1–15
To find the nth occurrence of asserting a chip select line 1–16
To verify that the chip select line of a memory chip is strobed after the ad-
dress on the address bus is stable 1–17
To trigger when expected data does not appear on the data bus from a re-
mote device when requested 1–18
To test minimum and maximum pulse limits 1–20
To detect a handshake violation 1–22
To detect bus contention 1–23
Cross-Arming Trigger Examples 1–24
To examine software execution when a timing violation occurs 1–25
To look at control and status signals during execution of a routine 1–26
2Intermodule Measurements
Intermodule Measurement Examples 2–4
To set up a group run of modules within the HP 16500B 2–5
To start a group run of modules from an external trigger source 2–7
To start an external instrument on command from a module within the HP
16500 and 16501 mainframe 2–9
To see the status of a module within an intermodule measurement 2–11
o see time correlation of each module within an intermodule measurement
2–12
To use a timing analyzer to detect a glitch 2–13
v
ii

To capture the waveform of a glitch 2–14
o capture state flow showing how your target system processes an interrupt
2–15
Using stimulus-response to test a circuit 2–17
To use a state analyzer to trigger timing analysis of a count-down on a set of
data lines 2–19
To use two state analyzers to monitor the activity of coprocessors in a target
system 2–20
Special displays 2–21
To interleave trace lists 2–22
To view trace lists and waveforms together on the same display 2–24
Skew Adjustment 2–26
To adjust for minimum skew between two modules involved in an intermod-
ule measurement 2–27
3 File Management
Transferring Files Using the Flexible Disk Drive 3–3
To save a measurement configuration 3–4
To load a measurement configuration 3–6
To save a trace list in ASCII format 3–8
To save a menu or measurement as a graphic image 3–10
To load system software 3–12
Using the HP 16500L LAN Interface 3–13
To set up the HP 16500B 3–14
To transfer data files from the HP 16500B system to your computer 3–16
To transfer graphics files from the HP 16500B system to your computer
3–18
4Concepts
The Trigger Sequencer 4–3
Contents
viii

The Inverse Assembler 4–10
Configuration Translation for Analyzer Modules 4–13
5 If You Have a Problem
Analyzer Problems 5–3
Intermittent data errors 5–3
Unwanted triggers 5–3
No Setup/Hold field on format screen 5–4
No activity on activity indicators 5–4
Capacitive loading 5–4
No trace list display 5–5
Preprocessor Problems 5–6
Target system will not boot up 5–6
Slow clock 5–7
Erratic trace measurements 5–7
Inverse Assembler Problems 5–9
No inverse assembly or incorrect inverse assembly 5–9
Inverse assembler will not load or run 5–10
Intermodule Measurement Problems 5–11
An event wasn't captured by one of the modules 5–11
Messages 5–12
“Default Calibration Factors Loaded” (HP 16540, 16541, and 16542) 5–12
“. . . Inverse Assembler Not Found” 5–12
“Measurement Initialization Error” 5–13
“No Configuration File Loaded” 5–14
“Selected File is Incompatible” 5–14
“Slow or Missing Clock” 5–14
“State Clock Violates Overdrive Specification” 5–15
“Time from Arm Greater Than 41.93 ms” 5–15
Contents
ix

“Waiting for Trigger” 5–15
6Application Notes
Contents
x

1
Triggering

Triggering
As you begin to understand a problem in your system, you may realize
that certain conditions must occur before the problem occurs. You can
use sequential triggering to ensure that those conditions have
occurred before the analyzer recognizes its trigger and captures
information.
You set up sequential triggering as follows:
•Select the Trigger menu for the module you are using.
•In the Trigger menu, define terms and associated values to be used
when searching through the sequence.
•In the Trigger menu, select the number of the state sequence level
you want to modify, and enter the appropriate store qualification,
sequence-advance specification, and sequence-Else specification.
If you aren’t familiar with the trigger menus, try working through the
examples in the Logic Analyzer Training Kit manual, or refer to the
User’s Reference for your analyzer.
1
2

To store and time the execution of a subroutine
Most systems software of any kind is composed of a hierarchy of functions
and procedures. During integration, testing, and performance evaluation, you
will want to look at specific procedures to verify that they are executing
correctly and that the implementation is efficient. The analyzer allows you to
do this by triggering on entry to the address range of the subroutine and
counting the elapsed time since the trigger state.
1Select the state analyzer Trigger menu.
2Set Count to Time.
Setting the Count to Time causes the state analyzer to store a time stamp for
each data point that is stored in trace memory. The trace list will show these
time stamps next to each state.
3Define a range term, such as Range1, to represent the address range
of the subroutine of interest.
You may need to examine the structure of your code to help determine this. If
your subroutine calls are really procedure calls, then there is likely to be
some code at the beginning of the routine that adjusts the stack for local
variable allocation. This will precede the address of the first statement in the
procedure. If your subroutine has no local storage and is called by a jump or
branch, then the first statement will also be the entry address.
4Under State Sequence Levels, enter the following sequence
specification:
•While storing “no state” Trigger on “In_range1” 1 time
•While storing “In_range1” Then find “Out_range1” 1 time
•Store “no state”
Example Suppose you want to trigger on entry to a routine called MY_SUB. You can
define the address of MY_SUB in the Format menu, allowing you to reference
the symbol name when setting up the trace specification. Assume that
MY_SUB extends for 0A hex locations. You can set up the trigger sequencer
as shown in the display.
Triggering
To store and time the execution of a subroutine
13

Trigger Setup for Storing Execution ofa Subroutine
For processors that do prefetching of instructions or have pipelined
architectures, you may want to add partor all of the depth of the pipeline to the
start address for In_Range1 to ensure that the analyzer does not trigger on a
prefetched but unexecuted state.
Triggering
To store and time the execution of a subroutine
1
4

To trigger on the nth iteration of a loop
Traditional debugging requires print statements around the area of interest.
This is not possible in most embedded systems designs. But, the analyzer
allows you to view the system’s behavior when a particular event occurs.
Suppose that your system behaves incorrectly on the last iteration of a loop,
which, in this instance, happens to be the 10th iteration. You can use the
analyzer’s triggering capabilities to capture that iteration and subsequent
processor activity.
1Select the state analyzer Trigger menu.
2Define the terms LP_START and LP_END to represent the start and
end addresses of statements in the loop, and LP_EXIT to represent
the first statement executed after the loop terminates.
3Under State Sequence Levels, enter the following sequence
specification:
•While storing “no state” Find LP_END 1 time
•While storing “anystate” TRIGGER on LP_START 9 times; Else on
“LP_EXIT” go to level 1
•Store “anystate”
The above sequence specification has some advantages and a potential
problem. The advantages are that a pipelined processor won't trigger until it
has executed the loop 10 times. Requiring LP_END to be seen at least once
first ensures that the processor actually entered the loop; then, 9 more
iterations of LP_START is really the 10th iteration of the loop. Also, no
trigger occurs if the loop executes less than 10 times: the analyzer sees
LP_EXIT and restarts the trigger sequence. The potential problem is that
LP_EXIT may be too near LP_END and thus appear on the bus during a
prefetch. The analyzer will constantly restart the sequence and will never
trigger. The solution to this problem depends on the structure of your code.
You may need to experiment with different trigger sequences to find one that
captures only the data you wish to view.
Triggering
To trigger on the nth iteration of a loop
15

Trigger Setup for Triggering on the 10th Iteration of a Loop
Triggering
To trigger on the nth iteration of a loop
1
6

To trigger on the nth recursive call of a recursive
function
1Select the state analyzer Trigger menu.
2Define the terms CALL_ADD, F_START, and F_END to represent the
called address of the recursive function, and the start and end
addresses of the function. Define F_EXIT to represent the address of
the first program statement executed after the original recursive call
has terminated.
Typically, CALL_ADD is the address of the code that sets up the activation
record on the stack, F_START is the address of the first statement in the
function, and F_END is the address of the last instruction of the function,
which does not necessarily correspond to the address of the last statement. If
the start of the function and the address called by recursive calls are the
same, or you are not interested in the function initialization code, you can use
F_START for both CALL_ADD and F_START.
3Under State Sequence Levels, enter the following sequence
specification:
•While storing “no state” Find “F_END” 1 time
•While storing “anystate” Then find “F_START” 1 time
•While storing “anystate” TRIGGER on “CALL_ADD” 20 times Else on
“F_EXIT” go to level 1
•Store “anystate”
As with the trigger specification for “To trigger on the nth iteration of a loop,”
this specification helps avoid potential problems on pipelined processors by
requiring that the processor already be in the first recursive call before
advancing the sequencer. Depending on the exact code used for the calls, you
may need to experiment with different trigger sequences to find one that
captures only the data you wish to view.
Triggering
To trigger on the nth recursive call of a recursive function
17

Triggering on the 22nd Call of a Recursive Function
Triggering
To trigger on the nth recursive call of a recursive function
1
8

To trigger on entry to a function
This sequence triggers on entry to a function only when it is called by one
particular function.
1Select the state analyzer Trigger menu.
2Define the terms F1_START and F1_END to represent the start and
end addresses of the calling function. Define F2_START to represent
the start address of the called function.
3Under State Sequence Levels, enter the following sequence
specification:
•While storing “anystate” Find “F1_START” 1 time
•While storing “anystate” TRIGGER on “F2_START” 1 time Else on
“F1_END” go to level 1
•Store “anystate”
This sequence specification assumes there is some conditional logic in
function F1 that chooses whether or not to call function F2. Thus, if F1 ends
without the analyzer having seen F2, the sequence restarts.
The specification also stores all execution inside function F1, whether or not
F2 was called. If you are interested only in the execution of F1, without the
code that led to its invocation, you can change the storage specification from
“anystate” to “nostate” for the second sequence term.
Triggering
To trigger on entry to a function
19

Triggering on Entry to a Function
Triggering
To trigger on entry to a function
1
10