HP 27130A Product manual

HP 27130A
EIGHT -CHANNEL MULTIPLEXER
(MUX)
HEWLETT-PACKARD COMPANY
Roseville Networks Division
8000 Foothills Boulevard
Roseville,
California 95678
Technical Reference Manual
Flin- HEWLETT
~I!.I PACKARD
Card Assembly: 5061-4929
Date Code: A-2301
Manual Part No.2 7132-90006
Printed in U.S.A.
June 1983

PRINTING HISTORY
The Printing History below identifies the Edition of this Manual and any Updates that are
included. Periodically, update packages are distributed which contain replacement pages to
be merged into the manual, including
an updated copy of this Printing History page. Also,
the update may contain
write-in instructions.
Each reprinting of this manual will incorporate all past updates; however, no new
informa-
tion will be added. Thus, the reprinted copy will be identical in contenf.to prior printings
of
the same edition with its user-inserted update information. New editions of this
manual
will contain new information, as well as updates.
First Edition
................ June 1983
NOTICE
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO
THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Hewlett-Packard shall not be liable for errors contained herein or for incidental or con-
sequential damages in connection with the furnishing, performance, or use of this material.
This document contains proprietary information which
is protected by copyright. All
rights are reserved. No
part of this document may be photocopied or reproduced without
the prior
written consent of Hewlett-Packard Company.
Copyright (c) 1983 by HEWLETT-PACKARD COMPANY
ii

CONTENTS
Section I Page
GENERAL INFORMATION
PhY5icai De5cription .•.•..•••.••.••••••.•••••.••.•••••.•••...••.. 1-1
Functional Description ....• ·.;, •.•..•........•..•..............•... 1-1
Equipment Supplied ............................................... 1-3
Identification ................................................... 1-3
The Product .... ~ ............................................... 1-3
Printed Circuit Card ....••...•.•.••••....•..••...•.•.••.•.•••.. 1-3
fw1a.nua15 ..••.•.•••••...••••••.••.••••••.••••••••••••••••.••••••• 1-4
Specifications ................................................... 1-4
Section II
INSTALLATION
Page
Determining
Current Requirements .•.•.•...••••.••.•••..••••••.•... 2-1
Firmware
(EPROM> In5tallation ....•••.•.•.••••.•.••..•.••..••.•... 2-1
Jumpe r5 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2-3
Memory Configuration Jumper •.•...•...•...•...........••........ 2-3
Signature AnalY5i5 Jumper ..•.......•••..•.•.........•.•..•.••.. 2-3
liD Channel Interface ....•...•..•.•.••..•........•........•...... 2-5
Peripheral Device Interface ..•.••.••••..•.•...................... 2-5
In5talling the MUX .•....•••..•.•......•...•.•....•...•..•.•..•.. 2-12
Checkout ........................................................ 2-13
Reshipment ...................... a a .• a ••• a .• a a .•••••••••••••••• a •••• 2-14
Section III
Page
PRINCIPLES OF OPERATION
Functional de5cription ......•.•••..••.•...............•......•... 3-1
Sys t em C1 oc k5 .•.•••..••••••••••••••••••••••.•••••••.•••.••••••• 3- 3
Memory Addre55 Space ....•.......••.••••••••.••...........•.•... 3-3
110 Address Space ............... e ••••••••••• e .•••••••••••••••••• 3-6
Z-80B Microproc·e550r CPU ...............•....................... 3-6
Z-80 510/2 (Serial liD Controller> .•.•.••••..•..•.....•.••.•... 3-6
CTC (Counter Timer Circuit .....•••.• ~ •.•.••.•.•.•..•...••.••.. 3-19
Interfac·ing to the BIC .••..•.....•••.•.•••..••••.•.•..••.•••.. 3-19
Memory Interface Circuit (MIC) .•••.•.•.•.•..•••.•..•..•.••.•.. 3-24
Regi5 ter 0 - MI C Conf igurat ion •...•....•......•..•....•..•.. 3-24
Regi5ter 1 - DMA B Upper Byte of Memory Addre55 ....••....•.. 3-24
Regi5ter 2 - DMA Lower Byte of Memory Addre55 .......•.••.•.. 3-24
Regi5ter 3 - DMA B Configuration .•.•.•.••.••.....•..•....•.. 3-25
Regi5ter 4 - Lower Byte of Tran5fer Byte Count •.....•.••.••. 3-25
Regi 5ter 5 - DMA B 110 Port Addre55 •.•.•.........•..•.•..•.. 3-25
Regi5ter 6 - DMA A Upper Byte of Memory Addre55 .....•..•.•.. 3-25
Regi5ter 7 - DMA A Lower Byte of Memory Addre55 ............. 3-25
Regi5ter 8 - DMA A Configuration .......•..............•...•. 3-26
iii

CONTENTS
Register 9
Register A Lower Byte
of Transfer Byte Count ••.
DMA A I/O Port Address.
Register B Interrupt vector •••••••
Priority Interrupt Structure •..••••...•••••...
Wait State Circuits for Interrupt Acknowledge.
Diagnostic Hood for External Loop Back •..•••.•••
Section IV
PROGRAMvtING
MUX Programmable Features.
Transact ions ....••.•••.•••
Connect Logical Channel Request Format ••
Capabi lit ies •...•••••..••••••••••.••••••
Receive Character Processing ..
Receive Error Conditions •.
Signal Character.
Edit Mode •...•
Backspace ...
Line Deletion ..
Software Handshake with the Device••
Host
ENQ/ACK Handshake •.•...•.••.••...••.•..
Device X-ON/X-OFF Handshake.
Host
X-ON/X-OFF Handshake ......•..
Single Text Termination •..•..•.
End-On-Count Text Termination.
Alert 1 Mode ...........••.
Type Ahead and Echoing .••.
Receiving Transparent or Binary Data •..
Read Request Length ...•.......•..
Host Initiated Text Termination ..
Transmit Character Processing ...•..
Automatic Output Separators Appendage •..
Transmitting Transparent or Binary Data.
Buffer Flushing ..•......•.•..•..•..••••.•.
Programming the Receiver and Transmitter.
Parity in Transmitted or Received data •••••••..
Break Detection.
Handshake Timer.
AdditionaIOptions ..
Error Handling ...
Quoting Character Mode Option .•....••..•••••••.....
Conditional Output Separators Appendage .•.
Speed Sense Mode ..
Asynchronous Events.
Solicited Events.
Diagnost ics ......•.
iv
3-26
3-26
3-26
3-27
3-27
3-28
Page
4-1
4-2
4-2
4-4
. .... . 4-4
4-5
4-5
4-6
4-6
4-6
4-7
4-7
4-8
4-8
4-9
4-9
4-9
4-10
4-11
4-11
4-12
4-12
• • '4-12
4-12
4-12
4-13
4-15
4-15
4-15
4-16
4-16
4-18
4-18
4-18
4-19
4-19
4-20

CONTENTS
Connect Logical Channel Request Definitions •••.•••••••••••...•.. 4-21
Read Device
Data, Request Code = 1 .••••••.••••••.•••••••.•.•.• 4-22
Write Device Data, 'Request Code • 2 .••••••••••••••••••.•••.•.. 4-22
Read Card Information, Request Code = 4 .••...•••••••••••...••• 4-23
Subfunct ions 0 through 33 •.•.•••••••••••••••••••••••••.•.••. 4-23
Subfunction 249 -Read Data Status •...•.•••.••••.•••••....•. 4-23
Subfunction 250. Get Card RAM •.•••.•••••••••••••••••••.•.•. 4-23
Subfunct ion 254. Get Card Status .•••••..•.•••••••••••...••• 4-24
Write Card Configuration, Request Code =5 .•.... ~ ............. 4-25
Subfunct ion 0 ............................................... 4-25
Subfunction 1. Configure Read Option •••••••••.•••••••••.•.• 4-28
Subfunction 2. End-On-Count Length •••••••••••••••••.•••.••. 4-29
Subfunction 3. Alert 1 Read Mode ............................ 4-29
Subfunction 5. Transmission Mode .•...••••••••.•.•••••...••. 4-30
Subfunction 6. Backspace Character ..••••.••••••••••••...••. 4-30
Subfunction 7. Line Delete Character •••...•••••••••.•.•••.• 4-30
Subfunction 8. Backspace and Other Options ••••••.••••...••• 4-31
Subfunction 9. Device Handshake Option •••••••••••••••.•.•.. 4-32
Subfunct ion 10. Baud Rate .••••...•..•••...•••••••••••.•..•. 4-33
Subfunction 11. Character Length ........•.••••••••.••.•.•.. 4-33
Subfunction 12. Number Of Stop Bits .•..•••.••••.•••.•...... 4-34
Subfunct ion 13. Pari ty ....•.......•..•.•...•••••••••••.....• 4-34
Subfunction 18. Character Handshake Timer .••.•..•.......... 4-35
Subfunct ion 21. Host I nterrupt Mask ..•••••.••.•.••••••..... 4-35
Subfunction 22. Host X-ON/X-OFF Characters •••.•.•••••...... 4-36
Subfunction 23. Device X-ON/X-OFF Characters •••••••.•...••. 4-37
Subfunction 24. Host ENQ/ACK Characters .•..••••....•.....•. 4-37
Subfunction 25. Host ENQ/ACK Pacing Counter .••....•........ 4-37
Subfunction 27. Single Text Terminator for Echoing CR-LF •.. 4-37
Subfunct
ion 28. Output Separator .......•.••.....•.•........ 4-37
Subfunct ion 31. Addi t ional Opt ions ...•••.•..••..•••.•...... 4-38
Subfunction 32. Single Text Terminator ••..••••..•...•...•.• 4-39
Subfunct ion 33.· Card Wr i te Regi ster ..•••...•••••....•....•. 4-39
Subfunction 34. Set Port ID .........••••..••••..•.......•.. 4-40
Control Card, Request Code = 6 ........................•....... 4-40
RTS and WIC Block Definitions .....•........•.••.•.•..•...•...... 4-41
Event Block
Description .............•..•.••.••••...•.......... 4-42
Read Status Request Block Definitions ..•..••.•...•.......•...••. 4-44
Identity Information Block Definitions .•..••..••.....•.•.•..••.. 4-46
Default MUX Configuration ...•...•.•..••..••••...••.•.....•...•.. 4-46
Subfunct ion Ass ignment Summary ....•.•••..••••....•••••...•..••.• 4-48
Read Device Data .......•.............•...••................... 4-49
Wr i t e Dev ice De t a. . . . •. . . . . . •. . •••. •••. . . • •. •. •• •. . •. . . •. . . . . . 4-49
Read Card
Information .......•...•....•..•••...•..•....•.•...•. 4-49
Write Card Co~figuration ..•...•...••...••.............•.•..... 4-49
Control Card .................................................. 4-51
v

CONTENTS
Section V Page
MA I NTENANCE •••••••••••••••••••••••••••••••••••••••••••••••••••••••• 5-1
Section VI
REPLACEABLE PARTS
Page
Replaceable Parts .................................................. 6-1
Ordering Information •.•••..........•...•.•....................... ° •• 6-1
Section VII Page
SCHEMATI C DIAGRAMS •••••..•••...•••••••••••.••.•.•••••..••.•..•••.•• 7-1
Appendix A Page
ASC II CHARACTERS AND BI NARY CODES ......•........................... A-1
vi

Figure 1-1. HP 27130A MUX
1-0

GENERAL INFORMATION Irl~II.II'
This manual provides general information, installation, theory of operation, maintenance instruc-
tions, replaceable parts information, and servIcIng diagrams for the Hewlett-Packard
HP 27130A Eight-Channel Multiplexer (MUX). This chapter contains general information concern-
ing the MUX, and includes a description and specifications.
PHYSICAL DESCRIPTION
The HP 27130A Eight-Channel Multiplexer (MUX) is shown in fIgure 1-1 and consists of a printed
circuit card, a cable,
an RS-232-C connection box, and an installation manual.
FUNCTIONAL DESCRIPTION
The HP 27130A Eight-Channel Multiplexer provides multiplexed connections between a
Hewlett-Packard computer system and up to eight EIA RS-232-C/RS-423-A/RS-422-A type
devices (not including modems).
Figure
1- 2 shows a Hewlett-Packard computer system using CHANNEL I/O and the MUX.
(CHANNEL I/O is a Hewlett-Packard standard defining the physical and electrical characteristics
for
an I/O system consisting of an I/O channel, an I/O channel adapter, and I/O cards. The MUX is
one of the I/O cards.)
Note
that the computer system CPU and memory communicate directly along a Memory/Processor
Bus (MPB). I/O data to/from peripheral devices reaches the CPU/memory through the I/O channel,
the
I/O channel adapter, and an I/O card such as the MUX card. The I/O data is received from
and transmitted to peripheral devices by the
I/O card, which converts device-specific data to a
format compatible with
the I/O channel, and thus the computer. The I/O channel adapter (see
figure 1-2) controls the flow of traffic between the I/O channel and the memory/processor bus.
1-1

HP 27130A
I/O
CARD
I/o
CHANNEL
ADAPTER
I/O
CARD
I/O
CARD
MUX
CARD
..... ----,
I/O
DEVICE
o UP TO
o e
o DEVICES
I/O
DEVICE
Figure 1- 2. MUX in a Typical Hewlett -Packard Computer System
1-2

HP 27130A
The HP 27130A uses several of the Z-80A family of microprocessor components to relieve the host
computer of much
of the overhead. This permits a wide range of configurable transmission
modes
and formats, thus allowing connections to various CRT terminals, printing terminals, printers,
and plotters.
EQUIPMENT SUPPLIED
The standard HP 27130A Eight-Channel Multiplexer consists of the following items (see figure 1-1):
Printed circuit card, part number 5061-4929
Seventy centimeter (27.5 inch) RS-232-C connection box cable, part number 8120-4076
RS-232-C connection box; part number 12828-60001
Extension cable kit, part number 12828-60004
EPROMs, part numbers 27130-80003 and 27130-80004
Installation manual, paI't number 27130-90001
IDENTIFICA TION
The Product
Up to five digits and a letter (2 7130A in this case) are used to identify Hewlett-Packard products.
The five digits identify
the product; the letter indicates the revision level of the product.
Printed Circuit Card
The printed circuit card supplied with the HP 27130A product is identified by a part number
marked on the card. In addition to the
part number, the card is further identified by a letter and a
four-digit date code (e.g., A;...230l). This designation is placed below the part number. The letter
identifies the version of the etched circuit on the card. The date code (the four digits following
the letter) identifies
the electrical characteristics of the card with components mounted. Thus, the
complete part number on the MUX card is:
5061-4929
A-2301
If the date code stamped on the card does not agree with the date code on the title page of this
manual, there are differences between your card and the card described herein. These
dif-
ferences are described in manual supplements available at the nearest Hewlett-Packard Sales and
Service Office
(a list of Hewlett-Packard Sales and Service Offices is contained at the back of this
manual).
1-3

HP 27130A
Manuals
The Installation Manual (part number 27130-90001, supplied with the HP 27130A product) and
this manual (HP 27130 Technical Reference Manual, part number 27132-90006) are identified by
name and
part number. (Note that this manual is part of the HP 27132A Technical Reference
Package.) The name, part number, and publication date are printed on the title page of each
manual. If the manual is revised, the publication date is changed. In this manual, the "Printing
History" page (page ii) records the reprint dates and manual update record. Reprint dates for
the Installation Manual are printed on the title page.
SPECIFICA TIONS
Table 1-1 lists the specifications of the MUX.
Table 1-1. Specifications
FEATURES
* Eight full-duplex asynchronous serial lID ports
* EIA RS-232-C/RS-423-A compatible
* Simplex, echoplex, half-duplex, or full-duplex mode operation
* Asynchronous baud rates from 110 baud to 19.2K baud
* Programmable character size of 7 or 8 bits
* 1 or 2 stop bits
* Parity: programmable even, odd, forced 1, forced 0, or none
* Break detection
* Parity, overrun, and framing error detection
* Firmware based self-test
* Optional device handshakes: host or device controlled X-ON/X-OFF, or
host controlled ENQ/ACK
* 16-bit parallel interface to lID channel (backplane)
1-4

Table 1-1. Specifications (Continued)
PHYSICAL CHARACTERISTICS
Size: 193.04 mm long by 171.45 mm wide
by· 16.383 mm thick
(7.6 by 6.75 by 0.645 inches)
Weight: 283.5 grams (0.625 pound)
lID Channel Interconnects: 80-pin connector, J1
Device Interconnects: 72-pin connector, J2
POWER REQUIREMENTS
Current
(amps) Power
Dissipation
(watts)
Voltage
(typical)
(2-sigma)
(typical)
(2-sigma)
+SV
1.672A 1.890A 8.36W 9.4SW
+12V 0.052A
O.062A O.62W
0.74W
-12V O.075A O.08SA O.90W
1.02W
1-5
HP 27130A

INSTALLATION 1-
~----------------~[[]
This section provides information on installing and checking the operation of the MUX.
DETERMINING CURRENT REQUIREMENTS
The MUX circuit card obtains its operating voltages from the host computer> power supply through
the I/O channel. Before installing the card, it is necessary to determine whether the added curre,nt
will overload the power supply. The current requirements of the card are listed in the power
requirements
entry of table 1-1. Current requirements for all other I/O cards can be found in
the appropriate Technical Reference Manuals.
FIRMW ARE (EPROM) INSTALLATION
I CAUTION I
SOME OF THE COMPONENTS USED IN THIS
PRODUCT ARE SUSCEPTIBLE TO DAMAGE
BY
STATIC DISCHARGE. REFER TO THE SAFETY
CONSIDERATIONS INFORMATION AT THE
FRONT OF THIS MANUAL BEFORE HANDLING
THE CARD OR REMOVING OR REPLACING
COMPONENTS.
The EPROMs are installed in sockets provided on the MUX card as shown in figure 2-1. Ensure
that they are installed properly, and that they have not been damaged or loosened from their soc-
kets during shipping
..
2-1

HP 27130A
CPU
SIC
SID
CTC
MIC SID
CTC
EPROM SID
CTC
EPROM SID
JUMPER
Figure 2-1. Component and Jumper Locations
2-2

HP 27130A
Additionally, when installing or removing EPROMs, guard against bending or breaking the pins on
the component. These pins also can become folded between
the component and its socket, which
would result in
intermittent operation of the MUX. In most cases, a bent or damaged pin can be
straightened
with careful use of needle-nose pliers.
JUMPERS
There are two jumpers on the MUX card: a Memory Configuration jumper, and a Signature Analysis
jumper. The locations of these two jumpers are shown on figure
2-1.
Memory Configuration Jumper
The Memory Configuration jumper, WI, is an internally-connected, IS-pin dual in-line package (DIP)
shunt network. The jumper is used to configure the two memory sockets (U64 and U74) to ac-
comodate different kinds of EPROMs and static RAMs. The pin diagram of WI is shown in figure
2-2, pin functions are listed in table 2-1.
18 17 18 15 14 13 12 11 10
234 567 8 9
Figure 2-2. Memory Configuration Jumper
Signature Analysis Jumper
The Signature Analysis jumper, U34, is a I4-pin pre-programmed shunt network. The internal con-
nections of this jumper are set at the factory and are shown in figure 2-3 for information only.
2-3

HP 27130A
JUMPER
A
B
C
D
E
F
G
H
J
Table
2-1. Functions of the Memory Configuration Jumper
FUNCTION
Installed only when a 16K byte EPROM is used in socket U64.
Position A connects OCE2- of the Memory Interface Circuit (MIC)
to pin 20 (CE-) of the EPROM in socket U64. This enables the
EPROM in socket U64 whenever the lower 16K bytes of memory are.
addressed.
Installed only when a 4Kor 8K byte EPROM is used in socket U64.
Position B connects OCEO- of the MIC to pin 18 (CE-) of the 4K
byte EPROM or pin 20 (CE-) of the 8K byte EPROM, depending on
which
EPROM is installed in socket U64. This enables the EPROM
in socket U64 whenever the lower 8K bytes of memory are
addressed.
Installed only when a 4K byte EPROM is used in socket U64.
Position C connects +5V power to pin 24 (VDD) of the 4K byte
EPROM.
Installed only when a 16K byte EPROM is used in socket U64.
Position D connects A13 of the address bus to pin 24 (A13) of
the 16K byte EPROM.
Installed only when an 8K byte EPROM is used in socket U74.
Position E connects +5V power to pin 27 (VPP-) of the 8K byte
EPROM.
Installed only when an 8K byte static RAM is used in socket U74.
Position F connects WR- of the Z-80~ CPU to pin 27 (WE-) of the
static RAM, thus enabling the CPU to write to the RAM.
Installed only when a 2K byte static RAM is used in socket U74.
Position G connects WR- of the Z-80B CPU to pin 21 (WE-) of the
static RAM, thus enabling the CPU to write to the RAM.
Installed only when a 4K or 8K byte EPROM or an 8K byte static
RAM is used in socket U74. Position H connects A11 of the Z-80B
CPU address bus to pin 23 (A11) of the 4K or 8K byte EPROM or 8K
byte RAM, depending on which device is installed in ~ocket U74.
Installed to enable the MIC wait state signal when slow EPROMs
(access time greater than 250 nsec) are used in U64 or U74.
2-4

HP 27130A
1" 13 12 11 10 a
2 3 " 5 S 7
Figure 2- 3. Signature Analysis Jumper Internal Connections
1/0 CHANNEL INTERFACE
All interface between the MUX and the host computer occurs on the I/O channel. An 80-pin con-
nector (J 1) located on the MUX mates with a receptacle on the I/O channel. Connections to J1
are listed in table
2-2.
PERIPHERAL DEVICE INTERFACE
Interface between the MUX card and up to eight peripheral devices is via a 72-pin connector (J2)
to a connection panel (RS-232-C Connection Box, part number 12828-60001) and from there, via
eight separate connectors and eight cables, to
the peripheral devices. A connection diagram for the
connection box is shown in figure 2- 4.
Connector J2 pin assignments are shown in table 2-3. Pin assignments for J2 and the connec~
tion panel are shown in table 2-4. Note that, in table 2-4, there are eight pairs of Send Data (SD)
and Signal Ground (SG) lines, and eight pairs of Receive Data (RD) and Signal Ground (SG) lines; that
is, one pair of Send Data lines and one pair of Receive Data lines for each of the eight connectors
(JO through J7) to the eight peripheral devices.
2-5

HP 27130A
BALANCED
RECEIVER
~
~
'-
DRIVER
7
HP 271JOA
MVLTlPLEXER
850 pf
FRAME GROUND
II
II
RECEIVED MTA
(RD-)
SEND MTA (50-0
+12'V
SIGNAL GROUND
SEND COMMON (SO+)
RECEIVED OATA (RD+)
-12V
17.
,.
1
m
. 2
.
:5
4
~
1K
35
AAAA.
6
yyy
1-
111
7
1-
16 8
9
lK
36
~AA'"
10
yyy
20
R5-232-C PANEL
• 36-PIN CONNECTOR RECEIVED PINOUTS
RECEIVE CH.',NNEL PIN I
SEND CHoINNEl PIN *
RDO-JJ
R04-2~
500-34
S04-26
R01-J1 RD5-23
501-32
505-24
RD2-29 RD6-21
SD2-3O 506-22
ROJ-27
R07-1~
503-28
SD7-20
PROTECTIVE GROUND (M)
TRAN5MIlTED OATA (SA)
RECEIVED DATA (89)
REQUEST TO SEND (CA)
CLEAR TO SEND (ca)
o.t.TII SET AEADY (CC)
SIGNAL GROUND (,t,B)
CARRIER OETECT(CF)
ON (+12V)
OFF (-12\0
OATA TERt,lINAL READy (CO)
PERIPHE:I'W.
DEVICE
Figure 2-,4. Connections from MUX to Connection Box to Device
2-6

HP 27130A
Table 2-2. I/O Channel Connector Jl
PIN NO.
SIGNAL MNEMONIC SIGNAL DEFINITION
A1
RES Not used
A2 DB14-
Data Bus,
Bi t 14
A3 DB12- Data Bus, Bit
12
A4
GND Ground
AS DB10- Data Bus, Bi t 10
A6
DBB-
Data Bus,
Bit 8
A7
GND Ground
A8 DB6-
Data Bus,
Bit 6
A9 DB4- Data Bus, Bit 4
A10 GND
Ground
A11
DB2- Data Bus, Bit
2
A12
DBO-
Data Bus,
Bit
0
A13
GND Ground
A14 AD2-
Address Bus,
Bi t 2
A15 ADO- Address Bus, Bit
0
A16
GND Ground
A17 DOUT-
Data Out
A18 BPO- Bus Primitive Bit 0
A19
CEND- Channel End
A20 SYNC-
Synchronize
A21
GND Ground
A22
CCLK
Corrmon Clock
A23 GND Ground
A24 BR-
Burst Request
A25 DBYT- Device Byte
A26 MYAD- My Address
A27
GND Ground
A28 ---
Not used
A29
---
Not used
A30
--- Not used
A31
RES Not
used
A32 PFW-
Power-Fail Warning
A33 PPON Primary Power On
A34 GND
Ground
A35 AC-
Not used
A36
AC+
Not used
A37
-12-
-12V
A38
+12
+12V
A39
+5S
Not used
A40
+5P +5P
2-7