IDT 89HPES12N3 User manual

June 2006
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Printed in U.S.A.
©2006 Integrated Device Technology,Inc.
IDT™89HPES12N3
PCI Express® Switch
User Manual

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and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patentrights or other rights, of Integrated Device Technology, Inc.
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Notes
PES12N3 User Manual 1 June 7, 2006
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES12N3, a memberof IDT’s
PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan-
dard.
Finding Additional Information
Information not included inthis manual such as mechanicals, packagepin-outs, and electrical character-
istics can be found in thedata sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES12N3 Device Overview,” provides a complete introduction to the performance capa-
bilities of the 89HPES12N3. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.
Chapter 5, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES12N3.
Chapter 6, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug andhot-swap features in
the PES12N3.
Chapter 7, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES12N3.
Chapter 8, “General Purpose I/O,” describes how the eight General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions
Chapter 9, “Transparent Mode Operation,” describes how the PES12N3 can be configured during a
fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization.
Chapter 10, “Test and Debug,” discusses the six testmodes, in addition tothe normal operatingmode,
associated with the PES12N3.
Chapter 11, “JTAG Boundary Scan,” discusses an enhanced JTAGinterface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is representedby a high or low voltage. The termnegate or negation
is used to indicate that a signal is inactive or false.

IDT About This Manual Numeric Representations
PES12N3 User Manual 2 June 7, 2006
Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. To
define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the
right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to1) transition. Falling edge indicates ahigh-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Term Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
1 2 3 4
high-to-low
transition low-to-high
transition
single clock cycle

IDT About This Manual Register Terminology
PES12N3 User Manual 3 June 7, 2006
Notes
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications madeby PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bitsare initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.) Bits
are read-only after initialization and can only be reset (for write-once
by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with thisattribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with thisattribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus, soft-
ware must deal correctly with fields that are reserved. On reads, soft-
ware must use appropriate masks to extract the defined bits and not
rely on reserved bits being any particular value. On writes, software
must ensure that the values of reserved bit positions are preserved.
That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written
back.
Read Only RO Softwarecanonly readregisters/bitswith thisattribute. Contentsare
hardwired. Writing to a RO location has no effect.
Read Only and set by
Hardware ROS Software can only read registers/bits with this attribute. Contents are set by hardware and may change. Writing to a ROS location has no
effect.
Read and Write RW Software can both read and write bits with this attribute.
Table 2 Register Terminology (Sheet 1 of 2)
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

IDT About This Manual Use of Hypertext
PES12N3 User Manual 4 June 7, 2006
Notes
Use of Hypertext
In Chapter 9 there are tables which contain register names and page numbers highlighted in blue under
the Register Definition column. In pdf files, users can jump from the source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.
Revision History
February 8, 2006: Initial Publication.
June 7, 2006: Added revision YC information in Chapters 1 and 9.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. How-
ever, writing a value of zero to a bit with this attribute has no effect. A
RW1C bit can only be set to a value of 1 by a hardware event. To
clear a RW1C bit (i.e., change its value to zero) a value of one must
be written to the location. An RW1C bit is never cleared by hardware.
Read and Write when
Unlocked RWL Software can read the register/bits with this attribute. Writing to regis- ter/bits with this attribute will only cause the value to be modified if
the REGUNLOCK bit in the SWCNTL register is set. When the
REGUNLOCK bit is cleared, writes are ignored and the register/bits
are effectively read-only
Zero Zero A zero register or bit must be written with a value of zero and returns
a value of zero when read.
Type Abbreviation Description
Table 2 Register Terminology (Sheet 2 of 2)

Notes
PES12N3 User Manual i June 7, 2006
Table of Contents
About This Manual
Introduction.....................................................................................................................................1
Finding Additional Information...............................................................................................1
Content Summary...........................................................................................................................1
Signal Nomenclature ......................................................................................................................1
Numeric Representations...............................................................................................................2
Data Units.......................................................................................................................................2
Register Terminology......................................................................................................................3
Use of Hypertext.............................................................................................................................4
Revision History..............................................................................................................................4
1 PES12N3 Device Overview
Introduction..................................................................................................................................1-1
Features.......................................................................................................................................1-3
System Identification....................................................................................................................1-4
Vendor ID ...........................................................................................................................1-4
Device ID............................................................................................................................1-4
Revision ID.........................................................................................................................1-5
JTAG ID..............................................................................................................................1-5
Logic Diagram..............................................................................................................................1-6
Pin Description.............................................................................................................................1-7
Pin Characteristics.....................................................................................................................1-11
2 Clocking, Reset, and Initialization
Introduction..................................................................................................................................2-1
Initialization..................................................................................................................................2-1
Reset ...........................................................................................................................................2-3
Fundamental Reset............................................................................................................2-5
Hot Reset ...........................................................................................................................2-6
3 Link Operation
Introduction..................................................................................................................................3-1
Polarity Inversion.........................................................................................................................3-1
Link Width Negotiation.................................................................................................................3-1
Lane Reversal..............................................................................................................................3-1
Link Retraining.............................................................................................................................3-3
Link Down....................................................................................................................................3-3
Slot Power Limit Support.............................................................................................................3-3

IDT Table of Contents
PES12N3 User Manual ii June 7, 2006
Notes 4 Switch Operation
Introduction..................................................................................................................................4-1
Routing........................................................................................................................................4-3
Data Integrity...............................................................................................................................4-4
Switch Time-Outs ........................................................................................................................4-5
Locking........................................................................................................................................4-5
Interrupts......................................................................................................................................4-7
Switch Core Errors.......................................................................................................................4-8
5 Power Management
Introduction..................................................................................................................................5-1
PME Messages..................................................................................................................5-2
Link States...................................................................................................................................5-2
Active State Power Management ................................................................................................5-3
6 Hot-Plug and Hot-Swap
Introduction..................................................................................................................................6-1
Hot-Plug with Downstream Port(s) Connected to a Slot....................................................6-3
Hot-Plug with Switch on an Add-In Card............................................................................6-6
Hot-Swap.....................................................................................................................................6-7
7 SMBus Interfaces
Introduction..................................................................................................................................7-1
SMBus Registers.........................................................................................................................7-2
Master SMBus Interface..............................................................................................................7-4
Initialization ........................................................................................................................7-4
Serial EEPROM .................................................................................................................7-4
Hot-Plug I/O Expander.......................................................................................................7-8
Slave SMBus Interface................................................................................................................7-9
Initialization ........................................................................................................................7-9
SMBus Transactions..........................................................................................................7-9
8 General Purpose I/O
Introduction..................................................................................................................................8-1
GPIO Registers............................................................................................................................8-1
GPIO Configuration .....................................................................................................................8-2
GPIO Pin Configured as an Input.......................................................................................8-2
GPIO Pin Configured as an Output....................................................................................8-2
GPIO Pin Configured as an Alternate Function .................................................................8-2
9 Transparent Mode Operation
Introduction..................................................................................................................................9-1
End-to-End CRC..........................................................................................................................9-2
Interrupts......................................................................................................................................9-2
Error Detection and Handling ......................................................................................................9-2

IDT Table of Contents
PES12N3 User Manual iii June 7, 2006
Notes Configuration Requests......................................................................................................9-6
Port Configuration Space Organization.......................................................................................9-6
Upstream Port A Configuration Space Registers ........................................................................9-8
Register Specialization.....................................................................................................9-10
Downstream Port B Configuration Space Registers..................................................................9-11
Register Specialization.....................................................................................................9-13
Downstream Port C Configuration Space Registers..................................................................9-14
Register Specialization.....................................................................................................9-16
Generic PCI to PCI Bridge Register Definition ..........................................................................9-17
Type 1 Configuration Header Registers...........................................................................9-17
PCI Express Capability Structure.....................................................................................9-26
Power Management Capability Structure.........................................................................9-36
Message Signaled Interrupt Capability Structure.............................................................9-39
Switch Control and Status Registers................................................................................9-40
Extended Configuration Space Access and INTx Status Registers.................................9-49
PCI Express Virtual Channel Capability...........................................................................9-50
Test Mode Registers ........................................................................................................9-55
System Integrity ...............................................................................................................9-60
10 Test and Debug
Device Test Modes ....................................................................................................................10-1
10-bit Loopback Test Mode (SWMODE[3:0] = 0x8).........................................................10-1
Internal Pseudo Random Bit Stream Self-Test Test Mode (SWMODE[3:0] = 0xA)..........10-2
External Pseudo Random Bit Stream Self-Test Test Mode (SWMODE[3:0] = 0xB).........10-3
SerDes Broadcast Test Mode (SWMODE[3:0] = 0xD).....................................................10-3
SerDes Test Clock.....................................................................................................................10-5
11 JTAG Boundary Scan
Introduction................................................................................................................................11-1
Test Access Point ......................................................................................................................11-1
Signal Definitions.......................................................................................................................11-1
Boundary Scan Chain................................................................................................................11-3
Test Data Register (DR).............................................................................................................11-4
Boundary Scan Registers ................................................................................................11-4
Instruction Register (IR).............................................................................................................11-6
EXTEST...........................................................................................................................11-7
SAMPLE/PRELOAD ........................................................................................................11-7
BYPASS...........................................................................................................................11-7
CLAMP.............................................................................................................................11-8
DEVICEID........................................................................................................................11-8
VALIDATE ........................................................................................................................11-8
RESERVED......................................................................................................................11-8
UNUSED..........................................................................................................................11-8
Usage Considerations ...............................................................................................................11-9

IDT Table of Contents
PES12N3 User Manual iv June 7, 2006
Notes

Notes
PES12N3 User Manual v June 7, 2006
List of Tables
Table 1.1 PES12N3 Offset Device IDs.............................................................................................1-4
Table 1.2 PES12N3 Revision IDs.....................................................................................................1-5
Table 1.3 PCI Express Interface Pins...............................................................................................1-7
Table 1.4 SMBus Interface Pins.......................................................................................................1-8
Table 1.5 General Purpose I/O Pins.................................................................................................1-8
Table 1.6 System Pins......................................................................................................................1-9
Table 1.7 Test Pins.........................................................................................................................1-10
Table 1.8 Power and Ground Pins..................................................................................................1-10
Table 1.9 Pin Characteristics..........................................................................................................1-11
Table 2.1 Reference Clock Mode Encoding.....................................................................................2-1
Table 2.2 Boot Configuration Vector Signals....................................................................................2-2
Table 2.3 Reset Conditions and Their Effect....................................................................................2-3
Table 4.1 PES12N3 Buffer Sizes......................................................................................................4-2
Table 4.2 PES12N3 Advertised Flow Control Credits ......................................................................4-3
Table 4.3 Switch Routing Methods...................................................................................................4-4
Table 4.4 PCI Compatible INTx Aggregation....................................................................................4-7
Table 4.5 PES12N3 Upstream Port Bridge Interrupt Mapping.........................................................4-8
Table 5.6 PES12N3 Power Management State Transition Diagram................................................5-2
Table 6.7 Downstream Ports B and C Hot Plug Signals...................................................................6-3
Table 6.8 SMBus I/O Expander Signals...........................................................................................6-4
Table 6.9 Upstream Port A Hot Plug Signals....................................................................................6-6
Table 7.1 SMBUSSTS - SMBus Status............................................................................................7-2
Table 7.2 SMBUSCTL - SMBus Control...........................................................................................7-3
Table 7.3 Serial EEPROM SMBus Address.....................................................................................7-4
Table 7.4 Base Addresses for PCI Configuration Spaces in the PES12N3 .....................................7-5
Table 7.5 PES12N3 Compatible Serial EEPROMs..........................................................................7-5
Table 7.6 Serial EEPROM Initialization Errors .................................................................................7-8
Table 7.7 Slave SMBus Address When a Static Address is Selected..............................................7-9
Table 7.8 Slave SMBus Command Code Fields ............................................................................7-10
Table 7.9 CSR Register Read or Write Operation Byte Sequence ................................................7-11
Table 7.10 CSR Register Read or Write CMD Field Description......................................................7-11
Table 7.11 Serial EEPROM Read or Write Operation Byte Sequence.............................................7-12
Table 7.12 Serial EEPROM Read or Write CMD Field Description..................................................7-13
Table 8.1 General Purpose IO Registers..........................................................................................8-1
Table 8.2 General Purpose I/O Pin Alternate Function....................................................................8-2
Table 8.3 GPIO Pin Configuration....................................................................................................8-2
Table 9.1 Transparent Mode Port B and C Interrupts.......................................................................9-2
Table 9.2 Physical Layer Errors........................................................................................................9-3
Table 9.3 Data Link Layer Errors......................................................................................................9-3
Table 9.4 Transaction Layer Errors..................................................................................................9-4
Table 9.5 Malformed TLP Error Checks...........................................................................................9-4
Table 9.6 Upstream Port A Configuration Space Registers .............................................................9-8
Table 9.7 Downstream Port B Configuration Space Registers.......................................................9-11
Table 9.8 Downstream Port C Configuration Space Registers.......................................................9-14
Table 10.1 PRBS LFSR Symbol Output...........................................................................................10-2
Table 10.2 SerDes Broadcast Test Mode Operation Transmit Delay Operation..............................10-4
Table 11.1 JTAG Pin Descriptions....................................................................................................11-2
Table 11.2 Boundary Scan Chain.....................................................................................................11-3
Table 11.3 Instructions Supported by PES12N3’s JTAG Boundary Scan........................................11-6

IDT List of Tables
PES12N3 User Manual vi June 7, 2006
Notes Table 11.4 System Controller Device Identification Register............................................................11-8

Notes
PES12N3 User Manual vii June 7, 2006
List of Figures
Figure 1.1 PES12N3 Functional Block Diagram ................................................................................1-2
Figure 1.2 PES12N3 Architectural Block Diagram .............................................................................1-3
Figure 1.3 PES12N3 Logic Diagram ..................................................................................................1-6
Figure 2.1 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ...................2-6
Figure 3.1 Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[1:0]=0x2) .......................3-2
Figure 3.2 Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[1:0]=0x1) .......................3-2
Figure 4.1 PES12N3 Switch Data Flow and Buffering .......................................................................4-1
Figure 5.1 PES12N3 Power Management State Transition Diagram ................................................5-1
Figure 5.2 PES12N3 ASPM Link Sate Transitions ............................................................................5-3
Figure 6.1 Hot-Plug on Switch Downstream Slots Application ........................................................... 6-1
Figure 6.2 Hot-Plug with Switch on Add-In Card Application .............................................................6-2
Figure 6.3 Hot-Plug with Carrier Card Application .............................................................................6-2
Figure 7.1 SMBus Interface Configuration Examples ........................................................................7-1
Figure 7.2 Single Double Word Initialization Sequence Format .........................................................7-6
Figure 7.3 Sequential Double Word Initialization Sequence Format ..................................................7-6
Figure 7.4 Configuration Done Sequence Format ............................................................................. 7-7
Figure 7.5 Slave SMBus Command Code Format .............................................................................7-9
Figure 7.6 CSR Register Read or Write CMD Field Format .............................................................7-11
Figure 7.7 Serial EEPROM Read or Write CMD Field Format .........................................................7-12
Figure 7.8 CSR Register Read Using SMBus Block Write/Read Transactions
with PEC Disabled ..........................................................................................................7-13
Figure 7.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions
with PEC Disabled ..........................................................................................................7-14
Figure 7.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ..........7-14
Figure 7.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled .......7-14
Figure 7.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled .......7-14
Figure 7.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ...7-15
Figure 9.1 PES12N3 Functional Block Diagram in Transparent Mode ..............................................9-1
Figure 9.2 Port Configuration Space Organization ............................................................................9-7
Figure 10.1 10-bit Loopback Test Mode ............................................................................................10-1
Figure 10.2 Internal Pseudo Random Bit Stream Self-Test ...............................................................10-2
Figure 10.3 External Pseudo Random Bit Stream Self-Test ..............................................................10-3
Figure 11.1 Diagram of the JTAG Logic .............................................................................................11-1
Figure 11.2 State Diagram of PES12N3’s TAP Controller .................................................................11-2
Figure 11.3 Diagram of Observe-only Input Cell ................................................................................11-4
Figure 11.4 Diagram of Output Cell ...................................................................................................11-5
Figure 11.5 Diagram of Output Enable Cell .......................................................................................11-5
Figure 11.6 Diagram of Bidirectional Cell ...........................................................................................11-6
Figure 11.7 Device ID Register Format ..............................................................................................11-8

IDT List of Figures
PES12N3 User Manual viii June 7, 2006
Notes

Notes
PES12N3 User Manual ix June 7, 2006
Register List
BAR0 - Base Address Register 0 (0x010)................................................................................................9-20
BAR1 - Base Address Register 1 (0x014)................................................................................................9-20
BCTRL - Bridge Control (0x03E)..............................................................................................................9-26
BIST - Built-in Self Test (0x00F)...............................................................................................................9-20
CAPPTR - Capabilities Pointer (0x034) ...................................................................................................9-25
CCODE - Class Code (0x009) .................................................................................................................9-19
CLS - Cache Line Size (0x00C)...............................................................................................................9-20
DID - Device Identification (0x002)...........................................................................................................9-17
ECFGADDR - Extended Configuration Space Access Address (0x0F8).................................................9-49
ECFGDATA - Extended Configuration Space Access Data (0x0FC).......................................................9-50
EEPROMINTF - Serial EEPROM Interface (0x0B4)................................................................................9-47
EROMBASE - Expansion ROM Base Address (0x038)...........................................................................9-25
GPIOCS - General Purpose I/O Control and Status (0x0A8)...................................................................9-45
HDR - Header Type Register (0x00E)......................................................................................................9-20
INTRLINE - Interrupt Line (0x03C)...........................................................................................................9-25
INTRPIN - Interrupt PIN (0x03D)..............................................................................................................9-25
INTSTS - Interrupt Status (0x0F4) ...........................................................................................................9-49
IOBASE - I/O Base (0x01C).....................................................................................................................9-21
IOBASEU - I/O Base Upper (0x030)........................................................................................................9-24
IOEXPINTF - I/O Expander Interface (0x0B8) .........................................................................................9-48
IOLIMIT - I/O Limit (0x01D)......................................................................................................................9-22
IOLIMITU - I/O Limit Upper (0x032).........................................................................................................9-25
MBASE - Memory Base (0x020)..............................................................................................................9-23
MLIMIT - Memory Limit (0x022)...............................................................................................................9-23
MSIADDR - Message Signaled Interrupt Address (0x080)......................................................................9-39
MSICAP - Message Signaled Interrupt Capability and Control (0x07C)..................................................9-39
MSIMDATA - Message Signaled Interrupt Message Data (0x088)..........................................................9-40
MSIUADDR - Message Signaled Interrupt Upper Address (0x084).........................................................9-40
PA_PCIECAP - PCI Express Capability (0x040)......................................................................................9-10
PB_PCIECAP - PCI Express Capability (0x040)......................................................................................9-13
PBUSN - Primary Bus Number (0x018)...................................................................................................9-21
PC_PCIECAP - PCI Express Capability (0x040)......................................................................................9-16
PCICMD - PCI Command (0x004)...........................................................................................................9-17
PCIECAP - PCI Express Capability (0x040).............................................................................................9-26
PCIEDCAP - PCI Express Device Capabilities (0x044)...........................................................................9-27
PCIEDCTL - PCI Express Device Control (0x048)...................................................................................9-28
PCIEDSTS - PCI Express Device Status (0x04A)....................................................................................9-29
PCIELCAP - PCI Express Link Capabilities (0x04C)................................................................................9-30
PCIELCTL - PCI Express Link Control (0x050)........................................................................................9-30
PCIELSTS - PCI Express Link Status (0x052).........................................................................................9-31
PCIESCAP - PCI Express Slot Capabilities (0x054)................................................................................9-32
PCIESCTL - PCI Express Slot Control (0x058)........................................................................................9-33
PCIESSTS - PCI Express Slot Status (0x05A) ........................................................................................9-35
PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100)..............................9-50
PCISTS - PCI Status (0x006)...................................................................................................................9-18
PLTIMER - Primary Latency Timer (0x00D).............................................................................................9-20
PMBASE - Prefetchable Memory Base (0x024).......................................................................................9-23
PMBASEU - Prefetchable Memory Base Upper (0x028).........................................................................9-24
PMCAP - PCI Power Management Capabilities (0x070)..........................................................................9-36

IDT Register List
PES12N3 User Manual x June 7, 2006
Notes PMCSR - PCI Power Management Control and Status (0x074)..............................................................9-36
PMLIMIT - Prefetchable Memory Limit (0x026)........................................................................................9-24
PMLIMITU - Prefetchable Memory Limit Upper (0x02C)..........................................................................9-24
PMPC - PCI Power Management Proprietary Control (0x078)................................................................9-37
PVCCAP1- Port VC Capability 1 (0x104).................................................................................................9-50
RID - Revision Identification (0x008)........................................................................................................9-19
SBUSN - Secondary Bus Number (0x019) ..............................................................................................9-21
SECSTS - Secondary Status (0x01E)......................................................................................................9-22
SLTIMER - Secondary Latency Timer (0x01B)........................................................................................9-21
SMBUSCTL - SMBus Control (0x0B0).....................................................................................................9-46
SMBUSSTS - SMBus Status (0x0AC) .....................................................................................................9-45
SUBUSN - Subordinate Bus Number (0x01A).........................................................................................9-21
SWCTL - Switch Control (0x0A4).............................................................................................................9-42
SWSICTL - Switch System Integrity Control (0x500)...............................................................................9-60
SWSIPECNT - Switch System Integrity Parity Error Count (0x504) ........................................................9-61
SWSITDCNT - Switch System Integrity Time-Out Drop Count (0x508)...................................................9-61
SWSTS Switch Status (0x0A0)................................................................................................................9-40
TMCNT0 - Test Mode Count 0 (0x0CC)...................................................................................................9-59
TMCNT1 - Test Mode Count 1 (0x0D0)...................................................................................................9-59
TMCNT2 - Test Mode Count 2 (0x0D4)...................................................................................................9-60
TMCNTCFG - Test Mode Count Configuration (0x0C8)..........................................................................9-57
TMCTL - Test Mode Control (0x0BC) ......................................................................................................9-55
TMFSTS - Test Mode Fail Status (0x0C0)...............................................................................................9-56
TMSSTS - Test Mode Synchronization Status (0x0C4)...........................................................................9-56
VCR0CAP- VC Resource 0 Capability (0x110)........................................................................................9-51
VCR0CTL- VC Resource 0 Control (0x114).............................................................................................9-51
VCR0STS - VC Resource 0 Status (0x118).............................................................................................9-52
VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120)...............................................................9-53
VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124)...............................................................9-54
VID - Vendor Identification (0x000)..........................................................................................................9-17

Notes
PES12N3 User Manual 1 - 1 June 7, 2006
Chapter 1
PES12N3 Device Overview
Introduction
The 89HPES12N3 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions
offering the next-generation I/O interconnect standard. The PES12N3 is a 12 lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized for high performance applications
such as servers, storage, and communications/networking. It provides high-performance I/O connectivity
and switching functions between a PCI Express upstream port and two downstream ports or peer-to-peer
switching between downstream ports.
Utilizing standard PCI Express interconnect, the PES12N3 provides the most efficient high-performance
I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 6 GBps (48 Gbps) of aggregate switching capacity
through 12 integrated seriallanes, using proven and robust IDT technology. Each lane provides 2.5Gbps of
bandwidth in both directions. The PES12N3 is fully compliant with PCI Express Base specification 1.0a.
The PES12N3 is based on a flexible and efficient layered architecture. The PCI Express layer consists
of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES12N3 can operate either as a store and forward or cut-through switch and is
designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management. This includes system selectable algorithms such
as round robin and weighted round-robin schemes guaranteeing bandwidth allocation and/or latency for
critical traffic classes in applications such as high throughput 10 Gigabit I/Os, streaming media for graphics,
TV tuners, and cameras.
Figure 1.1 provides a functional block diagram while Figure 1.2 illustrates the architecture of the device.

IDT PES12N3 Device Overview Introduction
PES12N3 User Manual 1 - 2 June 7, 2006
Notes
Figure 1.1 PES12N3 Functional Block Diagram
As shown in Figure 1.1, port A is configured as the upstream port and ports Band C as the downstream
ports. Port B resides on the internal PCI Bus at Device 0, Function 0. Port C resides on the internal PCI Bus
at Device 1, Function 0.
Type 1
Configuration Header
PCI-PCI
Transparent
Bridge
Type 1
Configuration Header
PCI-PCI
Transparent Bridge
(Device 1)
Virtual PCI Bus
Port A
(Upstream Port)
Port B
(Downstream Port) Port C (Downstream Port)
Type 1
Configuration Header
PCI-PCI
Transparent Bridge
(Device 0)

IDT PES12N3 Device Overview Features
PES12N3 User Manual 1 - 3 June 7, 2006
Notes
Figure 1.2 PES12N3 Architectural Block Diagram
Features
High Performance PCI Express Switch
– Three x4 ports with 12 PCI Express lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 2048 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin or weighted round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and queueing
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/decoder (no separate transceivers
needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internalend-to-endparityprotectiononall TLPs ensuresdataintegrityeven insystems thatdo not
implement end-to-end CRC (ECRC)
Transaction
Layer
Data Link
Layer
Physical
Layer MAC/PCS
PT NP CP
3-Port Switch Core
Port B
Downstream Port
GPIO
Controller
Hot-Plug
Controller
Master
SMBus
Interface
Slave
SMBus
Interface
Input FrameBuffer Route
Map
Table
PT NP CP
Input FrameBuffer Route
Map
Table
Egress
Scheduler Port Arbiter Egress Scheduler Port Arbiter Egress Scheduler Port Arbiter
Retry
SerDes
Buffer
Transaction
Layer
Data Link
Layer
Physical
Layer MAC/PCS
Retry
SerDes
Buffer
Transaction
Layer
Data Link
Layer
Physical
Layer MAC/PCS
Retry
SerDes
Buffer
PT NP CP
Input FrameBuffer Route
Map
Table
Port A
Upstream Port
Port C
DownstreamPorrt

IDT PES12N3 Device Overview System Identification
PES12N3 User Manual 1 - 4 June 7, 2006
Notes – Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC motherboards
– Supports Hot-Swap
Power Management
– Supports PCI Express Power Management Interface specification, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI)
supporting active link state
Testability and Debug Features
– Supports IEEE 1149.6 JTAG
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Two SMBus Interfaces
– Slave interface provides full access to all software-visible registers by an external SMBus master
– Master interface provides connection for an optional serial EEPROM used for initialization
– Master interface is also used by an external Hot-Plug
I/O expander
– Master and slave interfaces may be tied together so the PES12N3 can act as both master and
slave
8 General Purpose Input/Output pins
Packaged in 19x19mm 324 ball BCG with 1mm ball spacing
System Identification
Vendor ID
All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech-
nology, Inc.
Device ID
The device IDs for the PES12N3 are shown in Table 1.1.
PCI Device Offset
Device ID
Transparent bridge associ-
ated with Ports A, B, and C 0x8018
Table 1.1 PES12N3 Offset Device IDs