IDT 89HPES48T12G2 User manual

®
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©2013 Integrated Device Technology, Inc.
IDT®89HPES48T12G2
PCI Express®Switch
User Manual
April 2013

GENERAL DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
CODE DISCLAIMER
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at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
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IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
PES48T12G2 User Manual 1 April 5, 2013
®
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES48T12G2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES48T12G2 Device Overview,” provides a complete introduction to the performance
capabilities of the 89HPES48T12G2. Included in this chapter is a summary of features for the device as well
as a system block diagram and pin description.
Chapter 2, “Architectural Overview,” provides a high level architectural overview of the PES48T12G2
device.
Chapter 3, “Switch Core,” provides a description of the PES48T12G2 switch core.
Chapter 4, “Clocking,” provides a description of the PES48T12G2 clocking architecture.
Chapter 5, “Reset and Initialization,” describes the PES48T12G2 reset operations and initialization
procedure.
Chapter 6, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 7, “SerDes,” describes basic functionality and controllability associated with the Serialiazer-
Deserializer (SerDes) block in PES48T12G2 ports.
Chapter 7, “Theory of Operation,” describes the general operational behavior of the PES48T12G2.
Chapter 9, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in
the PES48T12G2.
Chapter 10, “Power Management,” describes the power management capability structure located in
the configuration space of each PCI-to-PCI bridge in the PES48T12G2.
Chapter 11, “General Purpose I/O,” describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 12, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the
PES48T12G2.
Chapter 13, “Multicast,” describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.
Chapter 14, “Register Organization,” describes the organization of all the software visible registers in
the PES48T12G2 and provides the address space for those registers.
Chapter 15, “PCI to PCI Bridge and Proprietary Port Specific Registers,” lists the Type 1 configura-
tion header registers in the PES48T12G2 and provides a description of each bit in those registers.
Chapter 16, “Switch Control and Status Registers,” lists the switch control and status registers in the
PES48T12G2 and provides a description of each bit in those registers.

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Notes
Chapter 17, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
Ter m Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
1234
high-to-low
transition low-to-high
transition
single clock cycle

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PES48T12G2 User Manual 3 April 5, 2013
Notes
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
Table 2 Register Terminology (Sheet 1 of 2)
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

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PES48T12G2 User Manual 4 April 5, 2013
Notes
Use of Hypertext
In Chapter 14, Tables 14.4, 14.5 and 14.6 contain register names and page numbers highlighted in blue
under the Register Definition column. In pdf files, users can jump from this source table directly to the regis-
ters by clicking on the register name in the source table. Each register name in the table is linked directly to
the appropriate register in the register section of Chapters and 16. To return to the source table after having
jumped to the register section, click on the same register name (in blue) in the register section.
Reference Documents
[1] PCI Express Base Specification Revision 2.0., December 20, 2006, PCI-SIG.
[2] Multicast Engineering Change Notice to [1]., May 8, 2008, PCI-SIG.
[3] Internal Error Reporting Engineering Change Notice to [1]., April 24, 2008, PCI-SIG.
[4] SMBus Specification, Version 2.0, August 3, 2000, SBS Implementers Forum.
Revision History
November 5, 2008: Initial publication of preliminary user manual.
January 12, 2009: On page 3-6, added last sentence to Port Arbitration section on page 3-6. In Table
8.10, under Description for Function in D3Hot state, changed reference to 10-1 instead of 9-1.
January 22, 2009: In Chapter 12, Table 12.15, changed the description for bit USA. In Chapter 15,
PCIEDCTL register, changed the description for bit ERO.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Read and Write RW Software can both read and write bits with this attribute.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked
RWL Software can read the register/bits with this attribute. Writing to
register/bits with this attribute will only cause the value to be modi-
fied if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis-
ter/bits are effectively read-only.
Fields with this attribute are implicitly SWSticky (i.e., their value is
preserved across all resets, except switch fundamental reset).
Sticky Sticky Register/bits with this designation take on their initial value as a
result of a switch fundamental reset or fundamental reset. Other
resets have no effect.
Switch Sticky SWSticky Register/bits with this designation take on their initial value as a
result of a switch fundamental reset. Other resets have no effect.
Type Abbreviation Description
Table 2 Register Terminology (Sheet 2 of 2)

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PES48T12G2 User Manual 5 April 5, 2013
Notes
February 9, 2009: In Chapter 1: Table 1.4, for Port 0 Serial Data Receive/Transmit signals, deleted
statement that port 0 is the upstream port; Table 1.8, revised Description for SWMODE[3:0]; Table 1.10,
added “3.3V is preferred” for signal VDDI/O. In Chapter 6, deleted footnote in 2nd paragraph under section
Software Management of Link Speed.
February 18, 2009: In Chapter 6, added a note under L2/L3 Ready in Link States section. In Chapter
15, modified Description for REG and EREG fields in the ECFGADDR register, GADDR field in the
GASAADDR register, DATA field in the GASADATA register, and RSE field in the SECSTS register. In
Chapters 14 and 15, added PHYLSTATE0 (0x540) register.
March 18, 2009: In Table 12.11, the address value was changed from zero to 1 for bits 3 and 5.
April 9, 2009: Changes made in register fields in Chapters 15 and 16 (Bridge and Switch Registers), to
conform with device specification and validation.
April 21, 2009: In Table 1.8, deleted reference to pull-down value of 251K ohm resistor for all
PxMERGEN pins. In Footnote 1 for Table 1.11, internal resistor pull-down value was changed to 91K ohms.
In Chapter 16, changed “Bit x in this field corresponds to GPIO pin (x+31)” to “Bit x in this field corresponds
to GPIO pin (x+32)” in the GPIOFUNC1, GPIOCFG1, and GPIOD1 registers. Changed title for Table 12.11.
April 27, 2009: ZB silicon was added to Table 1.3.
May 6, 2009: In Chapter 5, under section Switch Fundamental Reset, deleted bullet referencing
SWFRST bit.
May 14, 2009: In Table 1.11, changed CML to HCSL for PCIe reference clocks.
May 28, 2009: In Chapter 6, revised Crosslink section. In Chapter 7, Tables 7.2, 7.3 and 7.4, changed
column title of TX_EQ_MODE to reflect the register field used to control TX equalization depending on the
operating mode of the link (e.g., TX_EQ_3DBG1). In Chapter 12, revised Introduction section and deleted
references to LAERR bit in Table 12.2, Table 12.15, and Figure 12.8. In Chapter 14, added section Partial-
Byte Access to Word and DWord Registers. In Chapter 16, added bit BDISCARD to the Switch Control
register and changed bit 26 in the SMBus Status register from LAERR to Reserved.
June 16, 2009: In Chapters 5 and 6, added footnote explaining LTSSM reference. In Chapter 16,
removed reference to RDETECT bit in Hot-Plug Configuration Control register.
June 22, 2009: In Table 1.11, System Pins section, changed GCLKFSEL to pull-down.
July 30, 2009: In Chapter 16, Switch Registers, changed bits 19:18 in the SMBus Control register from
SSMBMODE to Reserved.
August 17, 2009: In Chapter 16, Switch Registers, revised the description for the RXEQZ and RXEQB
fields in the SerDes x Receiver Equalization Lane Control register.
September 22, 2009: Modified Chapter 4, Clocking. In Chapter 7, SerDes, modified Table 7.2 and
added Note before Figure 7.1. Modified section Transaction Layer Error Pollution in Chapter 9, Theory of
Operation. In Chapter 16, Switch Registers, modified description of the LANESEL field in the SxCTL
register and modified description of the RXEQZ and RXEQB fields in the SxRXEQLCTL register.
September 28, 2009: ZC silicon was added to Table 1.3.
November 6, 2009: In Chapter 3, Switch Core, modified text and figures in Operation section. In
Chapter 4, Clocking, modified Introduction section. In Chapter 14, Register Organization, added new
section Register Side-Effects. In Chapter 15, Bridge Registers, modified description for DVADJ bit in the
Requester Metering Control register.
November 11, 2009: In Chapter 7, SerDes, deleted settings greater than 0x0F in Tables 7.7 and 7.8.
December 7, 2009: In Chapter 6, added reference in section Link width Negotiation to the MAXLNK-
WDTH field in the PCI Express Link Capabilities register. In Chapter 14, added new sub-section Limitations
under Register Side-Effects. In Chapter 15, modified Description for the MAXLNKWDTH field in the
PCIELCAP register and added field RCVD_OVRD to the SerDes Configuration register. In Chapter 16,
added field DDDNC to the Switch Control register and modified Description for the BLANK field in the
SMBus Status register.

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PES48T12G2 User Manual 6 April 5, 2013
Notes
December 14, 2009: Deleted all references to support for Weighted Round Robin arbitration.
January 21, 2010: Removed Preliminary from title.
February 10, 2010: In Chapter 5, added new Port Merging section. In Table 1.8, added reference to Port
Merging section in PxxMERGEN pin description.
March 31, 2010: In Chapter 14, Table 14.6, added the following register names and cross-references for
ports 8, 9, 12, 13: SWPORTxCTL, SWPORTxSTS, SxCTL, SxTXLCTL0, SxTXLCTL1, SxRXEQLCTL.
December 8, 2010: In Chapter 13, corrected ports specified for I/O Expander 10 in Table 12.3. In
Chapter 17, deleted PERSTN, GLK1, and SMODE from Table 17.1.
February 2, 2011: In Table 8.13, revised text in Action Taken column for ACS Source Validation. In
Chapter 15, added footnote to STAS bit in PCISTS and SECSTS registers.
May 18, 2011: In Chapter 7, section Low-Swing Transmitter Voltage Mode, the reference in the first
paragraph to the LSE bit being in the SerDes Control register was changed to the SerDes Configuration
register.
June 28, 2011: In Chapter 16, added bit 26, TX_SLEW_C, to the SerDes x Transmitter Lane Control 0
register.
July 8, 2011: In Chapter 15, removed table footnotes from PCISTS and SECSTS registers, added
Reserved bits 31:24 to AERUEM and AERUESV registers, and added last sentence to each description in
the PCIESCTLIV register. In Chapter 16, added FEN and FCAPSEL fields to SWPART[x]CTL register and
SWPORT[x]CTL registers, added PFAILOVER and SFAILOVER fields to SWPART[X]STS register and
SWPORT[x]STS register, adjusted bit fields in GPIOCFG1 and GPIOD1 registers.
August 31, 2011: In Chapter 2, page 2-1, added bullet to explain behavior of an odd numbered port
when it is merged with its even counterpart. In Chapter 6, revised text in section Link Width Negotiation in
the Presence of Bad Lanes. In Chapter 7, revised Table 7.1 and text under this table, revised text in section
Programmable De-emphasis Adjustment, added headings to Figures 7.1 through 7.3, and added paragraph
after Figure 7.3. In Chapter 13, revised text in the Introduction section. In Chapter 15, changed type of
MAXLNKSPD field in the PCIELCAP register from RWL to RO, revised Description for MAXGROUP field in
MCCAP register, changed lower to upper in Description for MCBLKALLH and MCBLKUTH registers. In
Chapter 17, deleted references to Failover capability from several registers.
September 9, 2011: In Chapter 7, added additional reference in last paragraph of section Driver Voltage
Level and Amplitude Boost.
February 7, 2012: In Chapter 12, added footnote for RERR and WERR bits in Table 12.13.
February 23, 2012: Added paragraph after Table 12.13 to explain use of DWord addresses.
January 31, 2013: In Figure 12.8, changed No-ack to Ack between DATALM and DATAUM.
April 5, 2013: In Chapter 16, added USSBRDELAY register.

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PES48T12G2 User Manual i April 5, 2013
Table of Contents
®
About This Manual
Introduction ....................................................................................................................................1
Content Summary ..........................................................................................................................1
Signal Nomenclature .....................................................................................................................2
Numeric Representations ..............................................................................................................2
Data Units ......................................................................................................................................2
Register Terminology ..................................................................................................................... 3
Use of Hypertext ............................................................................................................................4
Reference Documents ................................................................................................................... 4
Revision History .............................................................................................................................4
PES48T12G2 Device Overview
Introduction .....................................................................................................................................1-1
Features..........................................................................................................................................1-1
Logic Diagram.................................................................................................................................1-5
System Identification.......................................................................................................................1-6
Vendor ID................................................................................................................................1-6
Device ID ................................................................................................................................1-6
Revision ID .............................................................................................................................1-6
JTAG ID..................................................................................................................................1-6
SSID/SSVID............................................................................................................................1-6
Device Serial Number Enhanced Capability...........................................................................1-6
Pin Description................................................................................................................................1-7
Pin Characteristics........................................................................................................................1-13
Architectural Overview
Introduction .....................................................................................................................................2-1
Logical View....................................................................................................................................2-2
Switch Core
Introduction .....................................................................................................................................3-1
Switch Core Architecture ................................................................................................................3-1
Ingress Buffer .........................................................................................................................3-1
Egress Buffer..........................................................................................................................3-2
Crossbar Interconnect ............................................................................................................3-3
Datapaths ...............................................................................................................................3-3
Packet Ordering..............................................................................................................................3-3
Arbitration........................................................................................................................................3-4
Port Arbitration........................................................................................................................3-5
Cut-Through Routing ......................................................................................................................3-5
Request Metering............................................................................................................................3-7
Operation................................................................................................................................3-9
Completion Size Estimation..................................................................................................3-11
Internal Errors ...............................................................................................................................3-12
Switch Time-Outs .................................................................................................................3-13
Memory SECDED ECC Protection.......................................................................................3-13
End-to-End Data Path Parity Protection ...............................................................................3-13

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PES48T12G2 User Manual ii April 5, 2013
Notes
Clocking
Introduction ..................................................................................................................................... 4-1
Port Clocking Mode ........................................................................................................................ 4-1
Reset and Initialization
Introduction ..................................................................................................................................... 5-1
Boot Configuration Vector............................................................................................................... 5-1
Switch Fundamental Reset............................................................................................................. 5-2
Hot Resets ...................................................................................................................................... 5-5
Hot Reset................................................................................................................................ 5-5
Upstream Secondary Bus Reset ............................................................................................5-5
Downstream Secondary Bus Reset........................................................................................5-6
Port Merging ................................................................................................................................... 5-6
Link Operation
Introduction ..................................................................................................................................... 6-1
Polarity Inversion ............................................................................................................................ 6-1
Lane Reversal................................................................................................................................. 6-1
Link Width Negotiation.................................................................................................................... 6-5
Link Width Negotiation in the Presence of Bad Lanes ...........................................................6-6
Dynamic Link Width Reconfiguration..............................................................................................6-6
Link Speed Negotiation................................................................................................................... 6-6
Link Speed Negotiation in the PES48T12G2 .........................................................................6-7
Software Management of Link Speed ....................................................................................6-9
Link Retraining.............................................................................................................................. 6-10
Link Down ..................................................................................................................................... 6-10
Slot Power Limit Support ..............................................................................................................6-11
Upstream Port ...................................................................................................................... 6-11
Downstream Port.................................................................................................................. 6-11
Link States .................................................................................................................................... 6-11
Active State Power Management .................................................................................................6-12
L0s ASPM............................................................................................................................. 6-12
L1 ASPM .............................................................................................................................. 6-13
L1 ASPM Entry Rejection Timer ...................................................................................................6-14
Link Status .................................................................................................................................... 6-14
De-emphasis Negotiation ............................................................................................................. 6-15
Crosslink ....................................................................................................................................... 6-15
Hot Reset Operation on a Crosslink .................................................................................... 6-16
Link Disable Operation on a Crosslink .................................................................................6-16
Gen1 Compatibility Mode ............................................................................................................. 6-16
SerDes
Introduction ..................................................................................................................................... 7-1
SerDes Numbering and Port Association .......................................................................................7-1
SerDes Transmitter Controls .......................................................................................................... 7-1
Driver Voltage Level and Amplitude Boost ............................................................................. 7-1
De-emphasis ..........................................................................................................................7-2
Slew Rate ............................................................................................................................... 7-2
PCI Express Low-Swing Mode ............................................................................................... 7-2
Receiver Equalization ..................................................................................................................... 7-3
Programming of SerDes Controls................................................................................................... 7-3
Programmable Voltage Margining and De-Emphasis.....................................................................7-3

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PES48T12G2 User Manual iii April 5, 2013
Notes
SerDes Transmitter Control Registers....................................................................................7-4
Transmit Margining using the PCI Express Link Control 2 Register............................................. 7-12
Low-Swing Transmitter Voltage Mode..........................................................................................7-13
Receiver Equalization Controls..................................................................................................... 7-14
SerDes Power Management.........................................................................................................7-15
Theory of Operation
Introduction ..................................................................................................................................... 8-1
Transaction Routing........................................................................................................................ 8-1
Interrupts......................................................................................................................................... 8-1
Downstream Port Interrupts....................................................................................................8-2
Legacy Interrupt Emulation..................................................................................................... 8-2
Access Control Services................................................................................................................. 8-3
Error Detection and Handling ......................................................................................................... 8-6
Physical Layer Errors ............................................................................................................. 8-7
Data Link Layer Errors............................................................................................................ 8-7
Transaction Layer Errors ........................................................................................................8-8
Routing Errors ...................................................................................................................... 8-16
Bus Locking .................................................................................................................................. 8-17
Hot-Plug and Hot-Swap
Introduction ..................................................................................................................................... 9-1
Hot-Plug Signals ............................................................................................................................. 9-3
Port Reset Outputs .........................................................................................................................9-4
Power Enable Controlled Reset Output.................................................................................. 9-5
Power Good Controlled Reset Output .................................................................................... 9-5
Hot-Plug Events.............................................................................................................................. 9-6
Legacy System Hot-Plug Support................................................................................................... 9-6
Hot-Swap ........................................................................................................................................ 9-8
Power Management
Introduction ................................................................................................................................... 10-1
PME Messages............................................................................................................................. 10-3
PCI Express Power Management Fence Protocol .......................................................................10-3
Upstream Switch Port or Downstream Switch Port Mode ....................................................10-3
Power Budgeting Capability.......................................................................................................... 10-4
General Purpose I/O
Introduction ................................................................................................................................... 11-1
GPIO Configuration ...................................................................................................................... 11-1
Configured as an Input ......................................................................................................... 11-1
Configured as an Output ......................................................................................................11-1
Configured as an Alternate Function .................................................................................... 11-1
SMBus Interfaces
Introduction ................................................................................................................................... 12-1
Master SMBus Interface ............................................................................................................... 12-1
Initialization........................................................................................................................... 12-1
Serial EEPROM.................................................................................................................... 12-1
Initialization from Serial EEPROM........................................................................................ 12-2
Programming the Serial EEPROM .......................................................................................12-5

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PES48T12G2 User Manual iv April 5, 2013
Notes
I/O Expanders.......................................................................................................................12-5
Slave SMBus Interface ............................................................................................................... 12-13
Initialization......................................................................................................................... 12-13
SMBus Transactions .......................................................................................................... 12-13
Multicast
Introduction ................................................................................................................................... 13-1
Addressing and Routing ............................................................................................................... 13-1
Multicast TLP Determination ................................................................................................13-1
Multicast TLP Routing .......................................................................................................... 13-4
Multicast Egress Processing ................................................................................................13-4
Register Organization
Introduction ................................................................................................................................... 14-1
Partial-Byte Access to Word and DWord Registers .............................................................14-2
Register Side-Effects............................................................................................................ 14-2
Address Maps............................................................................................................................... 14-2
PCI-to-PCI Bridge Registers.................................................................................................14-2
Capability Structures ............................................................................................................ 14-3
IDT Proprietary Port Specific Registers.............................................................................. 14-10
Switch Configuration and Status Registers ........................................................................14-12
PCI to PCI Bridge and Proprietary Port Specific Registers
Type 1 Configuration Header Registers .......................................................................................15-1
PCI Express Capability Structure ...............................................................................................15-11
Power Management Capability Structure ...................................................................................15-27
Message Signaled Interrupt Capability Structure .......................................................................15-29
Subsystem ID and Subsystem Vendor ID ..................................................................................15-31
Extended Configuration Space Access Registers ......................................................................15-31
Advanced Error Reporting (AER) Enhanced Capability..............................................................15-32
Device Serial Number Enhanced Capability............................................................................... 15-41
PCI Express Virtual Channel Capability ..................................................................................... 15-42
Power Budgeting Enhanced Capability ......................................................................................15-47
ACS Extended Capability ........................................................................................................... 15-49
Multicast Extended Capability..................................................................................................... 15-52
Proprietary Port Specific Registers............................................................................................. 15-56
Port Control and Status Registers ...................................................................................... 15-56
Internal Error Control and Status Registers........................................................................ 15-58
Physical Layer Control and Status Registers .....................................................................15-65
Power Management Control and Status Registers ............................................................15-68
Request Metering ...............................................................................................................15-69
Global Address Space Access Registers ........................................................................... 15-70
Switch Configuration and Status Registers
Switch Control and Status Registers ............................................................................................16-1
Internal Switch Timer .................................................................................................................... 16-3
Switch Port Registers ................................................................................................................... 16-3
SerDes Control and Status Registers...........................................................................................16-4
General Purpose I/O Registers................................................................................................... 16-12
Hot-Plug and SMBus Interface Registers ...................................................................................16-15

IDT Table of Contents
PES48T12G2 User Manual v April 5, 2013
Notes
JTAG Boundary Scan
Introduction ................................................................................................................................... 17-1
Test Access Point ......................................................................................................................... 17-1
Signal Definitions .......................................................................................................................... 17-1
Boundary Scan Chain................................................................................................................... 17-2
Test Data Register (DR) ............................................................................................................... 17-5
Boundary Scan Registers.....................................................................................................17-5
Instruction Register (IR)................................................................................................................ 17-7
EXTEST................................................................................................................................ 17-8
SAMPLE/PRELOAD............................................................................................................. 17-8
BYPASS ............................................................................................................................... 17-8
CLAMP ................................................................................................................................. 17-9
IDCODE................................................................................................................................ 17-9
VALIDATE ............................................................................................................................ 17-9
EXTEST_TRAIN................................................................................................................... 17-9
EXTEST_PULSE................................................................................................................ 17-10
RESERVED........................................................................................................................ 17-10
Usage Considerations ........................................................................................................ 17-10

IDT Table of Contents
PES48T12G2 User Manual vi April 5, 2013
Notes

Notes
PES48T12G2 User Manual vii April 5, 2013
List of Tables
®
Table 1.1 Initial Configuration Register Settings for PES48T12G2 .....................................................1-3
Table 1.2 PES48T12G2 Device IDs ....................................................................................................1-6
Table 1.3 PES48T12G2 Revision ID ...................................................................................................1-6
Table 1.4 PCI Express Interface Pins..................................................................................................1-7
Table 1.5 Reference Clock Pins ..........................................................................................................1-8
Table 1.6 SMBus Interface Pins ..........................................................................................................1-8
Table 1.7 General Purpose I/O Pins....................................................................................................1-9
Table 1.8 System Pins.........................................................................................................................1-9
Table 1.9 Test Pins............................................................................................................................1-11
Table 1.10 Power, Ground, and SerDes Resistor Pins .......................................................................1-12
Table 1.11 Pin Characteristics.............................................................................................................1-13
Table 3.1 IFB Buffer Sizes...................................................................................................................3-1
Table 3.2 EFB Buffer Sizes ................................................................................................................3-2
Table 3.3 Replay Buffer Storage Limit.................................................................................................3-3
Table 3.4 Packet Ordering Rules in the PES48T12G2........................................................................3-4
Table 3.5 Conditions for Cut-Through Transfers .................................................................................3-6
Table 3.6 Request Metering Decrement Value..................................................................................3-10
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State............................................4-2
Table 5.1 PES48T12G2 Reset Precedence........................................................................................5-1
Table 5.2 Boot Configuration Vector Signals.......................................................................................5-2
Table 6.1 Crosslink Port Groups........................................................................................................6-15
Table 6.2 Gen1 Compatibility Mode: bits cleared in training sets......................................................6-17
Table 7.1 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers............7-5
Table 7.2 SerDes Transmit Driver Settings in Gen1 Mode..................................................................7-6
Table 7.3 SerDes Transmit Driver Settings in Gen2 Mode with -3.5dB de-emphasis.........................7-7
Table 7.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis.........................7-8
Table 7.5 Transmitter Slew Rate Settings .........................................................................................7-11
Table 7.6 PCI Express Transmit Margining Levels supported by the PES48T12G2......................... 7-12
Table 7.7 SerDes Transmit Drive Swing in Low Swing Mode at Gen1 Speed .................................. 7-13
Table 7.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed ..................................7-14
Table 8.1 Switch Routing Methods......................................................................................................8-1
Table 8.2 Downstream Port Interrupts.................................................................................................8-2
Table 8.3 Downstream to Upstream Port Interrupt Routing Based on Device Number.......................8-3
Table 8.4 Prioritization of ACS Checks for Request TLPs...................................................................8-5
Table 8.5 Prioritization of ACS Checks for Completion TLPs..............................................................8-6
Table 8.6 TLP Types Affected by ACS Checks...................................................................................8-6
Table 8.7 Physical Layer Errors...........................................................................................................8-7
Table 8.8 Data Link Layer Errors.........................................................................................................8-7
Table 8.9 Transaction Layer Errors associated with the PCI-to-PCI Bridge Function.........................8-9
Table 8.10 Conditions handled as Unsupported Requests (UR) by the PCI-to-PCI Bridge Function .8-11
Table 8.11 Ingress TLP Formation Checks Associated with the PCI-to-PCI Bridge Function.............8-11
Table 8.12 Egress Malformed TLP Error Checks................................................................................8-12
Table 8.13 ACS Violations for Ports Operating in Downstream Switch Port Mode ............................. 8-13
Table 8.14 Prioritization of Transaction Layer Errors ..........................................................................8-14
Table 9.1 Port Hot Plug Signals...........................................................................................................9-3
Table 9.2 Negated Value of Unused Hot-Plug Output Signals............................................................ 9-3
Table 10.1 PES48T12G2 Power Management State Transition Diagram...........................................10-2
Table 11.1 GPIO Pin Configuration .....................................................................................................11-1
Table 11.2 General Purpose I/O Pin Alternate Function .....................................................................11-2

IDT List of Tables
PES48T12G2 User Manual viii April 5, 2013
Notes
Table 11.3 GPIO Alternate Function Pins ........................................................................................... 11-2
Table 12.1 PES48T12G2 Compatible Serial EEPROMs..................................................................... 12-2
Table 12.2 Serial EEPROM Initialization Errors ..................................................................................12-5
Table 12.3 I/O Expander Function Allocation ...................................................................................... 12-6
Table 12.4 I/O Expander Default Output Signal Value ........................................................................ 12-7
Table 12.5 Pin Mapping for I/O Expanders 0 through 7 ......................................................................12-9
Table 12.6 Pin Mapping I/O Expander 8 ...........................................................................................12-10
Table 12.7 Pin Mapping I/O Expander 9 ...........................................................................................12-10
Table 12.8 Pin Mapping I/O Expander 10 .........................................................................................12-11
Table 12.9 I/O Expander 12 - Link Up Status....................................................................................12-12
Table 12.10 I/O Expander 13 - Link Activity Status ............................................................................. 12-12
Table 12.11 Slave SMBus Address..................................................................................................... 12-13
Table 12.12 Slave SMBus Command Code Fields ............................................................................. 12-14
Table 12.13 CSR Register Read or Write Operation Byte Sequence .................................................12-15
Table 12.14 CSR Register Read or Write CMD Field Description.......................................................12-16
Table 12.15 Serial EEPROM Read or Write Operation Byte Sequence .............................................12-16
Table 12.16 Serial EEPROM Read or Write CMD Field Description...................................................12-17
Table 14.1 Global Address Space Organization .................................................................................14-1
Table 14.2 Default PCI Capability List Linkage ................................................................................... 14-3
Table 14.3 Default PCI Express Capability List Linkage .....................................................................14-4
Table 14.4 PCI-to-PCI Bridge Configuration Space Registers ............................................................ 14-6
Table 14.5 Proprietary Port Specific Registers..................................................................................14-11
Table 14.6 Switch Configuration and Status .....................................................................................14-13
Table 17.1 JTAG Pin Descriptions ...................................................................................................... 17-2
Table 17.2 Boundary Scan Chain........................................................................................................ 17-3
Table 17.3 Instructions Supported by the JTAG Boundary Scan ........................................................17-8
Table 17.4 System Controller Device Identification Register ..............................................................17-9

Notes
PES48T12G2 User Manual ix April 5, 2013
List of Figures
®
Figure 1.1 PES48T12G2 Block Diagram ............................................................................................1-3
Figure 1.2 PES48T12G2 Logic Diagram .............................................................................................1-5
Figure 2.1 Transparent PCIe Switch ...................................................................................................2-2
Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers .................................................3-3
Figure 3.2 Architectural Model of Arbitration .......................................................................................3-5
Figure 3.3 PCIe Switch Static Rate Mismatch ....................................................................................3-8
Figure 3.4 PCIe Switch Static Rate Mismatch ....................................................................................3-8
Figure 3.5 Request Metering Count and Initial Value Loaded ............................................................3-9
Figure 3.6 Decrement Value and Decrement Value Adjustment .......................................................3-10
Figure 3.7 Request Metering Counter Decrement Operation ............................................................3-11
Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation ...............................3-11
Figure 4.1 Logical Representation of the PES48T12G2 Clocking Architecture ..................................4-1
Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................5-4
Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................5-4
Figure 6.1 Unmerged Port Lane Reversal for Maximum Link Width of x4 ..........................................6-2
Figure 6.2 Unmerged Port Lane Reversal for Maximum Link Width of x2 ..........................................6-2
Figure 6.3 Merged Port Lane Reversal for Maximum Link Width of x2 ...............................................6-3
Figure 6.4 Merged Port Lane Reversal for Maximum Link Width of x4 ...............................................6-4
Figure 6.5 Merged Port Lane Reversal for Maximum Link Width of x8 ...............................................6-5
Figure 6.6 PES48T12G2 ASPM Link Sate Transitions .....................................................................6-12
Figure 7.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................7-10
Figure 7.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................7-10
Figure 7.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB
Nominal de-emphasis ......................................................................................................7-11
Figure 8.1 ACS Source Validation Example .......................................................................................8-4
Figure 8.2 ACS Peer-to-Peer Request Re-direct at a Downstream Port ............................................8-4
Figure 8.3 ACS Upstream Forwarding Example .................................................................................8-5
Figure 8.4 Error Checking and Logging on a Received TLP .............................................................8-15
Figure 9.1 Hot-Plug on Switch Downstream Slots Application ............................................................9-1
Figure 9.2 Hot-Plug with Switch on Add-In Card Application ..............................................................9-2
Figure 9.3 Hot-Plug with Carrier Card Application ..............................................................................9-2
Figure 9.4 Power Enable Controlled Reset Output Mode Operation ..................................................9-5
Figure 9.5 Power Good Controlled Reset Output Mode Operation .....................................................9-5
Figure 9.6 PES48T12G2 Hot-Plug Event Signalling ...........................................................................9-7
Figure 10.1 PES48T12G2 Power Management State Transition Diagram .........................................10-2
Figure 12.1 Split SMBus Interface Configuration ................................................................................12-1
Figure 12.2 Single Double Word Initialization Sequence Format ........................................................12-3
Figure 12.3 Sequential Double Word Initialization Sequence Format .................................................12-3
Figure 12.4 Configuration Done Sequence Format ............................................................................12-4
Figure 12.5 Slave SMBus Command Code Format ..........................................................................12-14
Figure 12.6 CSR Register Read or Write CMD Field Format ............................................................12-15
Figure 12.7 Serial EEPROM Read or Write CMD Field Format ........................................................12-17
Figure 12.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled 12-18

IDT List of Figures
PES48T12G2 User Manual x April 5, 2013
Notes
Figure 12.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled .........................................................................................................................12-18
Figure 12.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled .........12-18
Figure 12.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled .....12-19
Figure 12.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ......12-19
Figure 12.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ..12-19
Figure 13.1 Multicast Group Address Ranges ....................................................................................13-2
Figure 13.2 Multicast Group Address Region Determination ..............................................................13-3
Figure 14.1 PCI-to-PCI Bridge Configuration Space Organization .....................................................14-5
Figure 14.2 Proprietary Port Specific Register Organization ............................................................14-10
Figure 14.3 Switch Configuration and Status Space Organization ...................................................14-12
Figure 17.1 Diagram of the JTAG Logic ..............................................................................................17-1
Figure 17.2 State Diagram of the TAP Controller ...............................................................................17-2
Figure 17.3 Diagram of Observe-only Input Cell .................................................................................17-6
Figure 17.4 Diagram of Output Cell ....................................................................................................17-6
Figure 17.5 Diagram of Bidirectional Cell ............................................................................................17-7
Figure 17.6 Device ID Register Format ...............................................................................................17-9

Notes
PES48T12G2 User Manual xi April 5, 2013
Register List
®
ACSCAP - ACS Capability Register (0x324)........................................................................................ 15-49
ACSCTL - ACS Control Register (0x326)............................................................................................. 15-50
ACSECAPH - ACS Extended Capability Header (0x320) .................................................................... 15-49
ACSECV - ACS Egress Control Vector (0x328)................................................................................... 15-51
AERCAP - AER Capabilities (0x100) ................................................................................................... 15-32
AERCEM - AER Correctable Error Mask (0x114) ................................................................................ 15-38
AERCES - AER Correctable Error Status (0x110) ............................................................................... 15-37
AERCTL - AER Control (0x118)........................................................................................................... 15-40
AERHL1DW - AER Header Log 1st Doubleword (0x11C) ................................................................... 15-40
AERHL2DW - AER Header Log 2nd Doubleword (0x120)................................................................... 15-40
AERHL3DW - AER Header Log 3rd Doubleword (0x124).................................................................... 15-40
AERHL4DW - AER Header Log 4th Doubleword (0x128).................................................................... 15-41
AERUEM - AER Uncorrectable Error Mask (0x108) ............................................................................ 15-34
AERUES - AER Uncorrectable Error Status (0x104) ........................................................................... 15-32
AERUESV - AER Uncorrectable Error Severity (0x10C)...................................................................... 15-36
BAR0 - Base Address Register 0 (0x010).............................................................................................. 15-4
BAR1 - Base Address Register 1 (0x014).............................................................................................. 15-4
BCTL - Bridge Control Register (0x03E) .............................................................................................. 15-10
BCVSTS - Boot Configuration Vector Status (0x0004) .......................................................................... 16-2
BIST - Built-in Self Test Register (0x00F) .............................................................................................. 15-4
CAPPTR - Capabilities Pointer Register (0x034) ................................................................................... 15-9
CCODE - Class Code Register (0x009) ................................................................................................. 15-3
CLS - Cache Line Size Register (0x00C)............................................................................................... 15-4
DID - Device Identification Register (0x002) .......................................................................................... 15-1
ECFGADDR - Extended Configuration Space Access Address (0x0F8) ............................................. 15-31
ECFGDATA - Extended Configuration Space Access Data (0x0FC)................................................... 15-32
EEPROMINTF - Serial EEPROM Interface (0x0AD0).......................................................................... 16-19
EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 15-9
GASAADDR - Global Address Space Access Address (0xFF8).......................................................... 15-70
GASADATA - Global Address Space Access Data (0xFFC)................................................................ 15-70
GPECTL - General Purpose Event Control (0x0AE8).......................................................................... 16-21
GPESTS - General Purpose Event Status (0x0AEC) .......................................................................... 16-22
GPIOAFSEL0 - General Purpose I/O Alternate Function Select 0 (0x0A98) ....................................... 16-13
GPIOCFG0 - General Purpose I/O Configuration 0 (0x0AA8) ............................................................. 16-14
GPIOCFG1 - General Purpose I/O Configuration 1 (0x0AAC)............................................................. 16-14
GPIOD0 - General Purpose I/O Data 0 (0x0AB0) ................................................................................ 16-14
GPIOD1 - General Purpose I/O Data 1 (0x0AB4) ................................................................................ 16-15
GPIOFUNC0 - General Purpose I/O Function 0 (0x0A90)................................................................... 16-12
GPIOFUNC1 - General Purpose I/O Function 1 (0x0A94)................................................................... 16-13
HDR - Header Type Register (0x00E).................................................................................................... 15-4
HPCFGCTL - Hot-Plug Configuration Control (0x0ABC) ..................................................................... 16-16
HPSIGMAP - Hot-Plug GPIO Signal Map (0x0AB8) ............................................................................ 16-15
IERRORCTL - Internal Error Reporting Control (0x480) ...................................................................... 15-58
IERRORMSK - Internal Error Reporting Mask (0x488) ........................................................................ 15-59
IERRORSEV - Internal Error Reporting Severity (0x48C).................................................................... 15-61
IERRORSTS - Internal Error Reporting Status (0x484) ....................................................................... 15-58
IERRORTST - Internal Error Reporting Test (0x490)........................................................................... 15-64
INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 15-9
INTRPIN - Interrupt PIN Register (0x03D) ............................................................................................. 15-9

IDT Register List
PES48T12G2 User Manual xii April 5, 2013
Notes
IOBASE - I/O Base Register (0x01C)......................................................................................................15-5
IOBASEU - I/O Base Upper Register (0x030).........................................................................................15-8
IOEXPADDR0 - SMBus I/O Expander Address 0 (0x0AD8).................................................................16-20
IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) ................................................................16-20
IOEXPADDR2 - SMBus I/O Expander Address 2 (0x0AE0) .................................................................16-21
IOEXPADDR3 - SMBus I/O Expander Address 3 (0x0AE4) .................................................................16-21
IOLIMIT - I/O Limit Register (0x01D).......................................................................................................15-6
IOLIMITU - I/O Limit Upper Register (0x032)..........................................................................................15-8
L1ASPMRTC - L1 ASPM Rejection Timer Control (0x710) ..................................................................15-68
LANESTS0 - Lane Status 0 (0x51C).....................................................................................................15-66
LANESTS1 - Lane Status 1 (0x520) .....................................................................................................15-66
MBASE - Memory Base Register (0x020)...............................................................................................15-7
MCBARH- Multicast Base Address High (0x33C).................................................................................15-53
MCBARL- Multicast Base Address Low (0x338)...................................................................................15-53
MCBLKALLH- Multicast Block All High (0x34C)....................................................................................15-54
MCBLKALLL- Multicast Block All Low (0x348)......................................................................................15-54
MCBLKUTH - Multicast Block Untranslated High (0x354) ....................................................................15-55
MCBLKUTL- Multicast Block Untranslated Low (0x350).......................................................................15-55
MCCAP - Multicast Capability (0x334)..................................................................................................15-52
MCCAPH - Multicast Enhanced Capability Header (0x330) .................................................................15-52
MCCTL- Multicast Control (0x336)........................................................................................................15-52
MCOVRBARH- Multicast Overlay Base Address High (0x35C)............................................................15-55
MCOVRBARL- Multicast Overlay Base Address Low (0x358)..............................................................15-55
MCRCVH- Multicast Receive High (0x344)...........................................................................................15-54
MCRCVL- Multicast Receive Low (0x340) ............................................................................................15-53
MLIMIT - Memory Limit Register (0x022)................................................................................................15-7
MSIADDR - Message Signaled Interrupt Address (0x0D4)...................................................................15-30
MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) ...............................................15-29
MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)......................................................15-30
MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) .....................................................15-30
PBUSN - Primary Bus Number Register (0x018)....................................................................................15-5
PCICMD - PCI Command Register (0x004)............................................................................................15-1
PCIECAP - PCI Express Capability (0x040) .........................................................................................15-11
PCIEDCAP - PCI Express Device Capabilities (0x044) ........................................................................15-11
PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ...................................................................15-24
PCIEDCTL - PCI Express Device Control (0x048)................................................................................15-13
PCIEDCTL2 - PCI Express Device Control 2 (0x068)...........................................................................15-24
PCIEDSTS - PCI Express Device Status (0x04A) ................................................................................15-14
PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ...........................................................................15-24
PCIELCAP - PCI Express Link Capabilities (0x04C) ............................................................................15-14
PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .......................................................................15-24
PCIELCTL - PCI Express Link Control (0x050).....................................................................................15-16
PCIELCTL2 - PCI Express Link Control 2 (0x070)................................................................................15-25
PCIELSTS - PCI Express Link Status (0x052)......................................................................................15-17
PCIELSTS2 - PCI Express Link Status 2 (0x072).................................................................................15-27
PCIESCAP - PCI Express Slot Capabilities (0x054) .............................................................................15-19
PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) ........................................................................15-27
PCIESCTL - PCI Express Slot Control (0x058).....................................................................................15-20
PCIESCTL2 - PCI Express Slot Control 2 (0x078)................................................................................15-27
PCIESCTLIV - PCI Express Slot Control Initial Value (0x420)..............................................................15-56
PCIESSTS - PCI Express Slot Status (0x05A) .....................................................................................15-22
PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ................................................................................15-27
PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) ..............................................15-42
PCISTS - PCI Status Register (0x006) ...................................................................................................15-2
PHYLCFG0 - Phy Link Configuration 0 (0x530)....................................................................................15-67