IDT 89HPES5T5 User manual

®
January 2011
6024 Silver Creek Valley Road, San Jose, California 95138
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Printed in U.S.A.
©2011 Integrated Device Technology, Inc.
IDT™89HPES5T5
PCI Express® Switch
Preliminary User Manual

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Notes
PES5T5 User Manual 1 January 28, 2011
®
About this Manual
Introduction
This user manual includes hardware and software information on the 89HPES5T5, a member of IDT’s
PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan-
dard.
Finding Additional Information
Informationnot included inthis manualsuchas mechanicals,package pin-outs, andelectrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES5T5 Device Overview,” provides a complete introduction to the performance capabili-
ties of the 89HPES5T5. Included in this chapter is a summary of features for the device as well as a system
block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Theory of Operation,” describes the operation of the link feature including polarity inver-
sion, link width negotiation, and lane reversal.
Chapter 4, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 5, “General Purpose I/O,” describes how the 16 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES5T5.
Chapter 7, “Power Management,” describes the power management capabilitystructure located in the
configuration space of each PCI-PCI bridge in the PES5T5.
Chapter 8, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in
the PES5T5.
Chapter 9, “Configuration Registers,” discusses the base addresses, PCI configuration space, and
registers associated with the PES5T5.
Chapter 10, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether thatlevel is represented by a high or lowvoltage. The term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

IDT
PES5T5 User Manual 2 January 28, 2011
Notes To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edgeindicates a low-to-high(0 to1) transition. Falling edge indicates a high-to-low (1 to0)transition. These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x:y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD if x < y or to
ABCxD, ABC(x-1)D, ABC(x-2)D,... ABCyD if x > y.
Data Units
The following data unit terminology is used in this document.
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word.
Term Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
1 2 3 4
high-to-low
transition low-to-high
transition
single clock cycle

IDT
PES5T5 User Manual 3 January 28, 2011
Notes
Table 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Note: Software in the context of this register terminology refers to modifications made by PCIe
rootconfiguration writes toregisters made throughthe slave SMBusinterface,or serial EEPROM
register initialization.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mecha-
nisms such as pin strapping or serial EEPROM. (System firm-
ware hardware initialization is only allowed for system
integrateddevices.)Bitsareread-onlyafterinitializationandcan
only be reset (for write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading
the value will automatically cause the register/bit to be reset to
zero. Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading
the value will automatically cause the register/bits to be reset to
zero. Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular
value. On writes, software must ensure that the values of
reserved bit positions are preserved. That is, the values of
reserved bit positions must first be read, merged with the new
values for other bit positions and then written back.
Read Only RO Software can only read registers/bits with this attribute. Con-
tents are hardwired to a constant value or are status bits that
may be set and cleared by hardware. Writing to a RO location
has no effect.
Read and Write RW Software can both read and write bits with this attribute.
Table 3 Register Terminology (Sheet 1 of 2)
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

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PES5T5 User Manual 4 January 28, 2011
Notes
Use of Hypertext
In Chapter 9, Tables 9.2 and 9.3 contain register names and page numbers highlighted inblue under the
Register Definition column. In pdf files, users can jump from this source table directly to the registers by
clicking on the register name in the source table. Each register name in the table is linked directly to the
appropriate register in the register section of the chapter. To return to the source table after having jumped
to the register section, click on the same register name (in blue) in the register section.
Reference Documents
PCI Express Base Specification, Revision 1.1, PCI Special Interest Group.
PCI Power Management Interface Specification, Revision 1.2, PCI Special Interest Group.
PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.
SMBus Specification, Revision 2.0.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However,writing avalueof zerotoa bitwiththis attributehas no
effect. A RW1C bit canonlybe settoavalueof 1by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a
value of one must be written to the location. An RW1C bit is
never cleared by hardware.
Read and Write when
Unlocked RWL Software can read the register/bits with this attribute. Writing to register/bits with this attribute will only cause the value to be
modified if the REGUNLOCK bit in the SWCNTL register is set.
When the REGUNLOCK bit is cleared, writes are ignored and
the register/bits are effectively read-only.
These registers are Sticky as they are preserved across a hot
reset. These bits are not preserved during fundamental reset.
Read Only Sticky ROS Registers are read-only and cannot be altered by software. Reg-
isters are not initialized or modified by hot reset.
When device consumes AUX power, some of these bits main-
tain their value across fundamental reset and are marked
FRSticky.
Read and Write Sticky RWS Registers are read-write and may be either set or cleared by
software to the desired state. Bits are not initialized or modified
by hot reset.
When device consumes AUX power, some of these bits main-
tain their value across fundamental reset and are marked
FRSticky.
Read Write-1-to-Clear
Sticky RWICS Registers indicate status when read, a set bit indicating a status event may be cleared by writing a 1. Writing a 0 to RW1CS bits
has no effect. Bits are not initialized or modified by hot reset.
When device consumes AUX power, some of these bits main-
tain their value across fundamental reset and are marked
FRSticky.
Write Transient WT The zero is always read from a bit/field of this type. Writing of a
one is used to qualify the writing of other bits/fields in the same
register.
Zero Zero A zero register or bit must be written with a value of zero and
returns a value of zero when read.
Type Abbreviation Description
Table 3 Register Terminology (Sheet 2 of 2)

IDT
PES5T5 User Manual 5 January 28, 2011
Notes Revision History
June 5, 2007: Initial Publication.
July 11, 2007: Corrected AERUCS to AERUES in AERCTL register, Chapter 8.
July 16, 2007: Made numerous minor edits throughout manual.
January 23, 2008: In Table 9.2, changed pins PE0RN/RP/TN/TP to read [0] instead of [1:0].
September 24, 2009: In Chapter 3, change made to L2 description in Link States section. Made
numerous changes in Chapter 6, Power. In Chapter 8, Registers, modified description of the LDIS bit in the
PCI Express Link Control register and changed bit field for CTLPTOC in the Switch Time-Out Count register to
[24:16].
November 10, 2009: Added a new Chapter 3 called Theory of Operations.
January 28, 2011: ZB silicon added to Table 1.9, Revision ID.

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PES5T5 User Manual 6 January 28, 2011
Notes

Notes
PES5T5 User Manual i January 28, 2011
Table of Contents
®
PES5T5 Device Overview
Introduction.....................................................................................................................................1-1
List of Features...............................................................................................................................1-1
System Diagrams............................................................................................................................1-3
Logic Diagram.................................................................................................................................1-4
SSID/SSVID............................................................................................................................1-4
Device Serial Number Enhanced Capability...........................................................................1-5
Pin Description................................................................................................................................1-5
Pin Characteristics..........................................................................................................................1-9
System Identification.....................................................................................................................1-10
Vendor ID..............................................................................................................................1-10
Device ID..............................................................................................................................1-10
Revision ID...........................................................................................................................1-10
JTAG ID................................................................................................................................1-11
Port Configuration.........................................................................................................................1-11
Clocking, Reset, and Initialization
Introduction.....................................................................................................................................2-1
Initialization.....................................................................................................................................2-3
Reset...............................................................................................................................................2-5
Fundamental Reset................................................................................................................2-5
Hot Reset................................................................................................................................2-7
Upstream Secondary Bus Reset............................................................................................2-8
Downstream Secondary Bus Reset........................................................................................2-8
Downstream Port Reset Outputs....................................................................................................2-9
Power Enable Controlled Reset Output..................................................................................2-9
Power Good Controlled Reset Output..................................................................................2-10
Hot Reset Controlled Reset Output......................................................................................2-10
Theory of Operation
Port Interrupts.................................................................................................................................3-1
Legacy Interrupt Emulation.............................................................................................................3-1
Link Operation
Introduction.....................................................................................................................................4-1
Polarity Inversion............................................................................................................................4-1
Link Width Negotiation....................................................................................................................4-1
Link Retraining................................................................................................................................4-1
Link Down.......................................................................................................................................4-1
Slot Power Limit Support................................................................................................................4-2
Upstream Port.........................................................................................................................4-2
Downstream Port....................................................................................................................4-2
Link States......................................................................................................................................4-2
Active State Power Management....................................................................................................4-3
Link Status......................................................................................................................................4-4

IDT Table of Contents
PES5T5 User Manual ii January 28, 2011
Notes General Purpose Inputs/Outputs
Introduction.....................................................................................................................................5-1
GPIO Configuration ........................................................................................................................5-1
GPIO Pin Configured as an Input...........................................................................................5-2
GPIO Pin Configured as an Output........................................................................................5-2
GPIO Pin Configured as an Alternate Function......................................................................5-2
SMBus Interfaces
Introduction.....................................................................................................................................6-1
Master SMBus Interface.................................................................................................................6-2
Initialization.............................................................................................................................6-2
Serial EEPROM......................................................................................................................6-2
I/O Expanders.........................................................................................................................6-6
Slave SMBus Interface.................................................................................................................6-12
Initialization...........................................................................................................................6-12
SMBus Transactions ............................................................................................................6-12
Power Management
Introduction.....................................................................................................................................7-1
PME Messages...............................................................................................................................7-2
Power Express Power Management Fence Protocol.....................................................................7-3
Power Budgeting Capability............................................................................................................7-3
Wakeup Protocol ............................................................................................................................7-4
WAKEN Signal as an Input.....................................................................................................7-5
WAKEN Signal as an Output..................................................................................................7-5
WAKEN and Beacon Disabled...............................................................................................7-5
Auxiliary Power Implementation .....................................................................................................7-5
Switch System States.............................................................................................................7-5
Auxiliary Power Control ..................................................................................................................7-6
PES5T5 Auxiliary Power Usage............................................................................................7-8
Hot-Plug and Hot-Swap
Introduction.....................................................................................................................................8-1
Hot-Plug I/O Expander ...........................................................................................................8-4
Hot-Plug Interrupts and Wake-up...........................................................................................8-4
Legacy System Hot-Plug Support ..........................................................................................8-4
Hot-Swap........................................................................................................................................8-6
Configuration Registers
Configuration Space Organization..................................................................................................9-1
Upstream Port (Port 0) ...........................................................................................................9-3
Downstream Ports (Ports 2 through 5)...................................................................................9-7
Register Definitions.......................................................................................................................9-11
Type 1 Configuration Header Registers...............................................................................9-11
PCI Express Capability Structure.........................................................................................9-21
Power Management Capability Structure.............................................................................9-32
Message Signaled Interrupt Capability Structure.................................................................9-34
Subsystem ID and Subsystem Vendor ID............................................................................9-35
Extended Configuration Space Access Registers................................................................9-36
Advanced Error Reporting (AER) Enhanced Capability.......................................................9-37
Device Serial Number Enhanced Capability.........................................................................9-43
PCI Express Virtual Channel Capability...............................................................................9-43

IDT Table of Contents
PES5T5 User Manual iii January 28, 2011
Notes Power Budgeting Enhanced Capability................................................................................9-49
Switch Control and Status Registers....................................................................................9-51
Internal Switch Error Control and Status Registers..............................................................9-61
Wakeup Protocol Registers..................................................................................................9-64
JTAG Boundary Scan
Introduction...................................................................................................................................10-1
Test Access Point.........................................................................................................................10-1
Signal Definitions..........................................................................................................................10-1
Boundary Scan Chain...................................................................................................................10-3
Test Data Register (DR)...............................................................................................................10-4
Boundary Scan Registers.....................................................................................................10-4
Instruction Register (IR)................................................................................................................10-6
EXTEST................................................................................................................................10-7
SAMPLE/PRELOAD.............................................................................................................10-7
BYPASS...............................................................................................................................10-7
CLAMP.................................................................................................................................10-8
IDCODE................................................................................................................................10-8
VALIDATE............................................................................................................................10-8
RESERVED..........................................................................................................................10-8
Usage Considerations..........................................................................................................10-9

IDT Table of Contents
PES5T5 User Manual iv January 28, 2011
Notes

Notes
PES5T5 User Manual v January 28, 2011
List of Tables
®
Table 1.1 PCI Express Interface Pins..................................................................................................1-5
Table 1.2 SMBus Interface Pins..........................................................................................................1-6
Table 1.3 General Purpose I/O Pins....................................................................................................1-6
Table 1.4 System Pins.........................................................................................................................1-7
Table 1.5 Test Pins..............................................................................................................................1-8
Table 1.6 Power and Ground Pins.......................................................................................................1-8
Table 1.7 Pin Characteristics...............................................................................................................1-9
Table 1.8 PES5T5 Device ID.............................................................................................................1-10
Table 1.9 PES5T5 Revision ID..........................................................................................................1-10
Table 2.1 Reference Clock Mode Encoding........................................................................................2-1
Table 2.2 Boot Configuration Vector Signals.......................................................................................2-4
Table 3.1 Downstream Port Interrupts.................................................................................................3-1
Table 3.2 PES5T5 Downstream to Upstream Port Interrupt Routing..................................................3-2
Table 5.1 General Purpose I/O Pin Alternate Function.......................................................................5-1
Table 5.2 GPIO Pin Configuration.......................................................................................................5-1
Table 6.1 Serial EEPROM SMBus Address........................................................................................6-2
Table 6.2 PES5T5 Compatible Serial EEPROMs................................................................................6-3
Table 6.3 Serial EEPROM Initialization Errors....................................................................................6-5
Table 6.4 I/O Expander Function Allocation........................................................................................6-6
Table 6.5 I/O Expander Default Output Signal Value..........................................................................6-7
Table 6.6 I/O Expander 0 Signals........................................................................................................6-9
Table 6.7 I/O Expander 1 Signals......................................................................................................6-10
Table 6.8 I/O Expander 2 Signals......................................................................................................6-10
Table 6.9 I/O Expander 4 Signals......................................................................................................6-11
Table 6.10 Slave SMBus Address When a Static Address is Selected...............................................6-12
Table 6.11 Slave SMBus Command Code Fields ...............................................................................6-13
Table 6.12 CSR Register Read or Write Operation Byte Sequence...................................................6-13
Table 6.13 CSR Register Read or Write CMD Field Description.........................................................6-14
Table 6.14 Serial EEPROM Read or Write Operation Byte Sequence................................................6-15
Table 6.15 Serial EEPROM Read or Write CMD Field Description.....................................................6-16
Table 7.1 PES5T5 Power Management State Transition Diagram.....................................................7-2
Table 7.2 Auxiliary Power Enabled (Beacon OFF)..............................................................................7-9
Table 7.3 Auxiliary Power Enabled (SerDes OFF, only WAKEN Enabled).........................................7-9
Table 9.1 Base Addresses for Port Configuration Space Registers....................................................9-1
Table 9.2 Upstream Port 0 Configuration Space Registers.................................................................9-3
Table 9.3 Downstream Ports 2 through 5 Configuration Space Registers..........................................9-7
Table 10.1 JTAG Pin Descriptions.......................................................................................................10-2
Table 10.2 Boundary Scan Chain........................................................................................................10-3
Table 10.3 Instructions Supported by PES5T5’s JTAG Boundary Scan.............................................10-7
Table 10.4 System Controller Device Identification Register...............................................................10-8

IDT List of Tables
PES5T5 User Manual vi January 28, 2011
Notes

Notes
PES5T5 User Manual vii January 28, 2011
List of Figures
®
Figure 1.1 PES5T5 Architectural Block Diagram ................................................................................1-3
Figure 1.2 PES5T5 Logic Diagram .....................................................................................................1-4
Figure 1.3 PES5T5 Port Configuration ..............................................................................................1-11
Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread
Spectrum Clock) ................................................................................................................2-1
Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................2-2
Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................2-2
Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread
Spectrum Clock) ................................................................................................................2-3
Figure 2.5 Fundamental Reset with Serial EEPROM initialization ......................................................2-7
Figure 2.6 Power Enable Controlled Reset Output Mode Operation ..................................................2-9
Figure 2.7 Power Good Controlled Reset Output Mode Operation ...................................................2-10
Figure 4.1 PES5T5 ASPM Link Sate Transitions ................................................................................4-3
Figure 6.1 SMBus Interface Configuration Examples .........................................................................6-1
Figure 6.2 Single Double Word Initialization Sequence Format ..........................................................6-3
Figure 6.3 Sequential Double Word Initialization Sequence Format ...................................................6-4
Figure 6.4 Configuration Done Sequence Format ..............................................................................6-4
Figure 6.5 Slave SMBus Command Code Format ............................................................................6-12
Figure 6.6 CSR Register Read or Write CMD Field Format ..............................................................6-14
Figure 6.7 Serial EEPROM Read or Write CMD Field Format ..........................................................6-15
Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-16
Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-17
Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........6-17
Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........6-17
Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........6-17
Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....6-18
Figure 7.1 PES5T5 Power Management State Transition Diagram ....................................................7-1
Figure 7.2 PES5T5 System States .....................................................................................................7-5
Figure 7.3 L2 Mode Enable/Disable and FRSticky Bit Initialization .....................................................7-7
Figure 7.4 Vaux Usage Model .............................................................................................................7-8
Figure 7.5 Conceptual Diagram of the PES5T5 Auxiliary Power Connection ...................................7-10
Figure 8.1 Hot-Plug on Switch Downstream Slots Application ............................................................8-1
Figure 8.2 Hot-Plug with Switch on Add-In Card Application ..............................................................8-2
Figure 8.3 Hot-Plug with Carrier Card Application ..............................................................................8-2
Figure 8.4 PES5T5 Hot-Plug Event Signalling ....................................................................................8-5
Figure 9.1 Port Configuration Space Organization .............................................................................9-2
Figure 10.1 Diagram of the JTAG Logic ..............................................................................................10-1
Figure 10.2 State Diagram of PES5T5’s TAP Controller .....................................................................10-2
Figure 10.3 Diagram of Observe-only Input Cell .................................................................................10-5
Figure 10.4 Diagram of Output Cell ....................................................................................................10-5
Figure 10.5 Diagram of Bidirectional Cell ............................................................................................10-6
Figure 10.6 Device ID Register Format ...............................................................................................10-8

IDT List of Figures
PES5T5 User Manual viii January 28, 2011
Notes

Notes
PES5T5 User Manual ix January 28, 2011
Register List
®
AERCAP - AER Capabilities (0x100)..................................................................................................... 9-37
AERCEM - AER Correctable Error Mask (0x114).................................................................................. 9-41
AERCES - AER Correctable Error Status (0x110)................................................................................. 9-40
AERCTL - AER Control (0x118)............................................................................................................. 9-41
AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..................................................................... 9-42
AERHL2DW - AER Header Log 2nd Doubleword (0x120)..................................................................... 9-42
AERHL3DW - AER Header Log 3rd Doubleword (0x124)...................................................................... 9-42
AERHL4DW - AER Header Log 4th Doubleword (0x128)...................................................................... 9-42
AERUEM - AER Uncorrectable Error Mask (0x108).............................................................................. 9-38
AERUES - AER Uncorrectable Error Status (0x104)............................................................................. 9-37
AERUESV - AER Uncorrectable Error Severity (0x10C)........................................................................ 9-39
BAR0 - Base Address Register 0 (0x010).............................................................................................. 9-14
BAR1 - Base Address Register 1 (0x014).............................................................................................. 9-14
BCTL - Bridge Control Register (0x03E)................................................................................................ 9-19
BIST - Built-in Self Test Register (0x00F).............................................................................................. 9-14
CAPPTR - Capabilities Pointer Register (0x034)................................................................................... 9-19
CCODE - Class Code Register (0x009)................................................................................................. 9-13
CLS - Cache Line Size Register (0x00C)............................................................................................... 9-14
DID - Device Identification Register (0x002).......................................................................................... 9-11
ECFGADDR - Extended Configuration Space Access Address (0x0F8)............................................... 9-36
ECFGDATA - Extended Configuration Space Access Data (0x0FC)..................................................... 9-36
EEPROMINTF - Serial EEPROM Interface (0x34C).............................................................................. 9-57
EROMBASE - Expansion ROM Base Address Register (0x038)........................................................... 9-19
GPECTL - General Purpose Event Control (0x35C).............................................................................. 9-60
GPESTS - General Purpose Event Status (0x360)................................................................................ 9-61
GPIOCFG - General Purpose I/O Configuration (0x33C)....................................................................... 9-55
GPIOD - General Purpose I/O Data (0x340).......................................................................................... 9-55
GPIOFUNC - General Purpose I/O Control Function (0x338)................................................................ 9-55
GPR - General Purpose Register (0x334).............................................................................................. 9-54
HDR - Header Type Register (0x00E).................................................................................................... 9-14
HPCFGCTL - Hot-Plug Configuration Control (0x330)........................................................................... 9-53
INTRLINE - Interrupt Line Register (0x03C)........................................................................................... 9-19
INTRPIN - Interrupt PIN Register (0x03D)............................................................................................. 9-19
IOBASE - I/O Base Register (0x01C)..................................................................................................... 9-15
IOBASEU - I/O Base Upper Register (0x030)........................................................................................ 9-18
IOEXPADDR0 - SMBus I/O Expander Address 0 (0x354)..................................................................... 9-59
IOEXPADDR1 - SMBus I/O Expander Address 1 (0x358)..................................................................... 9-60
IOEXPINTF - I/O Expander Interface (0x350)........................................................................................ 9-58
IOLIMIT - I/O Limit Register (0x01D)...................................................................................................... 9-16
IOLIMITU - I/O Limit Upper Register (0x032)......................................................................................... 9-18
MBASE - Memory Base Register (0x020).............................................................................................. 9-16
MLIMIT - Memory Limit Register (0x022)............................................................................................... 9-17
MSIADDR - Message Signaled Interrupt Address (0x0D4).................................................................... 9-34
MSICAP - Message Signaled Interrupt Capability and Control (0x0D0)................................................ 9-34
MSIMDATA - Message Signaled Interrupt Message Data (0x0DC)....................................................... 9-35
MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8)...................................................... 9-35
PBUSN - Primary Bus Number Register (0x018)................................................................................... 9-15
PCICMD - PCI Command Register (0x004)...........................................................................................9-11
PCIECAP - PCI Express Capability (0x040)........................................................................................... 9-21

IDT Register List
PES5T5 User Manual x January 28, 2011
Notes PCIEDCAP - PCI Express Device Capabilities (0x044)..........................................................................9-21
PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064).....................................................................9-31
PCIEDCTL - PCI Express Device Control (0x048)..................................................................................9-22
PCIEDCTL2 - PCI Express Device Control 2 (0x068).............................................................................9-31
PCIEDSTS - PCI Express Device Status (0x04A) ..................................................................................9-23
PCIEDSTS2 - PCI Express Device Status 2 (0x06A) .............................................................................9-31
PCIELCAP - PCI Express Link Capabilities (0x04C) ..............................................................................9-24
PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) .........................................................................9-31
PCIELCTL - PCI Express Link Control (0x050).......................................................................................9-25
PCIELCTL2 - PCI Express Link Control 2 (0x070)..................................................................................9-31
PCIELSTS - PCI Express Link Status (0x052)........................................................................................9-26
PCIELSTS2 - PCI Express Link Status 2 (0x072)...................................................................................9-32
PCIESCAP - PCI Express Slot Capabilities (0x054)...............................................................................9-27
PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074)..........................................................................9-32
PCIESCTL - PCI Express Slot Control (0x058).......................................................................................9-28
PCIESCTL2 - PCI Express Slot Control 2 (0x078)..................................................................................9-32
PCIESSTS - PCI Express Slot Status (0x05A) .......................................................................................9-30
PCIESSTS2 - PCI Express Slot Status 2 (0x07A) ..................................................................................9-32
PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200)................................................9-43
PCISTS - PCI Status Register (0x006) ...................................................................................................9-12
PLTIMER - Primary Latency Timer (0x00D)............................................................................................9-14
PMBASE - Prefetchable Memory Base Register (0x024).......................................................................9-17
PMBASEU - Prefetchable Memory Base Upper Register (0x028)..........................................................9-18
PMCAP - PCI Power Management Capabilities (0x0C0)........................................................................9-32
PMCSR - PCI Power Management Control and Status (0x0C4) ............................................................9-33
PMLIMIT - Prefetchable Memory Limit Register (0x026)........................................................................9-17
PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)..........................................................9-18
PVCCAP1- Port VC Capability 1 (0x204)................................................................................................9-43
PVCCAP2- Port VC Capability 2 (0x208)................................................................................................9-44
PVCCTL - Port VC Control (0x20C)........................................................................................................9-45
PVCSTS - Port VC Status (0x20E) .........................................................................................................9-45
PWRBCAP - Power Budgeting Capabilities (0x280)...............................................................................9-49
PWRBD - Power Budgeting Data (0x288)...............................................................................................9-50
PWRBDSEL - Power Budgeting Data Select (0x284).............................................................................9-50
PWRBDV[9:0] - Power Budgeting Data Value [9:0] (0x300)...................................................................9-50
PWRBPBC - Power Budgeting Power Budget Capability (0x28C) .........................................................9-50
RID - Revision Identification Register (0x008) ........................................................................................9-13
SBUSN - Secondary Bus Number Register (0x019)...............................................................................9-15
SECSTS - Secondary Status Register (0x01E) ......................................................................................9-16
SLTIMER - Secondary Latency Timer Register (0x01B).........................................................................9-15
SMBUSCTL - SMBus Control (0x348)....................................................................................................9-56
SMBUSSTS - SMBus Status (0x344) .....................................................................................................9-55
SNUMCAP - Serial Number Capabilities (0x180) ...................................................................................9-43
SNUMLDW - Serial Number Lower Doubleword (0x184) .......................................................................9-43
SNUMUDW - Serial Number Upper Doubleword (0x188).......................................................................9-43
SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4)...........................................................9-36
SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0)...................................9-35
SUBUSN - Subordinate Bus Number Register (0x01A)..........................................................................9-15
SWCTL - Switch Control (0x32C)............................................................................................................9-52
SWERRCNT - Switch Internal Error Count (0x4E0)................................................................................9-63
SWERRCTL - Switch Internal Error Reporting Control (0x4DC).............................................................9-62
SWERRSTS - Switch Internal Error Status (0x4D8)...............................................................................9-62
SWPECTL - Switch Parity Error Control (0x4D4)....................................................................................9-61
SWSTS - Switch Status (0x328) .............................................................................................................9-51
SWTOCNT - Switch Time-Out Count (0x4EC)........................................................................................9-64

IDT Register List
PES5T5 User Manual xi January 28, 2011
Notes SWTOCTL - Switch Time-Out Control (0x4E4).......................................................................................9-63
SWTORCTL - Switch Time-Out Reporting Control (0x4E8)....................................................................9-63
VCR0CAP- VC Resource 0 Capability (0x210).......................................................................................9-45
VCR0CTL- VC Resource 0 Control (0x214)............................................................................................9-46
VCR0STS - VC Resource 0 Status (0x218)............................................................................................9-47
VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x220)..............................................................9-47
VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x224)..............................................................9-48
VCR0TBL2 - VC Resource 0 Arbitration Table Entry 2 (0x228)..............................................................9-48
VCR0TBL3 - VC Resource 0 Arbitration Table Entry 3 (0x22C).............................................................9-49
VID - Vendor Identification Register (0x000)...........................................................................................9-11
WAKEUPCNTL - Wakeup Protocol Control Register (0x5CC) ...............................................................9-64

IDT Register List
PES5T5 User Manual xii January 28, 2011
Notes