Infineon C166S V1 SubSystem User manual

Never stop thinking.
Microcontrollers
User’s Manual, V 1.6, August 2001
C166S V1 SubSystem
C166S V1 SubS R1

Edition 2001-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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Microcontrollers
User’s Manual, V 1.6, August 2001
Never stop thinking.
C166S V1 SubSystem
C166S V1 SubS R1

C166S V1 SubS R1
Revision History: 2001-08 V1.6
Previous Version: V 1.5
Page Subjects (
major changes since last revision )
2-12 Periodic Wake up from Idle or Sleep Mode
2-14 Clock Generation Unit, On-chip Bootstrap Loader
3-80..3-86 Particular Pipeline Effects
6-21 CALLA Instruction description
6-38 EINIT Instruction description
6-52 JMPA Instruction description
6-78 RETI Instruction description
6-91 SRVWDT Instruction description
6-96 TRAP Instruction description
8-1...8-29 RP0H Register
8-1, 8-34 DP3, P3, ODP4, ODP6 Registers
8-22 CLKEN System Clock Enable bit
8-31 External Bus Arbitration
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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User’s Manual
C166S V1 SubSystem
Table of Contents Page
User’s Manual I-1 V 1.6, 2001-08
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . 1-2
1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Basic CPU Concepts and Mega Core . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . 2-2
2.1.2 High Function 8-bit and 16-bit Arithmetic and Logic Unit . . . . . . . . . . . 2-3
2.1.3 Extended Bit Processing and Peripheral Control . . . . . . . . . . . . . . . . . 2-4
2.1.4 Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . . . 2-5
2.1.5 Programmable Multiple Priority Interrupt and PEC System . . . . . . . . . 2-6
2.2 The C166S System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1 Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.2 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3 The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3.1 Asynchronous / Synchronous Serial Channel (ASC0) . . . . . . . . . . . 2-9
2.2.3.2 High Speed Synchronous Serial Channel (SSC0) . . . . . . . . . . . . . 2-10
2.2.3.3 General Purpose Timer Unit (GPT12E) . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.4 Parallel Ports (PPorts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.5 Periodic Wakeup from Idle or Sleep Mode . . . . . . . . . . . . . . . . . . . . 2-12
2.2.6 OCDS and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.7 Core Control Block (CCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.8 Clock Generation Unit (CGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.2.9 On-chip Bootstrap Loader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
3 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 CPU Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . . . 3-7
3.3.1 Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.3.2 Sequential and Non-Sequential Instruction Flow . . . . . . . . . . . . . . . . 3-9
3.3.3 ATOMIC and EXTended Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.3.4 Code Addressing via Code Segment and Instruction Pointer . . . . . . 3-14
3.3.5 The CPU/System Configuration Register SYSCON . . . . . . . . . . . . . 3-17
3.4 Interrupt and Exception Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.4.1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.2 Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.4 Interrupt Control Functions in the Processor Status Word . . . . . . . 3-22
3.4.4.1 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . 3-24
3.4.4.2 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.4.5 Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.4.5.1 Software Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

User’s Manual
C166S V1 SubSystem
Table of Contents Page
User’s Manual I-2 V 1.6, 2001-08
3.4.5.2 Hardware Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.4.6 Peripheral Event Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.4.6.1 The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 3-33
3.4.6.2 PEC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
3.4.6.3 Short Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.4.6.4 Long Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.4.6.5 Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 3-41
3.4.6.6 PEC Channels Assignment and Arbitration . . . . . . . . . . . . . . . . . . 3-43
3.4.6.7 Programmable End of PEC Interrupt Level . . . . . . . . . . . . . . . . . . 3-44
3.5 Using General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3.5.1 Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
3.6 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.6.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.6.2 Long and Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.6.2.1 Addressing via Data Page Pointer . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
3.6.2.2 DPP Override Mechanism in the C166S . . . . . . . . . . . . . . . . . . . . 3-57
3.6.2.3 Long Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
3.6.2.4 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
3.6.3 The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
3.6.3.1 Stack Overflow and Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62
3.6.3.2 Linear Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
3.6.3.3 Circular (Virtual) Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
3.7 Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.7.1 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
3.7.2 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
3.7.3 The 16-bit Adder/Subtracter, Barrel Shifter
and the 16-bit Logic Unit 3-70
3.7.4 Bit-manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
3.7.5 Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
3.7.6 The Processor Status Word Register (PSW) . . . . . . . . . . . . . . . . . . 3-76
3.8 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
3.8.1 Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
3.8.1.1 General considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
3.8.1.2 Specific cases with core registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
3.8.1.3 Common portable solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86
3.8.2 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
3.9 Dedicated CSFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
3.10 Summary of CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
3.10.1 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
3.10.2 Core Special Function Registers Ordered by Name . . . . . . . . . . . . . 3-93
3.10.3 Core Special Function Registers ordered by Address . . . . . . . . . . . 3-94
3.10.4 Register Overview C166S Interrupt and Peripheral Event Controller 3-95

User’s Manual
C166S V1 SubSystem
Table of Contents Page
User’s Manual I-3 V 1.6, 2001-08
4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Data Organization in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2 Internal Local Memory Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 DPRAM and SFR-Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3.1 Data Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3.3 PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.4.1 External data accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.5 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.6.1 Data Organization in General Purpose Registers . . . . . . . . . . . . . . . 4-10
4.7 SFR / ESFR Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.8 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Short Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3 Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.4 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
6 Detailed Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
7 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.5 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
8 The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1 Single-chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2 External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.1 Multiplexed Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2.2 Demultiplexed Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.2.3 Switching Among the Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3 Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.3.1 ALE Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.3.2 Programmable Memory Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.3.3 Programmable Memory Tri-State Time . . . . . . . . . . . . . . . . . . . . . . 8-17
8.3.4 Read/Write Signal Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.3.5 Early WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.3.6 READY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4 Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

User’s Manual
C166S V1 SubSystem
Table of Contents Page
User’s Manual I-4 V 1.6, 2001-08
8.5 EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
8.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
8.7 The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
8.7.1 XBUS Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37
9 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1 Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
10 Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . . . 10-1
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.3 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3.1 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.3.1.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.3.1.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.3.1.3 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.3.2 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.3.2.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.3.2.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.3.2.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.3.3 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.3.3.1 Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.3.3.2 Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.3.4 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . 10-23
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
11 High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . . . . 11-1
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.2.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.2.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.2.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.2.5 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.2.6 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
12 General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Functional Description of Timer Block 1 . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.2.1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.2.2 Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12.2.3 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12.3 Functional Description of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . 12-26
12.3.1 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

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C166S V1 SubSystem
Table of Contents Page
User’s Manual I-5 V 1.6, 2001-08
12.3.2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.3.3 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
13 Instruction Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
14 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

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C166S V1 SubSystem
User’s Manual I-6 V 1.6, 2001-08

User’s Manual
C166S V1 SubSystem
Introduction
User’s Manual 1-1 V 1.6, 2001-08
1 Introduction
The rapidly growing area of embedded control applications is representing one of the
most time-critical operating environments for today’s microcontrollers. Complex control
algorithms have to be processed based on a large number of digital as well as analog
input signals, and the appropriate output signals must be generated within a defined
maximum response time. Embedded control applications also are often sensitive to
board space, power consumption, and overall system cost.
Embedded control applications therefore require microcontrollers, which...
• offer a high level of system integration
• eliminatetheneedforadditional peripheraldevicesand theassociatedsoftwareoverhead
• provide system security and fail-safe mechanisms
• provide effective means to control (and reduce) the device’s power consumption.
About this Manual
This manual describes the functionality of the 16-bit microcontroller-subsystem
C166S_R1 of the Infineon C166 Family, the C166S-class.

User’s Manual
C166S V1 SubSystem
Introduction
User’s Manual 1-2 V 1.6, 2001-08
1.1 The Members of the 16-bit Microcontroller Family
The microcontroller-subsystem of the Infineon 16-bit family has been designed to meet
the high performance requirements of real-time embedded control applications. The
architecture of this family has been optimized for high instruction throughput and
minimum response time to external stimuli (interrupts). Intelligent peripheral subsystems
have been integrated to reduce the need for CPU (Central Processing Unit) intervention
to a minimum extent. This also minimizes the need for communication via the external
bus interface. The high flexibility of this architecture allows to serve the diverse and
varying needs of different application areas such as automotive, industrial control, or
data communications.
The core of the 16-bit family has been developed with a modular family concept in mind.
All family members execute an efficient control-optimized instruction set (additional
instructions for members of the second generation). This allows an easy and quick
implementation of new family members with different internal memory sizes and
technologies, different sets of on-chip peripherals and/or different numbers of I/O (Input/
Output ) pins.
The Internal Bus Interface (IBI) concept opens a straight forward path for the integration
of application specific peripheral modules in addition to the standard on-chip peripherals
in order to build application specific derivatives.
As programs forembedded control applications become larger,
high level languages are
favoured by programmers, because high level language programs are easier to write, to
debug and to maintain.
The 80C166-type microcontrollers were the first generation of the 16-bit controller
family. These devices have established the C166 architecture.
The C165-type and C167-type devices are members of the second generation of this
family. This second generation is even more powerful due to additional instructions for
HLL support, an increased address space, increased internal RAM (Random Access
Memory) and highly efficient management of various resources on the external bus.
The C166S-type devices are members of the third generation of this family. This third
generation is the synthesizable version of the second generation.
Enhanced derivatives of this second/third generation provide additional features like
additional internal high-speed RAM, an integrated CAN-Module (Controller Area
Network), an on-chip PLL (Phase Locked Loop), etc.
Utilizing integration to design efficient systems may require the integration of application
specific peripherals to boost system performance, while minimizing the part count.
These efforts are supported by the so-called Internal Bus Interface, defined for the
Infineon 16-bit microcontrollers (XBus second generation). This Internal Bus Interface is
an internal representation of the External Bus Interface that opens and simplifies the
integration of peripherals by standardizing the required interface.

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C166S V1 SubSystem
Introduction
User’s Manual 1-3 V 1.6, 2001-08
1.2 Summary of Basic Features
The C166S is an improved representative of the Infineon family of full featured 16-bit
single-chip CMOS (Complementary Metal Oxide Silicon) microcontrollers. It combines
high CPU performance with high peripheral functionality.
Several key features contribute to the high performance of the C166S bases subsystem
(the indicated timings refer to a CPU clock of 50 MHz).
High Performance 16-Bit CPU With Four-Stage Pipeline
•40 ns minimum instruction cycle time, with most instructions executed in 1 cycle
•200 ns multiplication (16-bit *16-bit), 400 ns division (32-bit/16-bit)
• Multiple high bandwidth internal data buses
• Register based design with multiple variable register banks
• Single cycle context switching support
• 16 MBytes linear address space for code and data (von Neumann architecture)
• System stack cache support with automatic stack overflow/underflow detection
Control Oriented Instruction Set with High Efficiency
• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access
External Bus Interface
• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip slect signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for five programmable address areas
16-Priority-Level Interrupt System
• Up to 112 interrupt nodes with separate interrupt vectors
• 16 priority levels and 4(8) group levels
Up to 16-Channel Peripheral Event Controller (PEC)
• Interrupt driven single cycle data transfer
• Transfer count option (std. CPU interrupt afterprogrammable numberof PEC transfers)
• Long Transfer Counter
• Channel Linking
• Eliminates overhead of saving and restoring system state for interrupt requests

User’s Manual
C166S V1 SubSystem
Introduction
User’s Manual 1-4 V 1.6, 2001-08
Intelligent On-chip Peripherals
• General Purpose Timer Unit Timer Block 1:
–f
PDBUS+/4 maximum resolution
– 3 independent timers/counters
– Timer/counters can be concatenated
– 4 operation modes (timer, gated timer, counter, incremental)
– Seperate interrupt lines
• General Purpose Timer Unit Timer Block 2:
–f
PDBUS+/2 maximum resolution
– 2 independent timers/counters
– Timer/counters can be concatenated
– 3 operation modes (timer, gated timer, counter)
– Extendend capture/reload functions
– Seperate interrupt lines
• Asynchronous/Sychronous Serial Channel (ASC0)
with baud rate generator, parity, framing, and overrun error detection
• High Speed Synchronous Serial Cannel (SSC0)
with baud rate generator, programmable data length and shift direction
• Watchdog Timer with programmable timer events

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C166S V1 SubSystem
Introduction
User’s Manual 1-5 V 1.6, 2001-08
Complete Development Support
For the development tool support of its microcontrollers, Infineon follows a clear third
party concept. Currently around 120 tool suppliers world-wide, ranging from local niche
manufacturers to multinational companies with broad product portfolios, offer powerful
development tools for the Infineon C166/C166S microcontroller families, guaranteeing a
remarkable variety of price-performance classes as well as early availability of high
quality key tools such as compilers, assemblers, simulators, debuggers or in-circuit
emulators.
Infineon incorporates its strategic tool partners very early into the product development
process, making sure embedded system developers get reliable, well-tuned tool
solutions, which help them unleash the power of Infineon microcontrollers in the most
effective way and with the shortest possible learning curve.
The tool environment for the Infineon 16-bit microcontrollers includes the following tools:
• Compilers (C, MODULA2, FORTH)
• Macro-Assemblers, Linkers, Locaters, Library Managers, Format-Converters
• Architectural Simulators
• HLL debuggers
• Real-Time operating systems
• VERILOG chip models
• In-Circuit Emulators (based on bondout or standard chips)
• Plug-In emulators
• Emulation and Clip-Over adapters, production sockets
• Logic Analyzer disassemblers
• Starter Kits
• Evaluation Boards with monitor programs

User’s Manual
C166S V1 SubSystem
Introduction
User’s Manual 1-6 V 1.6, 2001-08

User’s Manual
C166S V1 SubSystem
System Overview
User’s Manual 2-1 V 1.6, 2001-08
2 System Overview
The architecture of the C166S combines the advantages of both RISC (Reduced
Instruction Set Computing) and CISC (Complex Instruction Set Computing) processors
in a very well-balanced way. The sum of the features which are combined results in a
high performance microcontroller, which is the right choice not only for today’s
applications, but also for future engineering challenges. C166S based derivatives does
not only integrate a powerful CPU (Central Processing Unit) core and a set of peripheral
units into one chip, but also connects the units in a very efficient way. One of the four
buses used concurrently on the C166S is the Internal Bus Interface, an internal
representation of the external bus interface. This bus provides a standardized method of
integrating application-specific peripherals to produce derivatives of the standard
C166S. This manual specially describes the C166S Subsystem consists of the CPU,
Interrupt Controller (ITC), Bus Controller (BC), On-Chip Debug Support (OCDS) and
other system specific peripherals and modules. The following figure shows the principles
of a C166S based system.
&&%
Local
Memory
up to 3 kByte
DPRAM
C166S
Subsystem
GPT12E SSC0
PLL
OSC
16
16
32
PDBUS+
PORT and dedicated Pins
0/1/4/6
Clock
Generation
Unit
Port
External
Bus
JTAG
RESET
&6
6\VWHP
PORT
BC
Config.
Block
External
Bus Interface
Internal
CONFIG
NMI
Peripheral
....
Local Memory Bus
Peripheral
....
Memory
Internal Bus Interface
Interrupt
Controller
CPU
Interrupt/
PEC Break Interface Trace Interface
ASC0
WDT
OCDS/
JTAG
PORT
Port Port
DPRAM
Interface
RC
PSC
CEG

User’s Manual
C166S V1 SubSystem
System Overview
User’s Manual 2-2 V 1.6, 2001-08
2.1 Basic CPU Concepts and Mega Core
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated Special Function Registers (SFRs). Additional
hardware is provided for a separate multiply and divide unit, a bit-mask generator and a
barrel shifter.
To meet thedemand for greater performance and flexibility, a number of areas has been
optimized in the processor core. Functional blocks in the CPU core are controlled by
signals from the instruction decode logic. These are summarized below, and described
in detail in the following sections:
1) High Instruction Bandwidth / Fast Execution
2) High Function 8-bit and 16-bit Arithmetic and Logic Unit
3) Extended Bit Processing and Peripheral Control
4) High Performance Branch-, Call-, and Loop Processing
5) Consistent and Optimized Instruction Formats
6) Programmable Multiple Priority Interrupt Structure
2.1.1 High Instruction Bandwidth / Fast Execution
Based on the hardware provisions, most of the C166S’s instructions can be executed in
just one machine cycle, which requires 2 CPU clock cycles T1 and T2 (2 * 1/ICPU =
4 TCL). For example, shift and rotate instructions are always processed within one
machine cycle, independent of the number of bits to be shifted.
Branch-, multiply- and divide instructions normally take more than one machine cycle.
These instructions, however, have also been optimized.
A 32-bit / 16-bit division takes 20 CPU clock cycles, a 16-bit * 16-bit multiplication takes
10 CPU clock cycles.
The instruction cycle time has been dramatically reduced through the use of instruction
pipelining. This technique allows the core CPUto process portions of multiple sequential
instruction stages in parallel. The following four stage pipeline provides the optimum
balancing for the CPU core:
FETCH: In this stage, an instruction is fetched from the internal ROM (Read Only
Memory) or RAM (Random Access Memory) or from the external memory, based on the
current Instruction Pointer (IP) value.
DECODE: In this stage, the previously fetched instruction is decoded and the required
operands are fetched.
EXECUTE: In this stage, the specified operation is performed on the previously fetched
operands.
WRITE BACK: In this stage, the result is written to the specified location.

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System Overview
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If this technique were not used, each instruction would require four machine cycles. This
increased performance allows a greater number of tasks and interrupts to be processed.
Instruction Decoder
Instruction decoding is primarily generated from PLA (Programmable Logic Array)
outputs based on the selected opcode. No microcode is used and each pipeline stage
receives control signals staged in control registers from the decode stage PLAs. Pipeline
holds are primarily caused by waitstates for external memory accesses and cause the
holding of signals in the control registers. Multiple-cycle instructions are performed
through instruction injection and simple internal state machines which modify required
control signals.
2.1.2 High Function 8-bit and 16-bit Arithmetic and Logic Unit
All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition,
for byte operations, signals are provided from bits six and seven of the ALU result to
correctly set the condition flags. Multiple precision arithmetic is provided through a
’CARRY-IN’ signal to the ALU from previously calculated portions of the desired
operation.
Most internal execution blocks have been optimized to perform operations on either 8-
bit or 16-bit quantities. Once the pipeline has been filled, one instruction is completed per
machine cycle, except for multiply and divide. An advanced Booth algorithm has been
incorporated to allow four bits to be multiplied and two bits to be divided per machine
cycle. Thus, these operations use two coupled 16-bit registers, MDL (Multiply Divide
Low Word) and MDH (Multiply Divide High Word), and require four and nine machine
cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one
machine cycle to setup and adjust the operands and the result. Even these longer
multiply and divide instructions can be interrupted during their execution to allow for very
fast interrupt response. Instructions have also been provided to allow byte packing in
memory while providing sign extension of bytes for word wide arithmetic operations. The
internalbus structure also allows transfers of bytes or words to or from peripherals based
on the peripheral requirements.
A set of consistent flags is automatically updated in the PSW (Program Status Word)
after each arithmetic, logical, shift, or movement operation. These flags allow branching
on specific conditions. Support for both signed and unsigned arithmetic is provided
through user-specifiable branch tests. These flags are also preserved automatically by
the CPU upon entry into an interrupt or trap routine. All targets for branch calculations
are also computed in the central ALU.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic
shifts are also supported.

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User’s Manual 2-4 V 1.6, 2001-08
2.1.3 Extended Bit Processing and Peripheral Control
A large number of instructions has been dedicated to bit processing. These instructions
provide efficient control and testing of peripherals while enhancing data manipulation.
Unlike other microcontrollers, these instructions provide direct access to two operands
in the bit-addressable space without requiring to move them into temporary flags.
The same logical instructions available for words and bytes are also supported for bits.
This allows the user to compare and modify a control bit for a peripheral in one
instruction. Multiple-bit shift instructions have been included to avoid long instruction
streams of single-bit shift operations. These are also performed in a single machine
cycle.
In addition, bit field instructions have been provided, which allow the modification of
multiple bits from one operand in a single instruction.
High Performance Branch-, Call-, and Loop Processing
Due to the high percentage of branching in controller applications, branch instructions
have been optimized to require one extra machine cycle only when a branch is taken.
This is implemented by precalculating the target address while decoding the instruction.
To decrease loop execution overhead, three enhancements have been provided:
• The first solution provides two cycle branch execution after the first iteration of a loop.
Thus, only one additional machine cycle is lost during the execution of the entire loop. In
loops which fall through upon completion, no additional machine cycles is lost when
exiting the loop. No special instructions are required to perform loops, and loops are
automatically detected during execution of branch instructions.
• The second loop enhancement allows the detection of the end of a table and avoids
the use of two compare instructions embedded in loops. One simply places the lowest
negative number at the end of the specific table, and specifies branching if neither this
value nor the compared value havebeen found. Otherwise the loop is terminated ifeither
condition has been met. The terminating condition can then be tested.
• The third loop enhancement provides a more flexible solution than the Decrement and
Skip on Zero instruction which is found in other microcontrollers. Through the use of
Compare and Increment or Decrement instructions, the user can make comparisons to
any value. This allows loop counters to cover any range. This is particularly
advantageous in table searching.
Saving of system state is automatically performed on the internal system stack avoiding
the use of instructions to preserve state upon entry and exit of interrupt or trap routines.
Call instructions push the value of the IP on the system stack, and require the same
execution time as branch instructions.
Instructions have also been provided to support indirect branch and call instructions.
This supports implementation of multiple CASE statement branching in assembler
macros and high level languages.