Infineon TRAVEO T2G Product manual

Technical reference manual Please read the Important Notice and Warnings at the end of this document 002-29852 Rev. *B
www.infineon.com 2022-04-18
TRAVEO™ T2G Automotive MCU:
TVII-B-E-4M body controller entry registers
Technical reference manual
About this document
Scope and purpose
The TRAVEO™ T2G body controller entry registers TRM provides reference information for registers and contains
respective programming details.
Intended audience
This manual is for system designer and programmers who are designing or programming using TVII-B-E-4M parts.

Technical Reference Manual 002-29852 Rev. *B
Definitions
Register Permission
The following table lists the register permission based on protection context and priviledges.
Permission Description
READ User mode = Read access, privilege mode = Read access, Non-
secure = yes
PRIVILEGE - WRITE User mode = Read access, privilege mode = Read and Write access,
Non-secure = yes
NO-ACCESS User mode = No access, Privilege mode = No access, Non-secure =
yes
SECURE - READ User mode = Read access, Privilege mode = Read access, Non-
secure = No
FULL Read and Write access in all modes, Non-secure = yes
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Technical Reference Manual 002-29852 Rev. *B
Software Access
The following table lists the behavior of registers, on various Software Read/Write Accesses.
SW
Access
HW
Access
Software Reads
Register
Software Writes
Register
Software Description
R any Register contents Ignored Software read-only
RW any Register contents Register takes data
written
Software read and write
RW1S any Register contents Every bit is set upon
writing 1
Software read and write 1 to
set
RW0S any Register contents Every bit is set upon
writing 0
Software read and write 0 to
set
RW1C any Register contents Every bit is cleared upon
writing 1
Software read and write 1 to
clear
RW0C any Register contents Every bit is cleared upon
writing 0
Software read and write 0 to
clear
RW1SC any NA NA Illegal
RW0SC any NA NA Illegal
W any Zero Register takes data
written
Software write only
W1S any Zero Every bit is set upon
writing 1
Software write 1 to set (no
read)
W0S any Zero Every bit is set upon
writing 0
Software write 0 to set (no
read)
W1C any Zero Every bit is cleared upon
writing 1
Software write 1 to clear (no
read)
W0C any Zero Every bit is cleared upon
writing 0
Software write 0 to clear (no
read)
W1SC any NA NA Illegal
W0SC any NA NA Illegal
A any NA NA Illegal
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Technical Reference Manual 002-29852 Rev. *B
Hardware Access
The following table lists the behavior of registers, on various Hardware Read/Write Accesses.
HW
Access
SW
Access
Hardware Description
any R Hardware read only
any RW Hardware read and write
any RW1S Hardware read and set
any RW0S Hardware read and set
any RW1C Hardware read and clear
any RW0C Hardware read and clear
any RW1SC Hardware read and set/clear
any RW0SC Hardware read and set/clear
any W Write access only
any W1S Hardware set
any W0S Hardware set
any W1C Hardware clear
any W0C Hardware clear
any W1SC Hardware set/clear
any W0SC Hardware set/clear
R A Not supported
RW A Hardware read and write
RW1S A Hardware read and set
RW0S A Hardware read and set
RW1C A Hardware read and clear
RW0C A Hardware read and clear
RW1SC A Not supported
RW0SC A Not supported
W A Not supported
W1S A Not supported
W0S A Not supported
W1C A Not supported
W0C A Not supported
W1SC A Not supported
W0SC A Not supported
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Technical Reference Manual 002-29852 Rev. *B
Core, Bus and Memory Access
The Cortex-M4 CPUSS uses AHB-Lite also for the system interconnect. Most of the IPs are compliant to the AHB-
Lite protocol.
The AHB-Lite protocol is little endian; the least significant byte of a word is mapped onto the word's lowest
byte address IPs use a bus data width of 32 bit.
This allows for byte (8-bit), halfword (16-bit) and word (32-bit) transfers. We distinguish two types of
transfer types:
- MMIO registers: These registers are typically used for IP control and status information. Unless otherwise
noted, transfers to these registers must be 32-bit transfers; any other transfer size generates an AHB-Lite bus
error. An IP's MMIO registers do not necessarily fully occupy a consecutive memory region; i.e. holes may be
present in the region
- Memory structures: This includes generic memory structures, such as system FLASH, system RAM and
system ROM, but also IP specific memory structures. Transfer to these memory structures may be 8-bit, 16-bit or
32-bit transfers; any other transfer size generates an AHB-Lite bus error. A memory structure fully occupies a
consecutive memory region; i.e. no holes are present in the memory structure region
A bus slave memory region may contain both MMIO registers and zero or more memory structures. Gaps
might exist in the bus slave's memory region, either due to gaps in the MMIO memory region or gaps between the
MMIO and memory structure region(s)
Gaps in the address space are reserved. Do not access these gaps, if accessed can result in Hard faults or
BUS ERROR depending on which bus segment or a peripheral an address space is allocated to.
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Technical Reference Manual 002-29852 Rev. *B
List of Partnumber
This TRM is valid for the following part numbers.
MPN Package Code Flash(KB) Work Flash(KB) SRAM(KB)
CYT2BL3BAS 64-LQFP 4160 128 512
CYT2BL3BAE 64-LQFP 4160 128 512
CYT2BL3CAS 64-LQFP 4160 128 512
CYT2BL3CAE 64-LQFP 4160 128 512
CYT2BL4BAS 80-LQFP 4160 128 512
CYT2BL4BAE 80-LQFP 4160 128 512
CYT2BL4CAS 80-LQFP 4160 128 512
CYT2BL4CAE 80-LQFP 4160 128 512
CYT2BL5BAS 100-LQFP 4160 128 512
CYT2BL5BAE 100-LQFP 4160 128 512
CYT2BL5CAS 100-LQFP 4160 128 512
CYT2BL5CAE 100-LQFP 4160 128 512
CYT2BL7BAS 144-LQFP 4160 128 512
CYT2BL7BAE 144-LQFP 4160 128 512
CYT2BL7CAS 144-LQFP 4160 128 512
CYT2BL7CAE 144-LQFP 4160 128 512
CYT2BL8BAS 176-LQFP 4160 128 512
CYT2BL8BAE 176-LQFP 4160 128 512
CYT2BL8CAS 176-LQFP 4160 128 512
CYT2BL8CAE 176-LQFP 4160 128 512
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Technical Reference Manual 002-29852 Rev. *B
Memory mapping
MMIO IP Address Description
MMIO0 PERI 0x40000000 Peripheral interconnect
PERI_MS 0x40010000 Peripheral interconnect, master interface
MMIO1 CRYPTO 0x40100000 Cryptography component
MMIO2 CPUSS 0x40200000 CPU subsystem (CPUSS)
FAULT 0x40210000 Fault structures
IPC 0x40220000 IPC
PROT 0x40230000 Protection
FLASHC 0x40240000 Flash controller
SRSS 0x40260000 SRSS Core Registers (ver3)
BACKUP 0x40270000 SRSS Backup Domain (ver3)
DW 0 0x40280000 Datawire Controller
DW 1 0x40290000 Datawire Controller
DMAC 0x402a0000 DMAC
EFUSE 0x402c0000 EFUSE MXS40 registers
EFUSE_DATA 0x402c0800 eFUSE memory
MMIO3 HSIOM 0x40300000 High Speed IO Matrix (HSIOM)
GPIO 0x40310000 GPIO port control/configuration
SMARTIO 0x40320000 Programmable IO configuration
TCPWM 0x40380000 Timer/Counter/PWM
EVTGEN 0x403f0000 Event generator
MMIO5 LIN 0x40500000 LIN
CXPI 0x40510000 CXPI
CANFD 0 0x40520000 CAN Controller
CANFD 1 0x40540000 CAN Controller
MMIO6 SCB 0 0x40600000 Serial Communications Block (SPI/UART/I2C)
SCB 1 0x40610000 Serial Communications Block (SPI/UART/I2C)
SCB 2 0x40620000 Serial Communications Block (SPI/UART/I2C)
SCB 3 0x40630000 Serial Communications Block (SPI/UART/I2C)
SCB 4 0x40640000 Serial Communications Block (SPI/UART/I2C)
SCB 5 0x40650000 Serial Communications Block (SPI/UART/I2C)
SCB 6 0x40660000 Serial Communications Block (SPI/UART/I2C)
SCB 7 0x40670000 Serial Communications Block (SPI/UART/I2C)
MMIO9 PASS 0x40900000 Programmable Analog Subsystem for S40E
SFLASH SFLASH 0x17000000 FLASH Supervisory Region
SYSTEM CM0P 0xe0000000 Cortex-M0+ specific registers
CM4 0xe0000000 Cortex-M4 specific registers
SYSAP 0xe0000000 System debug Access Port (SYSAP) registers
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Technical Reference Manual 002-29852 Rev. *B
1 BACKUP
Description SRSS Backup Domain (ver3)
Base Address 0x40270000
Size 0x10000
Slave Num MMIO2 - 6
Register Name Address Permission Description
BACKUP_CTL 0x40270000 FULL Control
Note:VDDBAK_CTL VBACKUP_MEAS
EN_CHARGE_KEY are not available for this register
BACKUP_RTC_RW 0x40270008 FULL RTC Read Write register
BACKUP_CAL_CTL 0x4027000C FULL Oscillator calibration for absolute frequency
BACKUP_STATUS 0x40270010 FULL Status
BACKUP_RTC_TIME 0x40270014 FULL Calendar Seconds, Minutes, Hours, Day of Week
BACKUP_RTC_DATE 0x40270018 FULL Calendar Day of Month, Month, Year
BACKUP_ALM1_TIME 0x4027001C FULL Alarm 1 Seconds, Minute, Hours, Day of Week
BACKUP_ALM1_DATE 0x40270020 FULL Alarm 1 Day of Month, Month
BACKUP_ALM2_TIME 0x40270024 FULL Alarm 2 Seconds, Minute, Hours, Day of Week
BACKUP_ALM2_DATE 0x40270028 FULL Alarm 2 Day of Month, Month
BACKUP_INTR 0x4027002C FULL Interrupt request register
BACKUP_INTR_SET 0x40270030 FULL Interrupt set request register
BACKUP_INTR_MASK 0x40270034 FULL Interrupt mask register
BACKUP_INTR_MASKED 0x40270038 FULL Interrupt masked request register
BACKUP_RESET 0x40270048 FULL Backup reset register
BACKUP_BREG0 0x40271000 FULL Backup register region
BACKUP_BREG1 0x40271004 FULL Backup register region
BACKUP_BREG2 0x40271008 FULL Backup register region
BACKUP_BREG3 0x4027100C FULL Backup register region
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Technical Reference Manual 002-29852 Rev. *B
1.1 Register Details
1.1.1 BACKUP_CTL
Description: Control
Address: 0x40270000
Offset: 0x0
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain.
Default: 0x0
Bit-field Table
Bits76543210
Name None [7:4] WCO_EN
[3:3]
None [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] PRESCALER [13:12] None [11:10] CLK_SEL [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:20] VBACKUP
_MEAS
[19:19]
VDDBAK_CTL [18:17] WCO
_BYPASS
[16:16]
Bits 31 30 29 28 27 26 25 24
Name EN_CHARGE_KEY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
3 WCO_EN RW A 0 Watch-crystal oscillator (WCO) enable. If there is a
write in progress when this bit is cleared, the WCO will
be internally kept on until the write completes.
After enabling the WCO software must wait until
STATUS.WCO_OK=1 before configuring any
component that depends on clk_lf/clk_bak, like for
example RTC or WDTs. Follow the procedure in
BACKUP_RTC_RW to access this bit.
8:9 CLK_SEL RW A 0 Clock select for RTC clock
WCO 0 Watch-crystal oscillator input, available in Active,
DeepSleep, Hibernate, and XRES.
ALTBAK 1 This allows to use the LFCLK selection as an alternate
backup domain clock. Note that LFCLK is only
available in Active and DeepSleep power modes.
Note that LFCLK clock glitches can propagate into the
backup logic when the clock is stopped. For this
reason, if the WCO or ILO is intended as the clock
source then choose it directly instead of routing
through LFCLK.
ILO 2 Internal Low frequency Oscillator, available in Active,
DeepSleep, Hibernate, and XRES.
For Hibernate operation CLK_ILO_CONFIG.
ILO_BACKUP must be set. If there are multiple ILO,
this is ILO0.
LPECO_PRESCALER 3 Low-power external crystal oscillator prescaler output,
available in Active, DeepSleep, Hibernate, and XRES.
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Bits Name SW HW Default or
Enum
Description
12:13 PRESCALER RW A 0 Prescaler for real time clock used when
WCO_BYPASS=1 and CLK_SEL = WCO. Configure
this field before enabling the WCO, and do not change
this setting when WCO_EN=1.
0: 32768 Hz square wave. Connect a 32768 Hz square
wave to WCO output pin. Do not connect WCO input
pin.
1: reserved
2: reserved
3: reserved
16 WCO_BYPASS RW A 0 Configures the WCO for different board-level
connections to the WCO pins. For example, this can
be used to connect an external watch crystal oscillator
instead of a watch crystal. In all cases, the two related
GPIO pins (WCO input and output pins) must be
configured as analog connections using GPIO
registers, and they must be hooked at the board level
as described below. Configure this field before
enabling the WCO, and do not change this setting
when WCO_EN=1.
0: Watch crystal. Connect a 32.768 kHz watch crystal
between WCO input and output pins.
1: Clock signal, either a square wave or sine wave.
See PRESCALER field for connection information.
17:18 VDDBAK_CTL RW A 0 Controls the behavior of the switch that generates
vddbak from vbackup or vddd.
0: automatically select vddd if its brownout detector
says it is valid. If the brownout says its not valid, then
use vmax which is the highest of vddd or vbackup.
1,2,3: force vddbak and vmax to select vbackup,
regardless of its voltage.
19 VBACKUP_MEAS RW A 0 Connect vbackup supply to the vbackup_meas output
for measurement by an ADC attached to
amuxbusa_adft_vddd. The vbackup_meas signal is
scaled to 10 percent of vbackup, so it is within the
supply range of the ADC.
24:31 EN_CHARGE_KEY RW A 0 When set to 3C, the supercap charger circuit is
enabled. Any other code disables the supercap
charger. THIS CHARGING CIRCUIT IS FOR A
SUPERCAP ONLY AND CANNOT SAFELY CHARGE
A BATTERY. DO NOT WRITE THIS KEY WHEN
VBACKUP IS CONNECTED TO A BATTERY.
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1.1.2 BACKUP_RTC_RW
Description: RTC Read Write register
Address: 0x40270008
Offset: 0x8
Retention: Not Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain but reset in DEEPSLEEP.
Default: 0x0
Bit-field Table
Bits76543210
Name None [7:2] WRITE [1:1] READ [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 READ RW A 0 Read bit
When this bit is set the RTC registers will be copied to
user registers and frozen so that a coherent RTC value
can safely be read. The RTC will keep on running.
Do not set the read bit if the RTC is still busy with a
previous update (see RTC_BUSY bit) or if the Write bit
is set. Do not set the Read bit at the same time that
the Write bit is cleared.
1 WRITE RW A 0 Write bit
Only when this bit is set can the RTC registers be
written to (otherwise writes are ignored). This bit
cannot be set if the RTC is still busy with a previous
update (see RTC_BUSY bit) or if the Read bit is set or
getting set.
The user writes to the RTC user registers, when the
Write bit is cleared by the user then the user registers
content is copied to the actual RTC registers.
Only user RTC registers that were written to will get
copied, others will not be affected.
When the SECONDS field is updated then TICKS will
also be reset (WDT is not affected).
When the Write bit is cleared by a reset (brown
out/DeepSleep) then the RTC update will be
ignored/lost.
Do not set the Write bit if the RTC if the RTC is still
busy with a previous update (see RTC_BUSY). Do not
set the Write bit at the same time that the Read bit is
cleared.
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1.1.3 BACKUP_CAL_CTL
Description: Oscillator calibration for absolute frequency
Address: 0x4027000C
Offset: 0xC
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. Calibration only works when the PRESCALER is set to
32768. Writes are ignored unless Write bit is set
Default: 0x0
Bit-field Table
Bits76543210
Name None [7:7] CALIB_SIG
N [6:6]
CALIB_VAL [5:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name CAL_OUT
[31:31]
None
[30:30]
CAL_SEL [29:28] None [27:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 CALIB_VAL RW A 0 Calibration value for absolute frequency (at a fixed
temperature). Each step causes 128 ticks to be added
or removed each hour. Effectively that means that
each step is 1.085ppm (= 128/(60*60*32,768)).
Positive values 0x01-0x3c (1..60) add pulses, negative
values remove pulses, thus giving a range of +/-65.1
ppm (limited by 60 minutes per hour, not the range of
this field)
Calibration is performed hourly, starting at 59 minutes
and 59 seconds, and applied as 64 ticks every 30
seconds until there have been 2*CALIB_VAL
adjustments.
6 CALIB_SIGN RW A 0 Calibration sign:
0= Negative sign: remove pulses (it takes more clock
ticks to count one second)
1= Positive sign: add pulses (it takes less clock ticks to
count one second)
28:29 CAL_SEL RW A 0 Select calibration wave output signal
CAL512 0 512Hz wave, not affected by calibration setting (not
supported for 50/60Hz input clock:
CTL.PRESCALER!=0)
RESERVED 1 N/A
CAL2 2 2Hz wave, includes the effect of the calibration setting,
(not supported for 50/60Hz input clock:
CTL.PRESCALER!=0)
CAL1 3 1Hz wave, includes the effect of the calibration setting
(supported for all input clocks)
31 CAL_OUT RW A 0 Output enable for wave signal for calibration and allow
CALIB_VAL to be written.
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1.1.4 BACKUP_STATUS
Description: Status
Address: 0x40270010
Offset: 0x10
Retention: Not Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain.
Default: 0x0
Bit-field Table
Bits76543210
Name None [7:3] WCO_OK
[2:2]
None [1:1] RTC_BUSY
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 RTC_BUSY R W 0 Pending RTC write
2 WCO_OK R W 0 Indicates that output has transitioned.
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1.1.5 BACKUP_RTC_TIME
Description: Calendar Seconds, Minutes, Hours, Day of Week
Address: 0x40270014
Offset: 0x14
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these
will read as zero until the read bit it set and the values are copied from the RTC into these
registers..
Default: 0x1000000
Bit-field Table
Bits76543210
Name None [7:6] RTC_SEC [5:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] RTC_MIN [13:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
CTRL
_12HR
[22:22]
None
[21:21]
RTC_HOUR [20:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:27] RTC_DAY [26:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 RTC_SEC RW A 0 Calendar seconds, 0-59
8:13 RTC_MIN RW A 0 Calendar minutes, 0-59
16:20 RTC_HOUR RW A 0 Calendar hours, value depending on 12/24HR mode
0=24HR: [20:16]=0-23
1=12HR: [20]:0=AM, 1=PM, [19:16]=1-12
22 CTRL_12HR RW A 0 Select 12/24HR mode: 1=12HR, 0=24HR
24:26 RTC_DAY RW A 1 Calendar Day of the week, 1-7
It is up to the user to define the meaning of the values,
but 1=Monday is recommended
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1.1.6 BACKUP_RTC_DATE
Description: Calendar Day of Month, Month, Year
Address: 0x40270018
Offset: 0x18
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these
will read as zero until the read bit it set and the values are copied from the RTC into these
registers..
Default: 0x101
Bit-field Table
Bits76543210
Name None [7:5] RTC_DATE [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] RTC_MON [11:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
RTC_YEAR [22:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 RTC_DATE RW A 1 Calendar Day of the Month, 1-31
Automatic Leap Year Correction
8:11 RTC_MON RW A 1 Calendar Month, 1-12
16:22 RTC_YEAR RW A 0 Calendar year, 0-99
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1.1.7 BACKUP_ALM1_TIME
Description: Alarm 1 Seconds, Minute, Hours, Day of Week
Address: 0x4027001C
Offset: 0x1C
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. This register is only used when
BACKUP_ALM1_DATE.ALM_EN=1. Writes are ignored unless Write bit is set. After reset,
these will read as zero until the read bit it set and the values are copied from the RTC into
these registers..
Default: 0x1000000
Bit-field Table
Bits76543210
Name ALM_SEC
_EN [7:7]
None [6:6] ALM_SEC [5:0]
Bits 15 14 13 12 11 10 9 8
Name ALM_MIN
_EN [15:15]
None
[14:14]
ALM_MIN [13:8]
Bits 23 22 21 20 19 18 17 16
Name ALM
_HOUR_EN
[23:23]
None [22:21] ALM_HOUR [20:16]
Bits 31 30 29 28 27 26 25 24
Name ALM_DAY
_EN [31:31]
None [30:27] ALM_DAY [26:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 ALM_SEC RW A 0 Alarm seconds, 0-59
7 ALM_SEC_EN RW A 0 Alarm second enable: 0=ignore, 1=match
8:13 ALM_MIN RW A 0 Alarm minutes, 0-59
15 ALM_MIN_EN RW A 0 Alarm minutes enable: 0=ignore, 1=match
16:20 ALM_HOUR RW A 0 Alarm hours, value depending on 12/24HR mode
24HR: [4:0]=0-23
12HR: [4]:0=AM, 1=PM, [3:0]=1-12
23 ALM_HOUR_EN RW A 0 Alarm hour enable: 0=ignore, 1=match
24:26 ALM_DAY RW A 1 Alarm Day of the week, 1-7
It is up to the user to define the meaning of the values,
but 1=Monday is recommended
31 ALM_DAY_EN RW A 0 Alarm Day of the Week enable: 0=ignore, 1=match
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1.1.8 BACKUP_ALM1_DATE
Description: Alarm 1 Day of Month, Month
Address: 0x40270020
Offset: 0x20
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these
will read as zero until the read bit it set and the values are copied from the RTC into these
registers..
Default: 0x101
Bit-field Table
Bits76543210
Name ALM_DATE
_EN [7:7]
None [6:5] ALM_DATE [4:0]
Bits 15 14 13 12 11 10 9 8
Name ALM_MON
_EN [15:15]
None [14:12] ALM_MON [11:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ALM_EN
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 ALM_DATE RW A 1 Alarm Day of the Month, 1-31
Leap Year corrected
7 ALM_DATE_EN RW A 0 Alarm Day of the Month enable: 0=ignore, 1=match
8:11 ALM_MON RW A 1 Alarm Month, 1-12
15 ALM_MON_EN RW A 0 Alarm Month enable: 0=ignore, 1=match
31 ALM_EN RW A 0 Master enable for alarm 1.
0: Alarm 1 is disabled. Fields for date and time are
ignored.
1: Alarm 1 is enabled. Alarm triggers whenever the
new date and time matches all the enabled date and
time fields, which can happen more than once
depending on configuration. If none of the date and
time fields are enabled, then this alarm triggers once
every second.
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TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

Technical Reference Manual 002-29852 Rev. *B
1.1.9 BACKUP_ALM2_TIME
Description: Alarm 2 Seconds, Minute, Hours, Day of Week
Address: 0x40270024
Offset: 0x24
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. This register is only used when
BACKUP_ALM2_DATE.ALM_EN=1. Writes are ignored unless Write bit is set. After reset,
these will read as zero until the read bit it set and the values are copied from the RTC into
these registers..
Default: 0x1000000
Bit-field Table
Bits76543210
Name ALM_SEC
_EN [7:7]
None [6:6] ALM_SEC [5:0]
Bits 15 14 13 12 11 10 9 8
Name ALM_MIN
_EN [15:15]
None
[14:14]
ALM_MIN [13:8]
Bits 23 22 21 20 19 18 17 16
Name ALM
_HOUR_EN
[23:23]
None [22:21] ALM_HOUR [20:16]
Bits 31 30 29 28 27 26 25 24
Name ALM_DAY
_EN [31:31]
None [30:27] ALM_DAY [26:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 ALM_SEC RW A 0 Alarm seconds, 0-59
7 ALM_SEC_EN RW A 0 Alarm second enable: 0=ignore, 1=match
8:13 ALM_MIN RW A 0 Alarm minutes, 0-59
15 ALM_MIN_EN RW A 0 Alarm minutes enable: 0=ignore, 1=match
16:20 ALM_HOUR RW A 0 Alarm hours, value depending on 12/24HR mode
24HR: [4:0]=0-23
12HR: [4]:0=AM, 1=PM, [3:0]=1-12
23 ALM_HOUR_EN RW A 0 Alarm hour enable: 0=ignore, 1=match
24:26 ALM_DAY RW A 1 Alarm Day of the week, 1-7
It is up to the user to define the meaning of the values,
but 1=Monday is recommended
31 ALM_DAY_EN RW A 0 Alarm Day of the Week enable: 0=ignore, 1=match
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TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

Technical Reference Manual 002-29852 Rev. *B
1.1.10 BACKUP_ALM2_DATE
Description: Alarm 2 Day of Month, Month
Address: 0x40270028
Offset: 0x28
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. Writes are ignored unless Write bit is set. After reset, these
will read as zero until the read bit it set and the values are copied from the RTC into these
registers..
Default: 0x101
Bit-field Table
Bits76543210
Name ALM_DATE
_EN [7:7]
None [6:5] ALM_DATE [4:0]
Bits 15 14 13 12 11 10 9 8
Name ALM_MON
_EN [15:15]
None [14:12] ALM_MON [11:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ALM_EN
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 ALM_DATE RW A 1 Alarm Day of the Month, 1-31
Leap Year corrected
7 ALM_DATE_EN RW A 0 Alarm Day of the Month enable: 0=ignore, 1=match
8:11 ALM_MON RW A 1 Alarm Month, 1-12
15 ALM_MON_EN RW A 0 Alarm Month enable: 0=ignore, 1=match
31 ALM_EN RW A 0 Master enable for alarm 2.
0: Alarm 2 is disabled. Fields for date and time are
ignored.
1: Alarm 2 is enabled. Alarm triggers whenever the
new date and time matches all the enabled date and
time fields, which can happen more than once
depending on configuration. If none of the date and
time fields are enabled, then this alarm triggers once
every second.
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TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

Technical Reference Manual 002-29852 Rev. *B
1.1.11 BACKUP_INTR
Description: Interrupt request register
Address: 0x4027002C
Offset: 0x2C
Retention: Retained
IsDeepSleep: No
Comment: These bits are in vddbak domain. Interrupt signal from SRSS includes this register and also
BACKUP_INTR, if present.
Default: 0x0
Bit-field Table
Bits76543210
Name None [7:3] CENTURY
[2:2]
ALARM2
[1:1]
ALARM1
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ALARM1 RW1C RW1S 0 Alarm 1 Interrupt
1 ALARM2 RW1C RW1S 0 Alarm 2 Interrupt
2 CENTURY RW1C RW1S 0 Century overflow interrupt
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TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers