Infineon XMC7000 Series User manual

Application note
Please read the sections “Important notice” and “Warnings” at the end of this document
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www.infineon.com
2023-11-08
AN234253
Clock configuration setup in XMC7000 MCU
family
About this document
Scope and purpose
This application note describes how to set up the various clock sources in XMC7000 family MCUs and provides
examples including configuring PLL/FLL and calibrating the ILO.
Intended audience
This document is intended for anyone using XMC7000 family MCUs.
Associated part family
XMC7000 family of XMC™industrial microcontrollers.

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Table of contents
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 2
1Introduction .......................................................................................................................... 4
2Clock system for XMC7000 family MCUs .................................................................................... 5
2.1 Overview..................................................................................................................................................5
2.2 Clock resources .......................................................................................................................................5
2.3 Clock system functions ...........................................................................................................................6
2.4 Basic clock system settings...................................................................................................................12
3Configuring the clock resources..............................................................................................13
3.1 ECO configuration .................................................................................................................................13
3.1.1 Use case............................................................................................................................................13
3.1.2 Code preview....................................................................................................................................15
3.2 WCO configuration ................................................................................................................................16
3.2.1 Overview...........................................................................................................................................16
3.3 Setting the IMO......................................................................................................................................17
3.4 Setting ILO0/ILO1 ..................................................................................................................................17
4FLL and PLL configuration......................................................................................................18
4.1 Setting the FLL.......................................................................................................................................18
4.1.1 Overview...........................................................................................................................................18
4.1.2 Use case............................................................................................................................................18
4.1.3 Code preview....................................................................................................................................19
4.2 Setting the PLL ......................................................................................................................................20
4.2.1 Overview...........................................................................................................................................20
4.2.2 Use case............................................................................................................................................20
4.2.3 Code preview....................................................................................................................................22
5Internal clock configuration ...................................................................................................24
5.1 Configuring CLK_PATHx........................................................................................................................24
5.1.1 Code preview....................................................................................................................................25
5.2 Configuring CLK_HFx ............................................................................................................................26
5.2.1 Code preview....................................................................................................................................27
5.3 Configuring CLK_LF...............................................................................................................................27
5.4 Configuring CLK_FAST_0/CLK_FAST_1 ................................................................................................28
5.5 Configuring CLK_MEM...........................................................................................................................28
5.6 Configuring CLK_PERI...........................................................................................................................28
5.7 Configuring CLK_SLOW.........................................................................................................................28
5.8 Configuring CLK_GR..............................................................................................................................28
5.9 Configuring PCLK...................................................................................................................................28
5.9.1 PCLK configuration example ...........................................................................................................30
5.9.1.1 Use case.......................................................................................................................................30
5.9.1.2 Configuration ..............................................................................................................................31
5.9.2 Code preview....................................................................................................................................32
5.10 Configuring the ECO Prescaler ............................................................................................................33
5.10.1 Overview...........................................................................................................................................33
6Supplementary information...................................................................................................34
6.1 Input clocks in peripheral functions.....................................................................................................34
6.2 Clock calibration counter function.......................................................................................................34
6.2.1 Overview...........................................................................................................................................34

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Table of contents
6.2.2 Use case............................................................................................................................................35
6.2.3 Configuration ...................................................................................................................................35
6.2.3.1 Sample code for initial configuration of clock calibration counter with ILO0 and ECO...........36
6.3 CSV diagram and relationship of monitored clock and reference clock.............................................37
Glossary .......................................................................................................................................39
References....................................................................................................................................40
Revision history.............................................................................................................................41
Disclaimer.....................................................................................................................................42

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Introduction
1Introduction
XMC7000 family MCUs are targeted at industrial systems. These products enable a secure computing platform
and incorporate Infineon low-power flash memory along with multiple high-performance analog and digital
functions.
XMC7000 family clock system supports high-speed and low-speed clocks using both internal and external clock
sources. One of the typical use cases for clock input is for internal real-time clock (RTC). XMC7000 family
supports phase-locked loop (PLL) and frequency-locked loop (FLL) to generate clocks that operate the internal
circuit at a high speed. XMC7000 family also supports a function to monitor the clock operation and to measure
the clock difference of each clock with reference to a known clock.
To understand more on the functionality described and terminology used in this application note, see the
“Clocking System” chapter in the XMC7000 MCU family architecture reference manual.

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Clock system for XMC7000 family MCUs
2Clock system for XMC7000 family MCUs
2.1 Overview
The clock system in this series of MCUs is divided into two blocks. One selects the clock resources (such as
external oscillator and internal oscillator) and multiplies the clock (using FLL and PLL). The other distributes
and divides clocks to the CPU cores and other peripheral functions. However, there are some exceptions such
as RTC that can connect directly to a clock resource.
Figure 1 shows the overview of the clock system.
Clock Distribution/
Division
Clock Selection
and Multiplier
Internal Circuit
(CPU Core, Peripheral Functions,
and so on)
Clock Sources
(External, Internal)
Clock System
Figure 1 Clock system structure
2.2 Clock resources
The MCU supports two types of resource inputs –internal and external. Each of these internally supports three
types of clocks, respectively.
•Internal clock sources (all clocks are enabled by default):
−Internal main oscillator (IMO): Built-in clock with a frequency of 8 MHz (Typical)
−Internal low-speed oscillator 0 (ILO0): Built-in clock with a frequency of 32.768 kHz (Typical)
−Internal low-speed oscillator 1 (ILO1): Has the same function as ILO0, but ILO1 can monitor the clock of
ILO0
•External clock sources (all clocks are disabled by default):
−External crystal oscillator (ECO): Uses an external oscillator whose input frequency range is between 8
and 33.34 MHz
−Watch crystal oscillator (WCO): Uses an external oscillator whose frequency is stable 32.768 kHz, mainly
used by the RTC module
−External clock (EXT_CLK): The EXT_CLK is a 0.25 MHz to 80 MHz range clock that can be sourced from a
signal on a designed I/O pin. This clock can be used as the source clock for either PLL or FLL or can be
used directly by the high-frequency clocks.
For more details on functions such as IMO, PLL, and so on, and numerical values such as frequency, see the
XMC7000 MCU family architecture reference manual and the datasheet.

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Clock system for XMC7000 family MCUs
2.3 Clock system functions
Figure 2 shows the details of the clock selection and multiplier block. This block generates root frequency
clocks CLK_HF0 to CLK_HF7 from the clock resources. This block has the capability to select one of the
supported clock resources –FLL and PLL to generate the required high-speed clock. This MCU supports two
types of PLLs: PLL without spread spectrum clock generation (SSCG) and fractional operation (PLL200#x), and
PLL with SSCG and fractional operation (PLL400#x).
IMO
EXT_CLK
Predivider
(1/2/4/8)
CSV
CLK_HF0
CLK_PATH0
FLL
CLK_PATH1
PLL400
#0
CLK_PATH2
PLL400
#1
CLK_PATH3
PLL200
#0
CLK_PATH4
PLL200
#1
Predivider
(1/2/4/8)
CSV
CLK_HF1
Predivider
(1/2/4/8)
CSV
CLK_HF2
Predivider
(1/2/4/8)
CSV
CLK_HF3
Predivider
(1/2/4/8)
CSV
CLK_HF4
Predivider
(1/2/4/8)
CSV
CLK_HF5
Predivider
(1/2/4/8)
CSV
CLK_HF6
Predivider
(1/2/4/8)
CSV
CLK_HF7
CLK_PATH5
ECO
Prescaler
ECO
ILO0
ILO1
WCO
CSV
CLK_REF_HF
CSV
CSV
CLK_LF
ActiveDomain
DeepSleep Domain
Hibernate Domain
REF_MUX
PATH_MUX5
DSI_MUX5
ROOT_MUX4
ROOT_MUX5
ROOT_MUX6
ROOT_MUX7
ROOT_MUX3
ROOT_MUX2
ROOT_MUX1
ROOT_MUX0
PATH_MUX4
DSI_MUX4
BYPASS_MUX4
PATH_MUX3
DSI_MUX3
BYPASS_MUX3
PATH_MUX2
DSI_MUX2
BYPASS_MUX2
PATH_MUX1
DSI_MUX1
BYPASS_MUX1
PATH_MUX0
DSI_MUX0
BYPASS_MUX0
LFCLK_SEL
CLK_SEL
CLK_ILO0
CLK_BAK
Figure 2 Clock system block diagram

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Domain/block
Description
Active domain
Region of operation only in Active power mode
DeepSleep
domain
Region of operation in Active and DeepSleep power modes
Hibernate domain
Region of operation in the All Power mode
ECO prescaler
Divides the ECO and creates a clock that can be used with the CLK_LF clock. The division
function has a 10-bit integer divider and an 8-bit fractional divider
DSI_MUX
Selects a clock from ILO0, ILO1, and WCO
PATH_MUX
Selects a clock from IMO, ECO, EXT_CLK, and DSI_MUX output
CLK_PATH
CLK_PATHs 0 through 5 are used as the input sources for high-frequency clocks
CLK_HF
CLK_HFs 0 through 7 are recognized as high-frequency clocks
FLL
Generates the high-frequency clock
PLL
Generates the high-frequency clock. There are two kinds of PLL:
−PLL200: Without SSCG and fractional operation
−PLL400: With SSCG and fractional operation
BYPASS_MUX
Selects the clock to be output to CLK_PATH. In case of FLL, the clock that can be selected
is either the FLL output or clock input to FLL.
ROOT_MUX
Selects the clock source of CLK_HFx. The clocks that can be selected are CLK_PATHs 0
through 5.
Predivider
Predivider (divided by 1, 2, 4, or 8) is available to divide the selected CLK_PATH.
REF_MUX
Selects the CLK_REF_HF clock source
CLK_REF_HF
Used to monitor CSV of CLK_HF
LFCLK_SEL
Selects the CLK_LF clock source
CLK_LF
MCWDT source clock
CLK_SEL
Selects the clock to be input to the RTC
CLK_BAK
Mainly input to the RTC
CSV
Clock supervision to monitor the clock operation
Note: The clock configuration is done one time via the ModusToolbox™Device Configurator; the settings
code is auto generated.

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Figure 3 shows the distribution of CLK_HF0.
CLK_HF0 is the root clock for the CPU subsystem (CPUSS) and peripheral clock dividers. For more details on
Figure 3, see the XMC7000 MCU family architecture reference manual and the datasheet.
CLK_TRC_DBG
CLK_GR3
CLK_ME
M
PCLK
CLK_SLOW
SLOW_CLOCK_CTLregister, INT_DIVbit
Divider
(1-256)
CLK_HF0
CM0+
ROM / SRAM / FLASH
CPUSS
Slow Infrastructure
P-DMA / M-DMA
CRYPTO
MEM_CLOCK_CTLregister,
INT_DIVbit
Divider
(1-256)
PERI_GR3_CLOCK_CTL register, INT_DIVbit
Divider
(1-256)
CLK_PER
I
PERI_CLOCK_CTLregister,
INT_DIVbit
Divider
(1-256)
Event Generator
SMIF
CPUSS
Fast Infrastructure
SRSS
E-Fuse
Ethernet
CLK_GR4
PERI_GR4_CLOCK_CTL register, INT_DIVbit
Divider
(1-256)
SDHC
IOSS
TCPWM[0]
CLK_GR8
PERI_GR8_CLOCK_CTL register, INT_DIVbit
Divider
(1-256)
AUDIOSS
CPUSS(DEBUG)
TRC_DBG_CLOCK_CTLregister, INT_DIVbit
Divider
(1-256)
Peripheral
Clock Divider
#0
PERI
Figure 3 CLK_HF0 block diagram

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Clock system for XMC7000 family MCUs
Clock input
Description
CLK_MEM
Clock input to the CPUSS of Fast Infrastructure, Ethernet, and Serial Memory Interface
(SMIF)
CLK_PERI
Clock source for CLK_GR and peripheral clock divider
CLK_SLOW
Clock input to the CPUSS of Cortex®-M0+ and Slow Infrastructure, SDHC, and SMIF
CLK_GR
Clock input to peripheral functions. CLK_GR is grouped by the clock gater. CLK_GR has six
groups.
PCLK
Peripheral clock used in peripheral functions. PCLK can be configured for each channel of
IPs independently; it can select one divider to generate PCLK.
CLK_TRC_DBG
Clock input to CPUSS(DEBUG)
Divider
Divider has a function to divide each clock. It can be configured from 1 division to 256
divisions.
Figure 4 shows details of the peripheral clock divider #0.
This MCU needs a clock to each peripheral unit (the serial communication block (SCB), the Timer, Counter, and
PWM (TCPWM), etc.) and its respective channel. The clocks are controlled by their respective dividers.
This peripheral clock divider #0 has many peripheral clock dividers to generate the peripheral clock (PCLK). See
the datasheet for the number of dividers. The output of any of these dividers can be routed to any peripheral.
Note that the dividers already in use cannot be used for other peripherals or channels.
PCLK
Clock divider
8.0
CLK_PERI
PERI_DIV_8_CTL register, INT8_DIV
bit
Clock enable multiplexing
Clock divider
16.0
PERI_DIV_16_CTL register,
INT16_DIV bit
Clock divider
24.5
PERI_DIV_24_5_CTL register,
FRAC5_DIV bit & INT24_DIV bit
PERI_CLOCK_CTL register,
TYPE_SEL bit & DEV_SEL bit
4 dividers
3 dividers
1 dividers
124 multiplexers
Clock
Generation
Figure 4 Peripheral clock divider #0 block diagram
Block
Description
Clock divider8.0
Divides a clock by 8
Clock divider16.0
Divides a clock by 16
Clock divider24.5
Divides a clock by 24.5
Clock Enable Multiplexing
Enables the signal output from clock divider
Clock Generator
Divides CLK_PERI based on clock divider

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Clock system for XMC7000 family MCUs
Figure 5 shows the distribution of CLK_HF1.
CLK_HF1 is a clock source for CLK_FAST_0 and CLK_FAST_1. The clock distribution of CLK_HF1 is shown in
Figure 5. CLK_FAST_0 and CLK_FAST_1 are the input sources for the CM7_0 and CM7_1 respectively.
CLK_FAST_0
CLK_HF1 CM7_0
FAST_0_CLOCK_CTL register,
INT_DIV bit
Divider
(1-256)
CLK_FAST_1 CM7_1
FAST_1_CLOCK_CTL register,
INT_DIV bit
Divider
(1-256)
Figure 5 CLK_HF1 block diagram
Figure 6 shows the distribution of CLK_HF2.
CLK_HF2 is a clock source for CLK_GR and PCLK. The clock distribution of CLK_HF2 is shown in Figure 6.
CLK_GR5
PCLK
Peripheral
Clock Divider #1
PERI_GR5_CLOCK_CTL register,
INT_DIV bit
Divider
(1-256) CAN FD
EFUSE
CLK_GR6
PERI_GR6_CLOCK_CTL register,
INT_DIV bit
Divider
(1-256) TCPWM[1]*
SCB
CLK_GR9
PERI_GR9_CLOCK_CTL register,
INT_DIV bit
Divider
(1-256) SAR ADC
CLK_HF2
*：TCPWM[1] is for XMC7200 series
Figure 6 CLK_HF2 block diagram

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Clock system for XMC7000 family MCUs
Figure 7 shows details of peripheral clock divider #1.
Peripheral clock divider #1 has many peripheral clock dividers to generate PCLK. See the datasheet for the
number of each divider. The output of any of these dividers can be routed to any peripheral. Note that dividers
already in use cannot be used for other peripherals or channels.
PCLK
Clock divider
8.0
CLK_HF2
PERI_DIV_8_CTL register, INT8_DIV
bit
Clock enable multiplexing
Clock divider
16.0
PERI_DIV_16_CTL register,
INT16_DIV bit
Clock divider
24.5
PERI_DIV_24_5_CTL register,
FRAC5_DIV bit & INT24_DIV bit
PERI_CLOCK_CTL register,
TYPE_SEL bit & DEV_SEL bit
19 dividers
20 dividers
21 dividers
124 multiplexers
Clock
Generation
Figure 7 Peripheral clock divider #1 block diagram
Block
Description
Clock divider8.0
Divides a clock by 8
Clock divider16.0
Divides a clock by 16
Clock divider24.5
Divides a clock by 24.5
Clock Enable Multiplexing
Enables the signal output from the clock divider
Clock Generator
Divides CLK_PERI based on the clock divider
Figure 8 shows the distribution of CLK_HF3, CLK_HF4, CLK_HF5, and CLK_HF6. For more details on these
functions in Figure 8, see the XMC7000 MCU family architecture reference manual.
CLK_HF4 Ethernet
CLK_HF5 AUDIOSS
CLK_HF6 SDHC
CLK_HF3 Event Generator
SMIF
Figure 8 CLK_HF3, CLK_HF4, CLK_HF5, and CLK_HF6 block diagram
CLK_HF7 is dedicated to CSV. See the XMC7000 MCU family architecture reference manual for CSV description.

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Clock system for XMC7000 family MCUs
2.4 Basic clock system settings
This section displays the configuration of the clock system in the Device Configurator of ModusToolbox™
software.
You can configure the clock system according to your system in the Device Configurator as follows:
Figure 9 Basic clock system setting

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Configuring the clock resources
3Configuring the clock resources
3.1 ECO configuration
The ECO is disabled by default and needs to be enabled for usage. Also, trimming is necessary to use the ECO.
This device can set the trimming parameters that control the oscillator according to the crystal unit and
ceramic resonator. The method to determine the parameters differs between the crystal unit and ceramic
resonator.
You can configure these parameters in the System tab of the ModusToolbox™Device Configurator.
ModusToolbox™software will automatically generate the corresponding code.
Figure 10 ECO configuration
3.1.1 Use case
Oscillator to use
Crystal unit
Fundamental frequency
16 MHz
Maximum drive level
300.0 µW
Equivalent series resistance
150.0 ohm
Shunt capacitance
0.530 pF
Parallel load capacitance
8.000 pF
Crystal unit vendor’s recommended value of negative resistance
1500 ohm
Automatic gain control
OFF
Note: These values are decided in consultation with the crystal unit vendor.
You can configure these parameters in the System tab of the Device Configurator; based on these,
ModusToolbox™software automatically generates the corresponding code.

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Configuring the clock resources
Double-click the Device Configurator on the left Quick Panel.
(you can also double-click design.modus to open the Device Configurator in your
project,\bsps\TARGET_APP_KIT_XMC72_EVK\config\design.modus)
Figure 11 Quick Panel
Figure 12 ECO use case

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Configuring the clock resources
3.1.2 Code preview
This code is auto generated after configuration in the Device Configurator.
Figure 13 Code preview

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Configuring the clock resources
3.2 WCO configuration
3.2.1 Overview
The WCO is disabled by default. Accordingly, WCO cannot be used unless it is enabled. Figure 14 shows how to
configure the registers for enabling the WCO.
To disable the WCO, write ‘0’to the WCO_EN bit of the BACKUP_CTL register.
Figure 14 Enabling the WCO
You can enable the WCO in the System tab of the Device Configurator. ModusToolbox™software automatically
generates the corresponding code.
Figure 15 WCO Configuration
Start
Write "1"to the WCO_EN bit
Check the state
of WCO_OK and the state of
TIMEOUT ?
Yes
End(Success)
No
Define variable to count timeout
Configure the initial value of TIMEOUT
Define Variables TIMEOUT
Configure TIMEOUT Value
Write "1"to the WCO_EN bit. And make WCO available.
TIMEOUT= 0?
Subtract TIMEOUT value
End(Timeout)
Yes
No
Check whetherthe processingexited the loop at TIMEOUT
(1)
(4)
(3)
(2)

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Configuring the clock resources
This code is auto generated after configuration in the Device Configurator.
Figure 16 Code preview
3.3 Setting the IMO
The IMO is enabled by default so that all functions operate properly. The IMO will automatically be disabled
during DeepSleep, Hibernate, and XRES modes. Therefore, it is not required to set IMO explicitly.
3.4 Setting ILO0/ILO1
ILO0 and ILO1 are enabled by default.
Note: ILO0 is used as the operating clock of the watchdog timer (WDT). Therefore, if ILO0 is disabled, you
should disable the WDT. To disable ILO0, write ‘0b01’ to the WDT_LOCK bit of the WDT_CTL
register, and then write ‘0b00’ to the ENABLE bit of the CLK_ILO0_CONFIG register.

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FLL and PLL configuration
4FLL and PLL configuration
This section shows the configuration of FLL and PLL in the clock system.
4.1 Setting the FLL
4.1.1 Overview
The FLL must be configured before it is used. The FLL has a current-controlled oscillator (CCO); the output
frequency of this CCO is controlled by adjusting the trim of the CCO.
4.1.2 Use case
Input clock frequency
16 MHz
Output clock frequency
100 MHz
You can configure these parameters in the System tab of the Device Configurator; based on these,
ModusToolbox™software automatically generates the corresponding code.
1. In the Device Configurator, select PATH_MUX0.
2. On the PATH_MUX Parameters pane, select ECO (16 MHz) as the source clock.
Figure 17 Setting ECO (16 MHz) as the source clock

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FLL and PLL configuration
Select FLL, and in the FLL –Parameters pane, under General, enter the Desired Frequency (MHz) as 100.000 to
set the frequency as 100 MHz.
Figure 18 Setting output clock frequency as 100.000 MHz
4.1.3 Code preview
Figure 19 Code preview

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FLL and PLL configuration
4.2 Setting the PLL
4.2.1 Overview
You must configure the PLL before using it.
You can configure these parameters in the System tab of the Device Configurator; based on these,
ModusToolbox™software automatically generates the corresponding code.
4.2.2 Use case
Parameter
Value
Input clock frequency
8.000 MHz
Output clock frequency
350.000 MHz (PLL400 #0)
250 MHz (PLL400 #1)
200.000 MHz (PLL200 #0)
100.000 MHz (PLL200 #1)
First, select the source clock for PLL400M#0/PLL400M#1/PLL200M#0/PLL200M#1 in
PATH_MUX1/PATH_MUX2/PATH_MUX3/PATH_MUX4.
Figure 20 Setting ‘IMO’ in ‘Parameters’