Infineon PSoC 4 Operator's manual

Application Note Please read the Important Notice and Warnings at the end of this document 001-84858 Rev. *N
www.infineon.com page 1 of 45 2021-03-23
AN84858
PSoC 4 Programming Using an External
Microcontroller (HSSP)
About this document
Scope and purpose
AN84858 shows you how to implement PSoC™4 device programming with an external microcontroller by using
modular C code. In this process, called Host Sourced Serial Programming (HSSP), the host microcontroller
programs PSoC 4 through the serial wire debug (SWD) interface. The C code is written so that it can be ported to
any microcontroller with minimal changes, speeding up HSSP application development for PSoC 4.
More code examples? We heard you.
To access an ever-growing list of hundreds of PSoC code examples, please visit our code examples web page.
You can also explore the video training library here.
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 1
1Introduction .......................................................................................................................... 3
1.1 Types of Programmers............................................................................................................................3
1.2 Terms and Definitions.............................................................................................................................3
2HSSP Firmware Architecture ................................................................................................... 5
2.1 SWD Protocol Physical Layer ..................................................................................................................6
2.2 SWD Protocol Packet Layer.....................................................................................................................6
2.3 Fetching Programming Data...................................................................................................................6
2.4 HSSP Programming Steps.......................................................................................................................7
2.5 HSSP Timeout Parameters .....................................................................................................................7
2.6 HSSP Programming Data........................................................................................................................8
2.7 Main Application Code ............................................................................................................................8
2.8 HSSP Error Status....................................................................................................................................8
3Hardware Connections for HSSP Programming ........................................................................10
4Porting the HSSP Application to a Host Programmer.................................................................11
4.1 Files That Must Be Ported .....................................................................................................................11
4.2 Code Changes Required While Porting.................................................................................................11
5Calculating HSSP Timeout Parameters ....................................................................................13
5.1 DEVICE_ACQUIRE_TIMEOUT.................................................................................................................13
5.2 SROM_POLLING_TIMEOUT ...................................................................................................................14
5.3 XRES_PULSE_100US .............................................................................................................................15
6Interface for Receiving HSSP Programming Data ......................................................................17
7HSSP Timing Validation .........................................................................................................19
8Power Cycle Mode Programming.............................................................................................20
9Testing the Example Projects .................................................................................................21
9.1 For CY8CKIT-038 PSoC 4 Development Kit...........................................................................................21

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Table of contents
9.2 For Kits with Onboard PSoC 5LP Programmer (KitProg).....................................................................21
9.3 For Kits with Onboard PSoC 5LP Programmer (KitProg2)...................................................................25
10 Tips and Tricks for Debugging HSSP Issues...............................................................................29
11 Summary .............................................................................................................................30
12 Related Documentation .........................................................................................................31
12.1 Application Notes..................................................................................................................................31
12.2 Programming Specifications ................................................................................................................31
12.3 Architecture Technical Reference Manuals..........................................................................................31
12.4 Web Page ...............................................................................................................................................31
13 List of Attached Projects ........................................................................................................32
14 Appendix A: Hex File Parser Application...................................................................................33
14.1 Using the Hex File Parser Application...................................................................................................33
14.2 Adding the Generated Files to PSoC Creator Example Project............................................................34
14.2.1 Using the HexImage.c, HexImage.h Files for the PSoC 4xxxL/ PSoC 41x8_BLE/ 42x8_BLE/ 41XXS
Plus Family Devices:.........................................................................................................................36
15 Appendix B: Status Codes for SROM Request ............................................................................37
16 Appendix C: Bit Field Definitions of HSSP Error Status Register ..................................................39
16.1 Bits[2:0] –SWD Acknowledge Response (SWD ACK [2:0])....................................................................39
16.2 Bit 3 –SWD Read Data Parity Error .......................................................................................................39
16.3 Bit 4 –Port Acquire Timeout.................................................................................................................39
16.4 Bit 5 –SROM Polling Timeout Error ......................................................................................................40
16.5 Bit 6 –Verification Failure .....................................................................................................................40
16.6 Bit 7 –Transition Error ..........................................................................................................................40
17 Appendix D: HSSP Functions...................................................................................................41
Revision history.............................................................................................................................44

Application Note 3 of 45 001-84858 Rev. *N
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PSoC 4 Programming Using an External Microcontroller (HSSP)
Introduction
1Introduction
PSoC 4 device programming refers specifically to the programming of the nonvolatile memory in PSoC 4 by
using an external host programmer. The host can be the programmer supplied by Infineon (CY8CKIT-002
MiniProg3), a third-party programmer, or a custom programmer (for example, an onboard microcontroller).
This application note explains how to implement a host programmer to program a PSoC 4 device. For more
information on the PSoC 4 architecture and to learn how to create projects for PSoC 4 using the PSoC Creator™
software, see AN79953 –Getting Started with PSoC 4.
1.1 Types of Programmers
The type of device programmer you choose depends on the stage of product development:
Prototyping: A programmer must be able to perform the following functions:
1. Program the device.
2. Debug the device to troubleshoot the application.
The programmers used during prototyping must also interact with the integrated design environment (IDE)—
for example, PSoC Creator™—to accomplish the programming and debugging operations. A few examples are
MiniProg3 or the PSoC 5LP Prototyping Kit, which can be used as a low-cost programmer/debugger.
Production: You require a programmer that can program multiple devices. It parses the hex file to extract the
necessary information and implements programming through the programming interface, such as SWD.
There are two major categories of programmers:
•In-system programmers can program the target device directly on the end-application PCB. You can
connect the external programmer to the device’s programming pins to do in-system programming.
•Socket programmers require the target device to be placed on the programmer hardware socket for
programming. After programming, solder the target device to the end-application PCB. Most third-party
production programmers are of the socket type.
In both in-system and socket programming, the programmer implements an HSSP algorithm and generates
signals to program the hex file’s data.
This application note provides the C code to implement an HSSP programmer. You can easily port this C code
to any host microcontroller with minimal changes. By porting, you reduce the time required to develop HSSP
applications for PSoC 4 devices. The project provided with this application note uses a PSoC 5LP device as a
host programmer to program the target device.
Before reading this application note, review the programming specifications document of the respective device
listed in the Related Documentation section. This document explains the programming interface,
programming algorithm, hardware connection, and electrical timing specifications required to program PSoC 4
devices. This application note is a practical implementation of the programming specifications.
1.2 Terms and Definitions
•Serial wire debug (SWD): Developed by ARM, the SWD protocol uses only two wires—SWDCLK (clock) and
SWDIO (bidirectional data line)—to program and debug.
•Debug access port (DAP): DAP is the program/debug interface between SWD and the CPU in PSoC 4 It
includes a debug port (DP) and an access port (AP).
−DP is responsible for the physical connection to the programmer/debugger.
−AP provides the interface between the DAP module and the Cortex-M0 CPU, the flash memory, and so on.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Introduction
•HSSP: HSSP refers to the programming of the target device on the board using a host microcontroller. The
target is programmed through the SWD interface. In this application note, HSSP uses a bit-banging
implementation to program the target device. Bit-banging programming refers to the technique in which
programming pins are manipulated using a software code that resides in the host programmer.
•Differences between bootloading and HSSP: In embedded systems, bootloaders are also used to update the
system firmware. Bootloading and HSSP differ in the following key aspects:
−Bootloaders are used to update the flash memory of the device over a standard communication protocol.
Bootloaders can update only a specific portion of the flash memory, known as the bootloadable area.
−On the other hand, HSSP supports complete programming of the flash memory in the target device.
−Bootloaders can use any standard communication interface (such as, USB, I2C, SPI, and UART) to update
the firmware, while HSSP uses an SWD or JTAG interface to program the flash. PSoC 4 supports only SWD
interfaces.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
2HSSP Firmware Architecture
HSSP for the target device is implemented in multiple layers using modular C code. These layers are as follows:
1. SWD Protocol Physical layer
2. SWD Protocol Packet layer
3. HSSP Programming Steps layer
See Figure 1 for the flow of control among these layers.
Note: See the A_Hssp_Programmer project, which uses PSoC 5LP as the external host programmer,
attached with this application note for the implementation of this firmware.
Figure 1 HSSP Firmware Architecture
The HSSP Programming Steps layer uses the “Fetching Programming Data” interface to extract the
programming data from the source of the data (for example, the hex file data provided by any communication
interface—I2C, SPI, UART, or USB or host flash—as Figure 1 shows. In addition, the “HSSP Programming Step”
layer uses the HSSP Timeout Parameters interface to configure timeouts in its programming APIs.
Host Programmer
SWDIO
SWDCK
XRES(1)
Target PSoC 4
device
RegisterDefines.h,
SWD_PhysicalLayer.h,
SWD_PhysicalLayer.c
SWD Protocol Physical Layer
SWD_PacketLayer.h,
SwdPacketLayer.c
SWD_UpperPacketLayer.h,
Swd_UpperPacketLayer.c
SWD Protocol Packet Layer
Timeout.h,
Timeout.c
HSSP Timeout
Parameters
ProgrammingSteps.h,
ProgrammingSteps.c
HSSP Programming Steps
DataFetch.h,
DataFetch.c
Fetching Programming
Data
HexImage.h,
HexImage.c
Programming
Data
main.c
Main application code
Device Acquire
Verify Silicon ID
Erase all Flash
Checksum Privileged Calculation
Program Flash
Exit HSSP Programming mode
Verify Flash
Program Protection Settings
Verify Protection Settings
Verify Checksum
HSSP Implementation Flow
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
(1)For power cycle mode programming, device power rails need to be
toggled instead of the reset (XRES) pin

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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
All layers used in the firmware architecture, as shown in Figure 1, are discussed in the following sections.
2.1 SWD Protocol Physical Layer
Files that constitute the SWD Protocol Physical layer are described:
Table 1 SWD Protocol Physical Layer Files
Source Files
Description
RegisterDefines
(.hfile)
This file defines the port number, pin number, input/output register, and drive mode
register of the programming pins.
SWD_PhysicalLayer
(.c and .hfiles)
These files contain macros and functions to manipulate the programming pins. The
pins are defined in the RegisterDefines.h file.
The codes in these files are written for PSoC 5LP as the host microcontroller. If these files are ported to any
other host microcontroller, then you should modify all the functions and macros appropriately.
Note: See “Pin Names and Requirements” in the programming specifications of the respective device
listed in the Related Documentation section for details on the pin configurations on the host side.
2.2 SWD Protocol Packet Layer
Files that constitute the SWD Protocol Packet layer are described:
Table 2 SWD Protocol Packet Layer Files
Source Files
Description
SWD_PacketLayer
(.cand .hfiles)
These files define the packet routines for sending the SWD Read and
SWD Write packets per the SWD protocol.
SWD_UpperPacketLayer
(.cand .hfiles)
These files use the functions defined in SWD_PacketLayer to
implement functions that directly read and write to the DAP register
and CPU address space.
The functions defined in this layer are called directly by the functions in the ProgrammingSteps.c file.
All of these SWD packet functions operate on three global variables—swd_PacketHeader,
swd_PacketAck, and swd_PacketData[]—that are accessed by the functions in the top layer files, as
Figure 1 shows.
2.3 Fetching Programming Data
Files used for fetching the programming data to the upper layer functions are described:
Table 3 Data Fetch Layer File
Source File
Description
DataFetch
(.cand .hfiles)
These files contain the routines to fetch the programming data from the HexImage.c file
and then pass that data to the functions in the ProgrammingSteps.c file.
The programming data includes flash row data, flash protection data, chip protection
data, Silicon ID, checksum, and the total number of flash rows.
Modify the definitions of the functions based on the method that you use to get the HSSP programming data.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
Note: See the section Interface for Receiving HSSP Programming Data for information on how to
modify the HSSP source code.
2.4 HSSP Programming Steps
This layer includes the files named ProgrammingSteps.c and ProgrammingSteps.h. These files contain the top-
level functions of the HSSP application. These functions are described in sequence as follows:
1. Device Acquire: In this step, the device is acquired by sending a specific sequence through the SWD
interface after a device reset. As a result, the host programmer can control the Cortex-M0 CPU and other
system resources, such as SRAM and registers. The PSoC 40xx, PSoC 4xx7_BLE, PSoC 40xxS PSoC 41xxS and
PSoC 4100PS family of devices requires the internal main oscillator (IMO) frequency to be set at 48 MHz
before flash erase/write operations. This operation is also included in the Device Acquire routine for these
devices.
Note: Some of the devices in the PSoC 4000 family do not have a dedicated reset (XRES) pin, and have to
be reset by toggling the device power rails. This is referred to as Power Cycle Mode programming.
Refer to the Power Cycle Mode Programming section for details on the changes required for
modifying the code to support power cycle mode programming.
2. Verify Silicon ID: This step verifies that the acquired device is the same as the one for which the hex file was
generated.
3. Erase All Flash: This step erases all user rows and corresponding flash protection.
4. Checksum Privileged Calculation: After all the user rows are erased, this step calculates the checksum of
the privileged rows, which is used to verify the checksum of the user rows in Step 9.
5. Program Flash: In this step, flash is programmed using the programming data in the hex file and SROM API
calls.
6. Verify Flash: This step is used to verify the flash data programmed in the previous step with the data in the
hex file. This step is optional but highly recommended.
7. Program Protection Settings: In this step, row protection settings and chip protection settings from the
hex file are written to the specific flash area.
8. Verify Protection Settings: Both protection settings are matched with the settings in the hex file.
9. Verify Checksum: This step matches the checksum of the user data in the flash with the checksum in the
hex file. It uses the checksum of the privileged rows calculated in step 4.
10.Exit HSSP Programming Mode: This step releases the target device from programming mode.
Each of these steps is described by functions made up of basic SWD instructions. See the programming
specifications document of the respective device listed in the Related Documentation section for detailed
information.
The functions declared in the ProgrammingSteps.h file access the functions, definitions, and global variables
from three layers: SWD Protocol Packet layer, DataFetch layer, and Timeout layer. The functions provided in the
ProgrammingSteps.c and ProgrammingSteps.h files cover all the steps required to program the target device.
2.5 HSSP Timeout Parameters
Table 4 Timeout Layer Files
Source File
Description
Timeout (.c and .h
files)
These files contain the timestamp definitions and the delay routines used in HSSP.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
Timestamp definitions are derived from the electrical timing specifications provided in the Device
Programming Specifications. The values of these timestamp parameter definitions in Timeout.h are for a
PSoC 5LP host programmer running at a clock frequency of 63 MHz.
Timestamp definitions and the delay routine are used in the function definitions in the ProgrammingSteps.c
file.
To learn how to calculate the timestamp parameters for a specific host programmer, see the section
Calculating HSSP Timeout Parameters.
2.6 HSSP Programming Data
Files that contain the programming data to be stored in the host programmer are described:
Table 5 Files Containing the Programming Data
Source Files
Description
HexImage
(.cand .hfiles)
These files contain the data to be programmed into the target device.
They also store the target device parameters used in HSSP programming, such as silicon ID,
checksum, total number of flash rows, and number of bytes per flash row.
The data in these files is stored in PSoC 5LP flash memory as an array of constants.
These files are generated by the C# application Hex File Parser, which is provided with this application note.
This application generates these files by taking the target device hex file as the input. The details of this
application are provided in Appendix A.
For details on the hex file format, see “Appendix B. Intel Hex File Format” in the programming specifications
document of the respective device listed in the Related Documentation section of this document.
For host programmers that lack the memory capacity to store the programming data in the on-chip memory,
the HexImage.c and HexImage.h files are not required. In such cases, the HSSP programming data is typically
sent to the host as packets through a communication interface, such as I2C, UART, or USB.
Note: See the section Interface for Receiving HSSP Programming Data for information on modifying
the HSSP source code according to the method used to get the programming data.
2.7 Main Application Code
The main.c file is the main application code that calls the top-level HSSP programming steps in the sequence
shown in Figure 1. The function ProgramDevice() in main.c executes all the steps. Each step must be
executed successfully before you can proceed to the next step.
The HSSP operation is aborted if a FAILURE is returned after any step. The error status returned by the
ReadHsspErrorStatus()function is used to identify the cause of the error. The status of the HSSP
operation, along with the error status register, is displayed on a character LCD in the attached HSSP project.
Note: The character LCD and Pin_Start routines are specific to the PSoC 5LP host programmer and,
therefore, should be modified as required for any other host programmer.
2.8 HSSP Error Status
When any of the top-level steps in the HSSP application returns a failure status, the
ReadHsspErrorStatus() function is called from the main application code to get the details of the error.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
This function returns the status byte. Use the status byte to infer error details from the bit field definitions.
See Figure 2 for the bit fields returned by this function.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SWD ACK [2:0] response
SWD Read Data
Parity Error
SROM Polling Timeout
Port Acquire Timeout
Transition Error
Verification Failure
Figure 2 HSSP Error Status Register
Table 6 describes the bit field definitions of this status register.
Table 6 HSSP Error Status Register
Bit
Field Name
Description
[2:0]
SWD ACK
These three bits store the acknowledge response of previous SWD
transactions.
3
SWD Read Data Parity
Error
If this bit is set, it indicates a parity error in the data received by the host.
4
Port Acquire Timeout
If this bit is set, it indicates that the device was not acquired within the
timeout window.
5
SROM Polling Timeout
If this bit is set, It indicates that SROM operations exceed 1 second.
6
Verification Failure
This bit is set in multiple steps. Depending upon the step where failure
occurred, the reason can be inferred.
7.
Transition Error
If this bit is set, it indicates that the chip protection settings read from the
chip and the hex file indicates a wrong transition.
To learn more about this register and for a detailed explanation of the bit fields, see Appendix C: Bit Field
Definitions of HSSP Error Status Register.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Hardware Connections for HSSP Programming
3Hardware Connections for HSSP Programming
HSSP programming in PSoC 4 uses the SWD interface pins (SWDIO and SWDCK) and the external reset pin
(XRES). The host programmer pin drive mode requirements are explained in the “Physical Layer”section in the
programming specifications document listed in the Related Documentation section of this document. Figure
3shows the basic hardware connection required between the host programmer and the target device.
Host
Programmer PSoC 40xx
VDD VDDD
SWDCK
XRES
SWDIO
GND
SWDCK ( P3[1]] )
XRES(1)
SWDIO ( P3[0] )
GND
VSSD
1.8 V –5.5 V
0.1 uF
Host
Programmer PSoC 4xxx/
PSoC 4xxxM/
PSoC 4xxxL/PSoC 40xxS/PSoC
41xxS/ PSoC 4100PS/ PSoC
4100S Plus
VDD VDDD
SWDCK
XRES
SWDIO
GND
SWDCK ( P3[3]] )
XRES
SWDIO ( P3[2] )
VDD
GND
VSSD
1.8 V –5.5 V
0.1 uF
Host
Programmer PSoC 4xx7_BLE/ PSoC 4xx8_BLE
VDD VDDD
SWDCK
XRES
SWDIO
GND
SWDCK ( P0[7] )
XRES
SWDIO ( P0[6] )
VDD
GND
VSSD
1.8 V –5.5 V
0.1 uF
(1) Toggle VDDD pin for devices
that do not have an XRES pin
Figure 3 Basic Host/Target Connections

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Porting the HSSP Application to a Host Programmer
4Porting the HSSP Application to a Host Programmer
The project A_Hssp_Programmer, provided with this application note, uses PSoC 5LP as the host programmer
for the target device. In the HSSP application, the host programmer can be any other microcontroller. This
section explains the changes required to port the HSSP application code to the specific host used to program
the target device.
4.1 Files That Must Be Ported
The PSoC 5LP host programmer-based project includes files specific to PSoC 5LP. While porting the HSSP
application code to any other host programmer, you must port only the files listed:
Table 7 Files That Must Be Ported
Header Files to Be Ported
Source Files to Be Ported
SWD_PhysicalLayer.h
SWD_PhysicalLayer.c
SWD_PacketLayer.h
SWD_PacketLayer.c
SWD_UpperPacketLayer.h
SWD_UpperPacketLayer.c
Timeout.h
Timeout.c
HexImage.h
HexImage.c
DataFetch.h
DataFetch.c
ProgrammingSteps.h
ProgrammingSteps.c
RegisterDefines.h
4.2 Code Changes Required While Porting
Make the following changes to each of the files while porting the attached HSSP application code to any host
programmer other than PSoC 5LP. Note that only some files need to be modified while porting.
•RegisterDefines.h: Modify the definitions in this header file for the port numbers, pin numbers, mask values,
output registers, input registers, and drive mode registers according to the host programmer used.
•SWD_PhysicalLayer.h: All the bit-banging macros defined in this header file are used in the function
definitions in the SWD_PhysicalLayer.c file. Modify these macros according to the host programmer used.
•SWD_PhysicalLayer.c: Modify all the bit-banging functions defined in this file according to the host
programmer used.
•Timeout.h: Modify the three timeout parameter definitions described according to the host programmer
used.
Table 8 Timing Parameters
S.No.
Timing Parameter
1
XRES_PULSE_100US
2
DEVICE_ACQUIRE_TIMEOUT
3
SROM_POLLING_TIMEOUT
To learn how to calculate the timeout parameters for a specific host programmer, see Calculating HSSP
Timeout Parameters.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Porting the HSSP Application to a Host Programmer
•HexImage.c, HexImage.h: These files contain the data to be programmed into the target device, defined as
an array of constants. For the PSoC 5LP host programmer, the data to be programmed is stored in the flash
memory of the host PSoC 5LP.
Some host programmers may lack the capacity to store the programming data in their on-chip memory.
Instead, they can use a communication interface, such as USB, SPI, or UART, to get the programming data. In
such a case, remove these files.
•DataFetch.c: The definitions for the functions should be modified based on the method used to get the
programming data.
See Interface for Receiving HSSP Programming Data for information on modifying the HSSP source code
according to the method used to get the programming data.
•main.c: The APIs for the character LCD and Pin_Start pin in the main.c file are specific to a PSoC 5LP host
programmer. Therefore, you should either remove them or modify them while porting to any other host
programmer.
In the above specified files, the following comments precede the code that needs to be modified based on the
host programmer. This helps you identify the code to be modified.
/******USER ATTENTION REQUIRED******/
/******HOST PROCESSOR SPECIFIC******/

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Calculating HSSP Timeout Parameters
5Calculating HSSP Timeout Parameters
Modify the values of the timeout parameters defined in the Timeout.h file according to the host programmer
used.
A separate test project, “C_Hssp_TimeoutCalc,” is provided with the application note. This project illustrates
the procedure to calculate the timeout parameters for a PSoC 5LP host programmer. Create a similar test
project for any other host programmer to calculate those timeout values.
The test project provides test functions in two files: TimeoutCalc.h andTimeoutCalc.c. These test functions
toggle a test pin during code execution. The timeout parameters are measured by measuring the LOW pulse
width of the signal on the test pin using an oscilloscope.
To calculate these timeout parameters, see the explanation in the macro definitions in the TimeoutCalc.h
header file of the project. Now look at the significance of each of these timeout values:
5.1 DEVICE_ACQUIRE_TIMEOUT
This macro is used in the function DeviceAcquire()in the ProgrammingSteps.c file. To program the device,
the device must be acquired within the maximum time window for acquiring the device after you do a device
reset using the XRES pin. Maximum time window for acquiring the device is defined:
Table 9 Timeout for Acquiring Device
Device Family
Timeout (ms)1
PSoC40xx
2.0
PSoC41/42xx
1.5
PSoC4xxxM
2.0
PSoC 4xxxL
2.0
PSoC4xx7_BLE / PSoC4xx8_BLE
2.0
PSoC 4000S/ PSoC 4100S/ PSoC 4100PS
2.0
PSoC 4100S Plus
5.0
Note: The recommended minimum frequency of the SWDCK clock, which meets the timing requirement
to acquire the device, is 1.5 MHz. See the “Step 1. Acquire Chip” subsection of the programming
specifications document of the respective device listed in the Related Documentation section for
more details.
The device-acquiring sequence consists of two steps:
1. Do a line Reset, which is a standard ARM command to reset the debug access port (DAP).
2. Read the DAP.
DEVICE_ACQUIRE_TIMEOUT indicates the maximum number of times a host can send the device-acquiring
sequence in a specific time window after device reset as given in Table 9.
To calculate this macro, uncomment the TestModeTimeout() function in the main.c file of the project, and
then program the device.
1
The timeout for acquiring the device in the case of Power Cycle mode programming must be longer, ~ 30 ms.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Calculating HSSP Timeout Parameters
Measure the LOW pulse width on the test pin for one iteration of the device-acquiring sequence by using an
oscilloscope. Then, calculate this macro as follows:
DEVICE_ACQUIRE_TIMEOUT = (X ms/low pulse width), where X is the maximum time window for acquiring the
device as defined in Table 9.
Code Listing 1 Calculating DEVICE_ACQUIRE_TIMEOUT Parameter
Unsignedshort timestamp = 0;
Unsignedlongchip_DAP_Id = 0;
/* Make the pin LOW before sending SWD clock train */
TESTPIN_OUTPUT_LOW;
for(timestamp = 0; timestamp < 1; timestamp++)
{
Swd_LineReset();
Read_DAP(DPACC_DP_IDCODE_READ, &chip_DAP_Id);
}
/* Make the pin HIGH after sending SWD clock train */
TESTPIN_OUTPUT_HIGH;
5.2 SROM_POLLING_TIMEOUT
This macro is used in the SROM polling operations during HSSP programming. It is used while polling the result
of the nonvolatile memory read and write operations through SROM requests in the target device.
When the host requests a SROM system call through the SWD interface, it waits a maximum of one second while
reading the CPUSS_SYSREQ register for status. If a response is not received, the host aborts the HSSP
operation.
SROM_POLLING_TIMEOUT indicates the maximum number of times the CPUSS_SYSREQ register can be read in
a time window of one second.
To calculate this macro, uncomment the TestSromPollingTimeout() function in the main.c file of the
project, and then program the device.
Measure the LOW pulse width on the test pin after sending 10 iterations of the SROM polling sequence by using
an oscilloscope. Then calculate the macro as follows:
SROM_POLLING_TIMEOUT = (1 s/LOW pulse width)*10
Code Listing 2 Calculating the SROM_POLLING_TIMEOUT Parameter
Unsignedshort timestamp = 0;
UnsignedlongstatusCode = 0;
/* Make the pin low before sending SWD clock train */

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Calculating HSSP Timeout Parameters
TESTPIN_OUTPUT_LOW;
for(timestamp = 0; timestamp < 10; timestamp++)
{
Read_IO (CPUSS_SYSREQ, &statusCode);
/*performing SROM_SYSREQ_BIT | SROM_PRIVILEGED_BIT */
statusCode &= (SROM_SYSREQ_BIT | SROM_PRIVILEGED_BIT);
}
/* Make the pin high after sending SWD clock train */
TESTPIN_OUTPUT_HIGH;
This macro signifies the number of times CPUSS_SYSREQ can be read and checked if SROM_SYSREQ_BIT and
SROM_PRIVILEGED_BIT are set to 0 in a 1-second interval.
5.3 XRES_PULSE_100US
To reset the target device, the host generates an active LOW signal with a minimum pulse width of 5 µs on the
XRES line. In the HSSP code, a pulse width of 100 µs is generated on the XRES pin.
The function TestDelayHundredUs() is defined in the TimeoutCalc.c file.
In the C_Hssp_TimeoutCalc project provided with the application note, this function is implemented using the
CyDelayUs() API. Uncomment the line in TimeoutCalc.h to implement this function using microcontrollers
other than PSoC as host programmer.
#define XRES_PULSE_100US 600
Modify the code in TestDelayHundredUs() defined in the TimeoutCalc.c as given in code 3.
To calculate this macro, uncomment the TestDelayHundredUs() function in the main.c file of the project,
and then program the device. Measure the pulse width of the test pin on an oscilloscope.
Code Listing 3 Delay Routine
unsignedshort timestamp;
/* Make the pin low before start of the delay */
TESTPIN_OUTPUT_LOW;
/* For loop to introduce the 100 us delay
for(timestamp = 0; timestamp < XRES_PULSE_100US; timestamp++)
{

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Calculating HSSP Timeout Parameters
/* Do Nothing */
}
/* Make the pin high after end of the delay */
TESTPIN_OUTPUT_HIGH;
The A_HSSP_Programmer and B_HSSP_Pioneer projects implement a 100-µs delay using the CyDelayUs ()
API. For microcontrollers other than PSoC as the host programmer, the XRES_PULSE_100US parameter has
to be defined in Timeout.h and the delay should be implemented using this parameter in the
DelayHundredUs function of Timeout.c.
For power cycle mode programming, this delay routine signifies the time for which the device power rails are
OFF. For power cycle mode programming, there are no requirements for this pulse width. The recommendation
is to have a 1-ms delay before turning ON the power rails.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Interface for Receiving HSSP Programming Data
6Interface for Receiving HSSP Programming Data
The files DataFetch.c and DataFetch.h contain the functions to fetch the data to be programmed into the target
device.
In the example project, the programming data is stored in the on-chip flash memory of the PSoC 5LP host
programmer in the files HexImage.c and HexImage.h. The data fetch routines access this data from the
PSoC 5LP flash memory to perform HSSP.
However, not all host programmers may have the on-chip memory to store the HSSP programming data. When
that is the case, the programmer can use a communication interface (such as SPI, USB, or UART) to get the
programming data. Also, all the function definitions in the DataFetch.c file should be modified appropriately.
The following example is a reference that shows the modifications required for the Hex_ReadRowData()
function. You can perform similar modifications for other functions as well.
Original Code
Code Listing 4 Original Code to Get Flash Data
void HEX_ReadRowData(unsignedshortrowCount, unsignedchar * rowData)
{
/* Maximum value of 'i' can be 256 */
unsignedshort i;
for(i = 0; i<BYTES_PER_FLASH_ROW; i++)
{
rowData[i] = FlashData_HexFile[rowCount][i];
}
}
Modified Code
If the programming data is received through a communication interface, then the modified code should be
similar to the following one.
Code Listing 5 Modified Code to Get Flash Data
void HEX_ReadRowData(unsignedshortrowCount, unsignedchar * rowData)
{
/* Maximum value of 'i' can be 256 */
unsignedshort i;
/* ADD WAITING CODE HERE FOR THE UART BUFFER TO GET THE FLASH DATA */

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Interface for Receiving HSSP Programming Data
for(i = 0; i<BYTES_PER_FLASH_ROW; i++)
{
rowData[i] = /* PLACE THE UART BUFFER ARRAY HERE */
}
}

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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Timing Validation
7HSSP Timing Validation
The host programmer must meet the timing specifications for the target device programming to achieve a
robust HSSP implementation. Those specifications are given in “Appendix D. Timing Specifications of the SWD
Interface” of the programming specifications document of the respective device listed in the Related
Documentation section.
The host programmer must meet the timing parameters specified for the SWD interface and programming
mode entry. To validate the timing, capture the SWDIO, SWDCK, and XRES signals on an oscilloscope. For power
cycle mode programming, the device power rails should be monitored instead of the XRES pin. Using the
captured waveforms, you can verify the timing parameters against the corresponding values provided in the
programming specification.

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PSoC 4 Programming Using an External Microcontroller (HSSP)
Power Cycle Mode Programming
8Power Cycle Mode Programming
Device programming starts with a device reset to acquire the device and enter programming mode. The
recommended method of resetting the device from the host side is to toggle the device XRES pin. But some
lower pin count devices in the PSoC 4000 family do not have an XRES pin, and the host has to toggle the device
Vdd pin to reset the device (power cycle mode). All the projects provided with the application note work using
the XRES programming mode because the PSoC 5LP host processor on the development kit does not have the
hardware connections to toggle the power supply of the target PSoC 4 device. So, when porting the projects to
your host processor and adding power cycle mode support, the following changes and considerations need to
be made in the project.
1. The DEVICE_ACQUIRE_TIMEOUT value, discussed in the section DEVICE_ACQUIRE_TIMEOUT, has to be
modified to reflect the much longer 30-ms timeout window required for power cycle mode programming.
So, for example, if the DEVICE_ACQUIRE_TIMEOUT define has been calculated to be 20 for a 2 ms XRES
mode acquire timing, then that define should be changed to 300 for a 30 ms power cycle mode acquire
timing.
2. The function definitions related to toggling of the XRES pin on the host side should be modified as
appropriate to toggle the device power rails. These functions are - SetXresHigh(),SetXresLow().
3. If an I/O pin of the host processor is used to power the PSoC 4 device directly to toggle the power from the
host side, ensure that the I/O pin can source the current required for device operation as specified in the
respective PSoC 4 device datasheet. If the I/O pin is not able to source the required current, the output
voltage (VOH) typically decreases, and can potentially go even below the minimum PSoC 4 device operating
voltage. This can cause programming failures. Such a voltage droop scenario can be identified by observing
the power rail voltages on the oscilloscope.