Intel PCH-LP Operating instructions

Document Number:
Broadwell Platform Controller Hub-
Low Power (PCH-LP)
SPI Programming Guide
June 2014
Revision 1.0
Intel Confidential

Intel Confidential 2
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Intel Confidential 3
ContentsContents
1 Introduction............................................................................................................9
1.1 Overview ...........................................................................................................9
1.2 Terminology .....................................................................................................10
1.3 Reference Documents........................................................................................10
2 PCH SPI Flash Architecture................................................................................11
2.1 Descriptor Mode................................................................................................11
2.2 Serial Flash Discoverable Parameter (SFDP)..........................................................11
2.3 SPI Fast Read...................................................................................................11
2.4 Intel®TPM on SPI Bus.......................................................................................11
2.5 Boot Destination Option .....................................................................................11
2.5.1 Boot Flow for Broadwell PCH-LP Family......................................................11
2.6 Flash Regions ...................................................................................................12
2.6.1 Flash Region Sizes..................................................................................12
2.7 Hardware vs. Software Sequencing......................................................................13
3 PCH SPI Flash Compatibility Requirement.......................................................15
3.1 Intel®microarchitecture code name Broadwell PCH-LP SPI Flash Requirements ......... 15
3.1.1 SPI-based BIOS Requirements.................................................................15
3.1.2 Integrated LAN Firmware SPI Flash Requirements.......................................16
3.1.2.1 SPI Flash Unlocking Requirements for Integrated LAN....................16
3.1.3 Intel®Management Engine Firmware (Intel®ME FW) SPI Flash Requirements 16
3.1.4 SFDP....................................................................................................17
3.1.5 JEDEC ID (Opcode 9Fh) ..........................................................................17
3.1.6 Multiple Page Write Usage Model..............................................................17
3.1.7 Hardware Sequencing Requirements.........................................................18
3.2 Broadwell PCH-LP SPI AC Electrical Compatibility Guidelines....................................19
3.3 SPI Flash DC Electrical Compatibility Guidelines.....................................................21
4 Descriptor Overview............................................................................................23
4.1 Flash Descriptor Content ....................................................................................24
4.1.1 Descriptor Signature and Map .................................................................. 24
4.1.1.1 FLVALSIG - Flash Valid Signature
(Flash Descriptor Records)24
4.1.1.2 FLMAP0 - Flash Map 0 Register
(Flash Descriptor Records)25
4.1.1.3 FLMAP1—Flash Map 1 Register
(Flash Descriptor Records)25
4.1.1.4 FLMAP2—Flash Map 2 Register
(Flash Descriptor Records)26
4.1.2 Flash Descriptor Component Section.........................................................26
4.1.2.1 FLCOMP—Flash Components Register
(Flash Descriptor Records)26
4.1.2.2 FLILL—Flash Invalid Instructions Register
(Flash Descriptor Records)28
4.1.2.3 FLILL1—Flash Invalid Instructions Register
(Flash Descriptor Records)28
4.1.3 Flash Descriptor Region Section ...............................................................29
4.1.3.1 FLREG0—Flash Region 0 (Flash Descriptor) Register ..........................
(Flash Descriptor Records)29
4.1.3.2 FLREG1—Flash Region 1 (BIOS) Register
(Flash Descriptor Records)29

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4.1.3.3 FLREG2—Flash Region 2 (Intel® ME) Register
(Flash Descriptor Records)..........................................................30
4.1.3.4 FLREG3—Flash Region 3 (GbE) Register
(Flash Descriptor Records)30
4.1.3.5 FLREG4—Flash Region 4 (Platform Data) Register
(Flash Descriptor Records)30
4.1.4 Flash Descriptor Master Section................................................................31
4.1.4.1 FLMSTR1—Flash Master 1 (Host CPU/ BIOS)
(Flash Descriptor Records)31
4.1.4.2 FLMSTR2—Flash Master 2 (Intel®ME)
(Flash Descriptor Records)31
4.1.4.3 FLMSTR3—Flash Master 3 (GbE)
(Flash Descriptor Records)31
4.1.5 PCH Softstraps.......................................................................................32
4.1.6 Descriptor Upper Map Section...................................................................32
4.1.6.1 FLUMAP1—Flash Upper Map 1
(Flash Descriptor Records)32
4.1.7 Intel®ME Vendor Specific Component Capabilities Table..............................32
4.1.7.1 JID0—JEDEC-ID 0 Register
(Flash Descriptor Records)..........................................................32
4.1.7.2 VSCC0—Vendor Specific Component Capabilities 0
(Flash Descriptor Records)32
4.1.7.3 JIDn—JEDEC-ID Register n
(Flash Descriptor Records)33
4.1.7.4 VSCCn—Vendor Specific Component Capabilities n
(Flash Descriptor Records)35
4.2 OEM Section .....................................................................................................36
4.3 Region Access Control ........................................................................................36
4.3.1 Intel Recommended Permissions for Region Access .....................................37
4.3.2 Overriding Region Access.........................................................................37
4.4 Intel®ME Vendor-Specific Component Capabilities (Intel®ME VSCC) Table...............38
4.4.1 How to Set a JEDEC ID Portion of Intel®ME VSCC Table Entry......................38
4.4.2 How to Set a VSCC Entry in
Intel®ME VSCC Table for Broadwell PCH-LP Platforms38
4.4.3 Intel®ME VSCC Table Settings for Broadwell PCH-LP Family Systems............40
5 Serial Flash Discoverable Parameter (SFDP) Overview..................................41
5.1 Introduction......................................................................................................41
5.2 Discoverable Parameter Opcode and Flash Cycle ....................................................41
5.3 Parameter Table Supported on PCH......................................................................42
5.4 Detail JEDEC Specification...................................................................................42
6 Configuring BIOS/GbE for SPI Flash Access ...................................................43
6.1 Unlocking SPI Flash Device Protection for Broadwell PCH-LP Platform........................43
6.2 Locking SPI Flash via Status Register ...................................................................44
6.3 SPI Protected Range Register Recommendations....................................................44
6.4 Software Sequencing Opcode Recommendations....................................................44
6.5 Recommendations for Flash Configuration
Lockdown and Vendor Component Lock Bits45
6.5.1 Flash Configuration Lockdown ..................................................................45
6.5.2 Vendor Component Lock..........................................................................45
6.6 Host Vendor Specific Component Control
Registers (VSCC)45
6.7 Host VSCC Register Settings ...............................................................................50
7 Flash Image Tool..................................................................................................51
7.1 Flash Image Details ...........................................................................................51
7.1.1 Flash Space Allocation.............................................................................52

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7.2 Modifying the Flash Descriptor Region..................................................................52
7.2.1 Setting the Number and Size of the Flash Components................................52
7.2.1.1 Region Access Control ...............................................................55
7.3 PCH Soft Straps ................................................................................................56
7.4 Management Engine VSCC Table .........................................................................56
7.4.1 Adding a New Table Entry........................................................................56
7.4.2 Removing an Existing Table Entry.............................................................57
8 Flash Programming Tool ....................................................................................59
8.1 BIOS Support ...................................................................................................59
8.2 Fparts.txt File ...................................................................................................59
8.3 Configuring a Fparts.txt Entry .............................................................................60
8.3.1 Display Name ........................................................................................60
8.3.2 Device ID..............................................................................................60
8.3.3 Device Size (in Bits) ...............................................................................60
8.3.4 Block Erase Size (in Bytes - 256B, 4K, 64K)...............................................61
8.3.5 Block Erase Command ............................................................................61
8.3.6 Write Granularity (1 or 64)......................................................................61
8.3.7 Enable Write Status /Unused ...................................................................61
8.3.8 Chip Erase Command..............................................................................61
9 SPI Flash Programming Procedures.................................................................63
9.1 Updating BIOS..................................................................................................63
9.1.1 Example of SPI flash programming...........................................................63
10 Intel®ME Disable for Debug/Flash Burning Purposes ...................................65
10.1 Intel®ME Disable..............................................................................................65
10.1.1 Erasing/Programming Intel®ME Region ....................................................65
11 Recommendations for SPI Flash Programming in Manufacturing
Environments67
12 FAQ and Troubleshooting ..................................................................................69
12.1 FAQ.................................................................................................................69
12.2 Troubleshooting ................................................................................................71
A APPENDIX A - Descriptor Configuration ..........................................................73
A.1 Flash Descriptor PCH Soft Strap Section ...............................................................73
A.2 PCHSTRP0—Strap 0 Record (Flash Descriptor Records)...........................................74
A.3 PCHSTRP1—Strap 1 Record (Flash Descriptor Records)...........................................76
A.4 PCHSTRP2—Strap 2 Record (Flash Descriptor Records)...........................................77
A.5 PCHSTRP3—Strap 3 Record (Flash Descriptor Records)...........................................78
A.6 PCHSTRP4—Strap 4 Record (Flash Descriptor Records)...........................................78
A.7 PCHSTRP5—Strap 5 Record (Flash Descriptor Records)...........................................80
A.8 PCHSTRP6—Strap 6 Record (Flash Descriptor Records)...........................................80
A.9 PCHSTRP7—Strap 7 Record (Flash Descriptor Records)...........................................80
A.10 PCHSTRP8—Strap 8 Record (Flash Descriptor Records)...........................................80
A.11 PCHSTRP9—Strap 9 Record (Flash Descriptor Records)...........................................81
A.12 PCHSTRP10—Strap 10 Record (Flash Descriptor Records) .......................................83
A.13 PCHSTRP11—Strap 11 Record (Flash Descriptor Records) .......................................84
A.14 PCHSTRP12—Strap 12 Record (Flash Descriptor Records) .......................................85
A.15 PCHSTRP13—Strap 13 Record (Flash Descriptor Records) .......................................85
A.16 PCHSTRP14—Strap 14 Record (Flash Descriptor Records) .......................................85
A.17 PCHSTRP15—Strap 15 Record (Flash Descriptor Records) .......................................87
A.18 PCHSTRP16—Strap 16 Record (Flash Descriptor Records) .......................................88
A.19 PCHSTRP17—Strap 17 Record (Flash Descriptor Records) .......................................88
A.20 PCHSTRP18—Strap 18 Record (Flash Descriptor Records) .......................................88
A.21 PCHSTRP19—Strap 19 Record (Flash Descriptor Records) .......................................89

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A.22 PCHSTRP20—Strap 20 Record (Flash Descriptor Records)........................................89
A.23 CPUSTRP0—Strap 0 Record (Flash Descriptor Records) ...........................................90
Figures
3-1 SPI Timing.........................................................................................................20
3-2 PCH Test Load....................................................................................................21
4-1 Flash Descriptor (Broadwell PCH-LP)......................................................................23
5-1 SFDP Read Instruction Sequence...........................................................................41
7-1 Firmware Image Components...............................................................................51
7-2 Editable Flash Image Region List...........................................................................53
7-3 Descriptor Region – Descriptor Map Options ...........................................................53
7-4 Descriptor Region – Fast Read Support Options.......................................................54
7-5 Descriptor Region - Component Section Options......................................................54
7-6 Region Access Control .........................................................................................55
7-7 Descriptor Region – Master Access Section Options..................................................55
7-8 Add New VSCC Table Entry ..................................................................................56
7-9 Add VSCC Table Entry .........................................................................................56
7-10 VSCC Table Entry................................................................................................57
7-11 Remove VSCC Table Entry....................................................................................57
Tables
1-1 Terminology .......................................................................................................10
1-2 Reference Documents..........................................................................................10
2-1 Region Size vs. Erase Granularity of Flash Components ............................................13
3-1 SPI Timings (20 MHz)..........................................................................................19
3-2 SPI Timings (33 MHz)..........................................................................................19
3-3 SPI Timings (50 MHz)..........................................................................................20
4-1 Region Access Control Table Options......................................................................36
4-2 Recommended Read/Write Settings for Platforms Using Intel® ME Firmware...............37
4-3 Recommended Read/Write Settings for Platforms Using Intel® ME Firmware (Cont’d) ..37
4-4 Jidn - JEDEC ID Portion of Intel® ME VSCC Table ....................................................38
4-5 Vsccn – Vendor-Specific Component Capabilities Portion of the Broadwell PCH-LP Platforms
39
6-1 Recommended Opcodes for FPT Operation..............................................................45
6-2 Recommended Opcodes for FPT Operation..............................................................45
6-3 VSCC0 - Vendor-Specific Component Capabilities Register for SPI Component 0 ..........46
6-4 VSCC1 - Vendor Specific Component Capabilities Register for SPI Component 1...........48
6-5 Description of How WSR and WEWS is Used............................................................49

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ContentsRevision History
§ §
Document
Number Revision Number Description Date
523462
0.5 Initial release of document. April 2013
0.7 Added section 4.1.2.3 for flash invalid instructions 4-7. August 2013
0.9 Updated section 6.4 table 6-1 and table 6-2. Sept 2013
1.0 Added Strap 14 bit 30 configuration information. June 2014

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Introduction
1Introduction
1.1 Overview
This manual is intended for OEMs and software vendors to clarify various aspects of
programming the SPI flash on PCH family based platforms. The current scope of this
document is for Intel®microarchitecture code name Broadwell PCH-LP only.
Chapter 2, “PCH SPI Flash Architecture”
Overview of SPI flash, Non-Descriptor vs. Descriptor, Flash Layout, compatible SPI
flash.
Chapter 3, “PCH SPI Flash Compatibility Requirement”
Overview of compatibility requirements for BroadwellPCH‐LPproducts.
Chapter 4, “Descriptor Overview”
Overview of the descriptor and Descriptor record definition
Chapter 5, “Serial Flash Discoverable Parameter (SFDP) Overview”
Overview of the SFDP definition.
Chapter 6, “Configuring BIOS/GbE for SPI Flash Access”
Describes how to configure BIOS/GbE for SPI flash access.
Chapter 7, “Flash Image Tool”
This tool creates a descriptor and combines the GBE, BIOS, Platform Data Region and
Intel®Management Engine Firmware (Intel®ME FW) into one image.
Chapter 8, “Flash Programming Tool”
This tool programs the SPI flash device on the Broadwell PCH-LP platforms. This section
will talk about requirements needed for FPT to work.
Chapter 9, “SPI Flash Programming Procedures”
Guide on how to program the SPI flash on the Intel CRB and PCH based platforms.
Chapter 10, “Intel®ME Disable for Debug/Flash Burning Purposes”
Methods of disabling Intel Management Engine for debug purposes.
Chapter 11, “Recommendations for SPI Flash Programming in Manufacturing
Environments”
Recommendations for manufacturing environments.
Chapter 12, “FAQ and Troubleshooting”
Frequently asked questions and Troubleshooting tips.

Introduction
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1.2 Terminology
1.3 Reference Documents
§ §
Table 1-1. Terminology
Term Description
BIOS Basic Input-Output System
CRB Customer Reference Board
FPT Flash Programming Tool - programs the SPI flash
FIT Flash Image Tool – creates a flash image from separate binaries
FW Firmware
FWH Firmware Hub – LPC based flash where BIOS may reside
Intel®AMT Intel®Active Management Technology
GbE Intel Integrated 1000/100/10
HDCP High-bandwidth Digital Content Protection
Broadwell PCH-LP Broadwell Platform Integrated I/O
Intel®Management Engine
Firmware (Intel®ME FW) Intel firmware that adds Intel®Active Management Technology, Braidwood Technology, Intel Anti-Theft Technology, Corwin Springs, Castle Peak, Sentry
Peak, etc.
Intel PCH Intel Platform Controller Hub
Intel PCHn family All PCHn derivatives including PCHn (desktop) and PCHnM (mobile)
LPC Low Pin Count Bus- bus on where legacy devices such a FWH reside
PCH–LP Platform Controller Hub – Low Power
SPI Serial Peripheral Interface – refers to serial flash memory in this document
VSCC Vendor Specific Component Capabilities
LVSCC Lower Vendor Specific Component Capabilities
UVSCC Upper Vendor Specific Component Capabilities
SFDP Serial Flash Discoverable Parameter
Table 1-2. Reference Documents
Document Document # / Location
Broadwell PCH-LP (Wildcat Point-LP)
External Design Specification (EDS) Contact your Intel field representative.
Intel Flash Image Tool (FIT) \System Tools\Flash Image Tool of latest Intel®ME kit from VIP.
The Kit MUST match the platform you intend to use the flash tools
for.
Intel Flash Programming Tool (FPT) \System Tools\Flash Programming Tool of latest Intel®ME from
VIP. The Kit MUST match the platform you intend to use the flash
tools for.
FW Bring Up Guide Root directory of latest Intel®Management Engine kit from VIP.
The Kit MUST match the platform you intend to use the flash tools
for.

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PCH SPI Flash Architecture
2 PCH SPI Flash Architecture
PCH SPI interface consists of clock (CLK), MOSI (Master Out Slave In) MISO (Master In
Slave Out),IO2, IO3 (For Quad Fast Read and Quad I/O support) and up to 3 active low
chip selects (CSX#) on Intel®microarchitecture code name Broadwell PCH-LP. Chip
Select 3 (CS3#) is dedicated for Intel TPM on SPI usage.
Broadwell PCH-LP Family can support SPI flash devices up to 64 Bytes per chip select
and frequencies of 20 MHz, 33 MHz, and 50 MHz.
2.1 Descriptor Mode
Descriptor mode supports up to two SPI flashes. It allows integrated LAN support, as
well as Intel®ME firmware to share flash. There is also additional security for reads and
writes to the flash. Hardware sequencing, heterogeneous flash space, Intel integrated
LAN, Intel®ME firmware on SPI flash, require descriptor mode. Descriptor mode
requires the SPI flash to be hooked up directly to the PCH’s SPI bus.
See SPI Supported Feature Overview of the latest Intel Platform Controller Hub
Family External Design Specification (EDS) for Broadwell PCH-LP (Wildcat Point-LP)
Family for more detailed information.
2.2 Serial Flash Discoverable Parameter (SFDP)
Broadwell PCH-LP supports SPI with SFDP. SFDP (Serial Flash Discoverable Parameter)
is a JEDEC standard provides a consistent method of describing the functional and
feature capabilities of SPI devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by PCH to enable adjustment needed to
accommodate divergent feature from multiple vendors.
Please refer to Chapter 5, “Serial Flash Discoverable Parameter (SFDP) Overview” for
more information.
2.3 SPI Fast Read
Broadwell PCH-LP Family supports SPI Dual output, Dual I/O, Quad output and
Quad I/O Fast read instruction with frequencies 20, 33, and 50 MHz.
Note: 50-MHz support requires SPI component that meet 66-MHz timing.
2.4 Intel®TPM on SPI Bus
Broadwell PCH-LP Family supports Intel TPM on the SPI bus. Intel TPM attached to the
system may be using LPC or SPI. SPI Intel TPM is accessed much like direct reads and
direct writes.
2.5 Boot Destination Option
2.5.1 Boot Flow for Broadwell PCH-LP Family
When booting from Global Reset, the PCH SPI controller will check whether the SPI
component is supporting SFDP by sending 5Ah to SPI to CS0 first then CS1. SFDP
fetching will triggered when assertion of MEPWROK. If the SPI has a valid SFDP, the
controller supports auto discovery of the Component Property Parameter Table (CPPT)

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PCH SPI Flash Architecture
which is having CPPT set to 1. CPPT is located at VSCC0 (for SPI 0) and VSCC1 (for SPI
1). Next, the SPI controller will look for a descriptor signature on the SPI flash device
on Chip Select 0 at address 0x10. If the signature is present and valid, then the PCH
controller will boot in Descriptor mode. It will load up the descriptor into corresponding
registers in the PCH. If the signature is NOT present the PCH will boot in non descriptor
mode where integrated LAN and all Intel Management Engine Firmware will be
disabled. Even if the PCH boot in non descriptor mode, SFDP parameters are available
for software use. Whether there is a valid descriptor or not, the PCH will look to the
BIOS boot straps to determine the location of BIOS for host boot.
See Boot BIOS strap in the Functional Straps of the latest Intel I/O Controller Hub
Family External Design Specification (EDS) for Broadwell PCH-LP Family for more
detailed information.
If LPC is chosen as the BIOS boot destination, then the PCH will fetch the reset vector
on top of the firmware hub flash device.
If SPI is chosen as the BIOS destination, it will either fetch the reset vector on top of
the SPI flash device on chip select 0, or if the PCH is in descriptor mode it will
determine the location of BIOS through the base address that is defined in the SPI flash
descriptor.
See 113H287HChapter 4, “Descriptor Overview” and for more detailed information.
2.6 Flash Regions
Flash Regions only exist in Descriptor mode. The controller can divide the SPI flash in
up to five separate regions.
The descriptor (Region 0) must be located in the first sector of component 0 (offset
0x10). Descriptor and Intel ME regions are required for all Broadwell PCH-LP Family
based platforms.
If Regions 0, 2, 3 or 4 are defined they must be on SPI. BIOS can be on either FWH or
SPI. The BIOS that will load on boot will be set by Boot BIOS destination straps.
Only three masters can access the five regions: Host CPU, integrated LAN, and
Intel ME.
2.6.1 Flash Region Sizes
SPI flash space requirements differ by platform and configuration. Please refer to
documentation specific to your platform for BIOS and ME Region flash size estimates.
The Flash Descriptor requires one block. GbE requires two separate blocks. The amount
of actual flash space consumed for the above regions are dependent on the erase
granularity of the flash part. Assuming 2 Mbyte BIOS, 64 Mb flash part is the target size
of flash for largest configuration. BIOS size will determine how small of a flash part can
be used for the platform.
Region Content
0Descriptor
1BIOS
2ME – Intel®Management Engine Firmware (Intel®ME FW)
3 GbE – Location for Integrated LAN firmware and MAC address
4 PDR – Platform Data Region

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PCH SPI Flash Architecture
2.7 Hardware vs. Software Sequencing
Hardware and software sequencing are the two methods the PCH uses communicates
with the flash via programming registers for each of the three masters.
When utilizing software sequencing, BIOS needs to program the OPTYPE and OPMENU
registers respectively with the opcode it needs. It also defines how the system should
use each opcode. If the system needs a new opcode that has not been defined, then
BIOS can overwrite the OPTYPE and OPMENU register and define new functionality as
long as the FLOCKDN bits have not been set.
FPT as well as some BIOS implementation support software sequencing. Note: FPT
defaults to hardware sequencing.
Hardware sequencing has a predefined list of opcodes with only the erase opcode being
programmable. This mode is only available if the descriptor is present and valid. Intel®
ME Firmware and Integrated LAN FW, and integrated LAN drivers all must use HW
sequencing, so BIOS must properly set up the PCH to account for this. The Host VSCC
registers and Intel Management Engine VSCC table have to be correctly configured for
BIOS, GbE and Intel®ME Firmware to have read/write access to SPI.
See Serial Peripheral Interface Memory Mapped Configuration Registers in
Broadwell PCH-LP Family External Design Specification (EDS) for more details.
Table 2-1. Region Size vs. Erase Granularity of Flash Components
Regions Size with uniform 4 KB blocks
Descriptor 4 KB
GbE 8 KB
Platform Data Region Varies by platform
BIOS Varies by platform
ME Varies by platform and configuration

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PCH SPI Flash Architecture

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PCH SPI Flash Compatibility Requirement
3 PCH SPI Flash Compatibility
Requirement
3.1 Intel®microarchitecture code name Broadwell
PCH-LP SPI Flash Requirements
• Broadwell PCH-LP Family allows for up to two SPI flash devices to store BIOS,
Intel®ME FW and security keys for Platform Data Region and integrated LAN
information.
—Intel
®ME FW is required for Broadwell PCH-LP Family-based
platforms!
— Each SPI component can support up to 64 MB (128 MB total addressable) using
26-bit addressing
• 3.3V SPI I/O buffer VCC
• SPI Fast Read instruction is supported and frequency of 20 MHz, 33 MHz and 50
MHz
— 50 MHz support requires component that meet 66Mhz timing
• SPI Dual Output and Dual I/O Fast Read instruction is supported with frequency of
20 MHz, 33M hz and 50 MHz
• SPI Quad Output and Quad I/O Fast read instruction is supported with frequency of
20 MHz, 33 MHz and 50 MHz
If there are two SPI components, both components have to support fast read in order
to enable Fast Read in PCH.
3.1.1 SPI-based BIOS Requirements
• Erase size capability of: 4 KBytes.
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh aliases to the top of the flash memory.
• SPI Compatible Mode 0 support: Clock phase is 0 and data is latched on the rising
edge of the clock.
• If the device receives a command that is not supported or incomplete (less than 8
bits), the device must discard the cycle gracefully without any impact on the flash
content.
• An erase command (page, sector, block, chip, etc.) must set all bits inside the
designated area (page, sector, block, chip, etc.) to 1 (Fh).
• Status Register bit 0 must be set to 1 when a write, erase or write to status register
is in progress and cleared to 0 when a write or erase is NOT in progress.
• Devices requiring the Write Enable command must automatically clear the Write
Enable Latch at the end of Data Program instructions.
• Byte write must be supported. The flexibility to perform a write between 1 byte to
64 bytes is recommended.
• SPI flash parts that do not meet Hardware sequencing command set requirements
may work in BIOS only platforms via software sequencing.

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3.1.2 Integrated LAN Firmware SPI Flash Requirements
A serial flash device that will be used for system BIOS and Integrated LAN or
Integrated LAN only must meet all the SPI Based BIOS Requirements plus:
Must support “Hardware Sequencing Requirements”.
4 KBytes erase capability must be supported.
3.1.2.1 SPI Flash Unlocking Requirements for Integrated LAN
BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE
region. GbE firmware and drivers for the integrated LAN need to be able to read, write
and erase the GbE region at all times.
3.1.3 Intel®Management Engine Firmware (Intel®ME FW) SPI
Flash Requirements
Intel Management Firmware must meet the SPI flash based BIOS Requirements plus:
3.1.4 SFDP
3.1.5 JEDEC ID (Opcode 9Fh)
3.1.6 Multiple Page Write Usage Model
3.1.7 Hardware Sequencing Requirements
Flash part must be uniform 4 KB erasable block throughout the entire part.
Write protection scheme must meet guidelines as defined in 317H SPI Flash Unlocking
Requirements for Intel Management Engine.
SPI Flash Unlocking Requirements for Intel Management Engine
Flash devices must be globally unlocked (read, write and erase access on the ME
region) from power on by writing 00h to the flash’s status register to disable write
protection.
If the status register must be unprotected, it must use the enable write status register
command 50h or write enable 06h.
Opcode 01h (write to status register) must then be used to write a single byte of 00h
into the status register. This must unlock the entire part. If the SPI flash’s status
register has non-volatile bits that must be written to, bits [5:2] of the flash’s status
register must be all 0h to indicate that the flash is unlocked.
If there is no need to execute a write enable on the status register, then opcodes 06h
and 50h must be ignored.
After global unlock, BIOS has the ability to lock down small sections of the flash as long
as they do not involve the ME or GbE region. See 318H6.1 Unlocking SPI Flash Device
Protection for Broadwell PCH-LP Platform and 320H321H6.2 Locking SPI Flash via Status Register
for more information about flash based write/erase protection.

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3.1.4 SFDP
Serial flash with SFDP have their supported capabilities and commands stored inside
the serial flash devices. The controller will discover the attributes needed to operate.
Please refer to JEDEC standard Serial Flash Discoverable Parameters in Standard
JESD216, for detail instruction and guideline. the document is available on the JEDEC
Website www.jedec.org.
3.1.5 JEDEC ID (Opcode 9Fh)
Since each serial flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV1
and is available on the JEDEC website: www.jedec.org.
3.1.6 Multiple Page Write Usage Model
Intel platforms have firmware usage models require that the serial flash device support
multiple writes to a page (minimum of 512 writes) without requiring a preceding erase
command. BIOS commonly uses capabilities such as counters that are used for error
logging and system boot progress logging. These counters are typically implemented
by using byte-writes to ‘increment’ the bits within a page that have been designated as
the counter. The Intel firmware usage models require the capability for multiple data
updates within any given page. These data updates occur via byte-writes without
executing a preceding erase to the given page. Both the BIOS and Intel Management
Engine firmware multiple page write usage models apply to sequential and non-
sequential data writes.
Flash parts must also support the writing of a single bytes 1024 times in a single 256
Byte page without erase. There will be 64 pages where this usage model will occur.
These 64 pages will be every 16 Kilo bytes.

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3.1.7 Hardware Sequencing Requirements
The following table contains a list of commands and the associated opcodes that a SPI-
based serial flash device must support in order to be compatible with hardware
sequencing.
Commands OPCODE Notes
Write to Status
Register 01h Writes a byte to SPI flash’s status register. Enable Write to Status Register command must be run prior to this
command
Program Data 02h Single byte or 64 byte write as determined by flash part
capabilities and software
Read Data 03h
Write Disable 04h
Read Status 05h Outputs contents of SPI flash’s status register
Write Enable 06h
Fast Read 0Bh
Enable Write to
Status Register 50h or 06h Enables a bit in the status register to allow an update to the status register
Erase Programmable/
Discoverable 4 Kbyte erase. Uses the value from SFDP (if available) else value from VSCCn Erase Opcode register value
Chip Erase C7h and/or 60
JEDEC ID 9Fh See Section 3.1.5 for more information
Dual Output Fast
Read 3Bh/ Discoverable Discoverable opcodes are obtained from each component’s SFDP table
Dual I/O Fast Read Discoverable Opcode is optained from each component’s SFDP table
Quad I/O Fast Read Discoverable Opcode is optained from each component’s SFDP table

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3.2 Broadwell PCH-LP SPI AC Electrical Compatibility
Guidelines
Notes:
1.Typical clock frequency driven by Broadwell PCH-LP Family is 17.86 MHz.
2.Measurement point for low time and high time is taken at .5(VccME3_3).
Notes:
1.Typical clock frequency driven by Broadwell PCH-LP Family is 31.25 MHz.
2.Measurement point for low time and high time is taken at .5(VccME3_3).
Table 3-1. SPI Timings (20 MHz)
Sym Parameter Min Max Units Notes
t180a Serial Clock Frequency - 20MHz Operation 17.06 18.73 MHz 1
t183a Tco of SPI_MOSI with respect to serial clock falling
edge at the host -5 13 ns
t184a Setup of SPI_MISO with respect to serial clock falling
edge at the host 16 - ns
t185a Hold of SPI_MISO with respect to serial clock falling
edge at the host 0-ns
t186a Setup of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host 30 - ns
t187a Hold of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host 30 - ns
t188a SPI_CLK High time 26.37 - ns 2
t189a SPI_CLK Low time 26.82 - ns 2
Table 3-2. SPI Timings (33 MHz)
Sym Parameter Min Max Units Notes
t180b Serial Clock Frequency - 33 MHz Operation 29.83 32.81 MHz 1
t183b Tco of SPI_MOSI with respect to serial clock falling
edge at the host -5 5 ns
t184b Setup of SPI_MISO with respect to serial clock falling
edge at the host 8-ns
t185b Hold of SPI_MISO with respect to serial clock falling
edge at the host 0-ns
t186b Setup of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host 30 - ns
t187b Hold of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host 30 - ns
t188b SPI_CLK High time 14.88 - ns 2
t189b SPI_CLK Low time 15.18 - ns 2

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Notes:
1.Typical clock frequency driven by Broadwell PCH-LP Family is 50 MHz.
2.When using 50 MHz mode ensure target flash component can meet t188c and t189c specifications.
Recommended to use SPI flash component rated at 66 MHz or faster.
3.Measurement point for low time and high time is taken at .5(VccME3_3).
Table 3-3. SPI Timings (50 MHz)
Sym Parameter Min Max Units Notes
t180c Serial Clock Frequency - 50 MHz Operation 46.99 53.40 MHz 1
t183c Tco of SPI_MOSI with respect to serial clock falling edge at the host -3 3 ns
t184c Setup of SPI_MISO with respect to serial clock falling edge at the host 8 - ns
t185c Hold of SPI_MISO with respect to serial clock falling edge at the host 0 - ns
t186c Setup of SPI_CS[1:0]# assertion with respect to serial clock rising edge at the host 30 - ns
t187c Hold of SPI_CS[1:0]# assertion with respect to serial clock rising edge at the host 30 - ns
t188c SPI_CLK High time 7.84 - ns 2, 3
t189c SPI_CLK Low time 11.84 - ns 2, 3
Figure 3-1. SPI Timing
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS#
t186 t187
t184 t185
t183
t189t188