JVC XL-SV302SL User manual

SERVICE MANUAL
VIDEO CD PLAYER
Contents
Safety precautions ............................................................1-2
Preventing static electricity ...............................................1-3
Disassembly ......................................................................1-4
Description of major IC....................................................1-5
XL-SV302SL/SV305GD
XL-SV308BU
POWER 1–MICVOLUME –2 OPEN/CLOSE
RETURN
1 – MIC – 2
123 45
[phone]/0
ON / OFF
MIN MAX MIN MAX
COMPACT
DIGITAL VIDEO
VIDEO CD
IMPORTANT
PLEASE TAKE NOTE BEFORE ORDERING
1. Order all service parts thro gh JVC Asia Pte Ltd.- C stomer Satisfaction Dept.
2. Two orders are available: Initial order and last order (Before End Of Line)
3. Minim m order q antity: 100pcs
4. Delivery term: Minim m 2 months pon confirmation of order.
No: 28207
OCT. 2001
COPYRIGHT 

2001 VICTOR COMPANY OF JAPAN LTD.
XL-SV320SL/305GD/308BU

XL-SV320SL/SV305GD
XL-SV308BU
1-2
XL-SV320SL/305GD/308BU
1. This design of this product contains special hardware and many circuits and components specially for
safety purposes. For continued protection, no changes should be made to the original design unless
authorised in writing by the manufacturer. Replacement parts must be identical to those used in the
original circuits. Services should be performed by qualified personnel only.
2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the
product should not be made. Any design alterations or additions will void the manufacturer’s warranty
and will further relieve the manufacture of responsibility for personal injury or property damage resulting
therefrom.
3. Many electrical and mechanical parts in the products have special safety-related characteristics.
These characteristics are often not evident from visual inspection nor can the protection afforded by
them necessarily be obtained by using replacement components rated for higher voltage, the Parts
List of Service Manual. Electrical components having such features are identified by shading on the
schematics and by ( ) on the Parts List in the Service Manual. The use of a substitute replacement
which does not have the same safety characteristics as the recommended replacement parts shown
in the Parts List of Service Manual may create shock, fire, or other hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubing’s, barriers and the like to
be separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention
of electric shock and fire hazard. When service is required, the original lead routing and dress should
be observed, and it should be confirmed that they have been returned to normal, after re-assembling.
5. Leakage current check (Electrical Shock hazard testing)
After re-assembling the product, always perform an isolation check on the exposed metal parts of the
product (antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.)
to be sure the product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.
• Plug the AC line cord directly into the AC outlet. Using a “Leakage Current Tester”, measure the
leakage current from each exposed metal parts of the cabinet, particularly and exposed metal
part having a return path to the chassis, to a known good earth ground. Any leakage current must
not exceed 0.5mA AC (r.m.s.)
• Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per
volt or more sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a
Warning
1. This equipment has been designed and manufactured to meet international safety standards.
2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.
3. Repairs must be made in accordance with the relevant safety standards.
4. It is essential that safety critical components are replaced by approved parts.
5. If mains voltage selector is provided, check setting for local voltage.
0.15µF AC-type capacitor between an exposed
metal part and a known good earth ground.
Measure the AC voltage across the resistor
with the AC voltmeter.
Move the resistor connection to each exposed
metal part, particularly any exposed metal part
having a return path to the chassis, and
measure the AC voltage across the resistor.
Now, reverse the plug in the AC outlet and
repeat each measurement. voltage measured
Any must not exceed 0.75 V AC (r.m.s.). This
corresponds to 0.5 mA AC (r.m.s.).
Safety precautions
0.15µF AC TYPE
1500 10W
Place this
probe on
each exposed
metal part.
Good earth ground
AC Voltmeter
(Having 1000
ohms/volts,
or more sensitivity

XL-SV320SL/305GD/308BU
1-3
Preventing static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is dis-
charged, can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when
performing repairs.
1.1. Grounding to prevent damage by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as DVD players.
Be careful to use proper grounding in the area where repairs are being performed.
1.1.1. Ground the workbench
1. Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
1.1.2. Ground yourself
1. Use an anti-static wrist strap to release any static electricity built up in your body.
1.1.3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original
condition. (Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester’s internal
power source can easily destroy the laser diode.
1.2. Handling the traverse unit (optical pickup)
1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For spe-
cific details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the
traverse unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it.
Conductive material
(conductive sheet) or
iron plate
(caption)
Anti-static wrist strap

XL-SV320SL/SV305GD
XL-SV308BU
1-4
XL-SV320SL/305GD/308BU
Disassembly
Procedure of disassembly
No. Description QTY. Action Remark
1 Main part 1 Place
2 Plane tray 1 Remove Turn on VCD, open the plane tray
then take up the CD door.
3 Self screw 1 Loosen screw Loose the screw, remove from the upper cover.
4 ¢4.0 Self screw 4 Loosen screw
5 Upper cover 1 Remove Loose screws then remove the upper cover
from the main part.
6 Self screw 5 Loosen screw
7 Self screw 1 Loosen screw
8 Front panel block 1 Remove Remove the front panel block from the main part.

XL-SV320SL/305GD/308BU
1-5
IC lead identification, internal diagram and description
IC301: HT16512 (VFD DRIVER)
Block diagram
Pin configuration (Top view)

XL-SV320SL/SV305GD
XL-SV308BU
1-6
XL-SV320SL/305GD/308BU
Pin description
Symbol Pin Name Pin No. Description
DIN Data input 6 Inputs serial data at the rising edge of the shift clock, starting from
the low order bit.
DOUT Data output 5 Output serial data at the falling edge of the shift clock, starting from
the low order bit. This is the N-ch open-drain output pin.
STB Strobe 9 Initializes the serial interface at the rising or falling edge of the µPD16512.
It then waits for reception of a command. Data input after STB has fallen is
processed as a command. While command data is processed, current
processing is stopped, and the serial interface is initialized. While STB is
high, CLK is ignored.
CLK Clockinput 8 Reads serial data at the rising edge, and outputs data at the falling edge.
OSC Oscillator pin 44 Connect a resistor to this pin to determine the oscillation frequency to this pin.
Seg1/KS1 to High-voltage 15 to 20 Segment output pins (Dual function as key source)
Seg6/KS6 output
Seg7 to seg11 High-voltage 21 to 25 Segment output pins
output (segments)
Grid1 to Grid6 High-voltage 37 to 32 Grid output pins
output (grid)
Seg12/Grid11 to High-voltage 26,28 to 31 These pins are selectable for segment or grid driving.
Seg16/Grid7 output
(segment/grid)
Led to Led Led output 42 to 39 CMOS output. +20 mA max.
Key1 to Key4 Key data input 10 to 13 Data input to these pins is latched at the end of the display cycle.
SW1 to SW4 Switch input 1 to 4 These pins constitute a 4-bit general-purpose input port.
VDD Logic power 14, 38 5V ± 10%
Vss Logic ground 7, 43 Connect this pin to system GND.
VEE Pull-down level 27 VDD-35 V max.
IC201/IC202,U5/U6: BA4558 (OP-AMP)
Pin configuration
IC101: 7805 (REGULATOR)
Block diagram
Pin description
Pin Function
1 A Output
2 A-Input
3 A+Input
4V-
5 B+Input
6 B-Input
7 B Output
8V+

XL-SV320SL/305GD/308BU
1-7
Pin configuration
U1: ES3210
Block diagram
Pin configuration

XL-SV320SL/SV305GD
XL-SV308BU
1-8
XL-SV320SL/305GD/308BU
ES3210 Pin description
Name Number I/O Definition
VDD 1, 31, 51 I Voltage supply for 3.3V.
RAS# 2 O DRAM row address strobe (active low).
DWE# 3 O DRAM write enable (active low).
DA[8:0] 12:4 O DRAM multiplexed row and column address bus.
DBUS[15:0] 28:13 I/O DRAM data bus.
RESET# 29 I System rest (active low).
VSS 30,50,80,100 I Ground.
YUV[7:0] 39:32 O Y is luminance, UV are chrominance data bus for screen video interface.
YUV[7:0] for 8-bit YUV mode.
VSYNC 40 I/O Vertical sync for screen video interface. programmable for rising or falling edge.
HSYNC 41 I/O Horizontal sync for screen video interface, programmable for rising or falling edge.
CPUCLK 42 I RISC and system clock input. CPUCLK is used only if SEL-PLL[1:0]=00.
PCLK2X 43 I/O Pixel clock; two times the actual pixel clock for screen video interface.
PCLK 44 I/O Pixel clock qualifier in for screen video interface.
AUX[7.0] 54,52,53,49:45 I/O Auxiliary control pins (AUX0 and AUX1 are open collectors).
LD[7:0] 62:55 I/O RISC interface data bus.
LWR# 63 O RISC interface write enable (active low).
LOE# 64 O RISC interface output enable (active low).
LCS[3,1,0]# 65,66,67 O RISC interface chip select (active low).
LA[17:0] 87:82, 79:68 O RISC interface address bus.
VPP 81 I Digital supply voltage for 5V.
ACLK 88 I/O Master clock for external audio DAC (8.192MHz, 11.2896MHz, 12.288MHz,16.9344MHz,
and 18.432MHz).
AOUT 89 O Dual-purpose pin. AOUT is the audio interface serial data output.
/SEL-PLLO I Pins SEL-PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK for the
ES3210: 00=bypass PLL.
01=54MHzPLL.
10=67.5MHzPLL.
11=81MHz PLL.
ATCLK 90 I/O Audio transmit bit clock.
ATFS/ 91 O Dual-purpose pin. ATFS is the audio interface transmit frame sync.
SEL-PLL I Pins SEL-PLL[1:0] select phase-lick loop(PLL) clock frequency CPUCLK for the
ES3210. See the SEL-PLL0 pin above for the sttings.
DOE# 92 O DRAM output enable (active low).
AIN 93 I Audio interface serial data input.
ARCLK 94 I Audio receive bit clock.
ARFS 95 I Audio interface receive frame sync.
TDMCLK 96 I TDM interface serial clock.
TDMDR 97 I TDM interface serial data receive.
TDMFS 98 I TDM interface frame sync.
CAS# 99 O DRAM column address strobe bank 0 (active low).

XL-SV320SL/305GD/308BU
1-9
U4: ES3207
Block diagram
Pin configuration

XL-SV320SL/SV305GD
XL-SV308BU
1-10
XL-SV320SL/305GD/308BU
ES3207 Pin description
Name Number I/O Definition
VSS 1,2,25,26,29,30,31, I Ground.
72,75,77,91,100
VCC 3,4,5,16,32 I Voltage supply 5V.
66,73,78,90
DSC-C 6 I Clock for programming to access internal registers.
AUX[15:0] 40-38,36-34,20,18, I/O Auxiliary control pins.
14,67-70,11,9,7
DSC-D[7:0] 81,83,85,93, I Data for programming to access internal registers.
95,97,99,8
DSC-S 10 I Strobe for programming to access internal registers.
DCLK/ 12 O Dual-purpose pin. DCLK is the mpeg decoder clock.
EXT-CLK I EXT-CLK is the external clock. EXT-CLK input during bypass PLL mode.
RST# 13 I Video reset (active low).
MUTE 15 O Audio mute.
MCLK 17 I Audio master clock.
TWS/ I Dual-purpose pin. TWS is the transmit audio frame sync.
SPLLOUT 19 O SPLLOUT is the select PLL output.
TSD 21 I Transmit audio data input.
TBCK 22 I Transmit audio bit clock.
RWS/ O Dual purpose pin. RWS is the receive audio frame sync.
SEL-PLL1 23 I Pins SEL-PLL[1:0] select the PLL clock frequency for DCLK output.
SELPLL1 SELPLL0 DCLK
0 0 Bypass PLL (Input Mode)
0 1 27MHz (Output Mode)
1 0 32.4MHz (Output Mode)
1 1 40.5MHz (Output Mode)
RSTOUT# 24 O Reset output (active low).
NC 27,28,65,76 No connect. Do not connect to these pins.
RSD/ 33 O Dual purpose pin. RSD is the receive audio data input.
SEL-PLL0 I SEL-PLL0 is the select PLL. See the table for pin no. 23.
RBCK 37 O Dual purpose pin. RBCK is the receive audio bit clock.
SER-IN I SER-INis serial input DSC mode.
0=ParallelDSCmode.
1=SerialDSC mode.
VSSA 41,50,51,56,57,62,63 I Analog ground.
VREFM 42 I DAC and ADC minimum reference. Bypass to VCMR with 10µF in parallel with 0.1µF.
VREFP 43 I DAC and ADC maximum reference. Bypass to VCMR with 10µF in parallel with 0.1µF.
VCCA 44,45,59,60 I Analog VCC. 5V.
AOR 46 O Right channel output.
AOL 47 O Left channel output.
MIC2 48 I Microphone input 2.
MIC1 49 I Microphone input 1.
VREF 52 I Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to
analog ground with 0.1µF.
VCM 53 I ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25V.
Bypass to analog ground with 47µF electrolytic in parallel with 0.1µF.
RSET 54 I Full scale DAC current adjustment.
COMP 55 I Compensationpin.
CDAC 58 O Modulated chrominance output.
YDAC 61 O Y luminance data bus for screen video port.
VDAC 64 O Composite video output.
XOUT 71 O Crystal output.
XIN 74 I 27MHz crystal input.
PCLK 79 I/O 13.5MHz pixel clock.
PCLK2X 80 I/O 27MHz (2 times pixel clock).
HSYNC# 82 I/O Horizontal sync (active low).
VSYNC# 84 I/O Vertical sync (active low).
YUV[7:0] 86-89,92,94,96,98 O YUV luminance and chrominance data bus for screen video port.

XL-SV320SL/305GD/308BU
1-11
U3: C16256 (4MB DRAM)
Block diagram
Pin configuration Pin description
Pin No. Pin Name Type Description
16~19,22~26 A0-A8 Input Address input
14 RAS Input Row address
strobe
28 CASH Input Column address
strobe/Upper
byte control
29 CASL Input Column address
strobe/lower
byte control
13 WE Input Write enable
27 OE Input Output enable
2~5,6~10, I/O1 -I/O16 Input/Output Data input/
31~34,36~39 output
1,6,20 Vcc Supply Power, 5V
21, 35, 40 Vss Ground Ground
11,12,15,30 NC - No connect

XL-SV320SL/SV305GD
XL-SV308BU
1-12
XL-SV320SL/305GD/308BU
U2: 27C020 (2MB EEPROM)
Block diagram
Pin configuration Pin description
I/O Pin Name Pin No. Description
- Vpp 1 Voltage input for program erase
operations
I A16,A15,A12 2,3,4 Address input pins
I A7-A0 5-12 Address input pins
I/O D0-D2 13-15 Input/Output pins
- GND 16 Ground
I/O D3-D7 17-21 Input/Output pins
I CE 22 Chip enable (Active low)
I A10 23 Address input pins
I OE 24 Output enable (Active low)
I A11,A9,A8 25,26,27 Address input pins
I A13,A14,A17 28,29,30 Address input pins
I WE 31 Write enable bar (Active low)
- VCC 32 Power supply for device
operation (5V ± 10%)

XL-SV320SL/305GD/308BU
1-13
U5: CXD3068Q (CD DSP)
Block diagram

XL-SV320SL/SV305GD
XL-SV308BU
1-14
XL-SV320SL/305GD/308BU
Pin configuration
Pin description
Pin No. Pin Name I/O Description
1DVDD0 - Digital power supply
2 XRST I System reset. Reset when low.
3 MUTE I Mute input (Low: off, high : on)
4 DATA I Serial data input from CPU
5 XLAT I Latch input from CPU. Serial data is latched at the falling edge.
6 CLOK I Serial data transfer clock input from CPU.
7 SENS O 1,0 SENS outputto CPU.
8 SCLK I SENS serial data readout clock input.
9 ATSK I/O 1,0 Anti-shock input/output
10 WFCK O 1,0 WFCKoutput
11 XUGF O 1,0 XUGF output. MNT0 or RFCK is output by switching with the command.
12 XPCK O 1,0 XPCK output. MNT1 is output by switching with the command.
13 GFS O 1,0 GFS output. MNT2 or XROF is output by switching with the command.
14 C2PO O 1,0 G2PO output. MNT3 or GTOP is output by switching with the command.
15 SCOR O 1,0 Outputs a high signal when either subcode sync S0 or S1 is detected.
16 C4M O 1,0 4.2336MHz output. 1/4 frequency division output for V16M in CAV-W mode or variable
pitch mode.
17 WDCK O 1,0 Word clock output. f=2Fs. GRSCOR is output by the command switching.
18 DVss0 - - DigitalGND.
19 COUT I/O 1,0 Track count signal I/O
20 MIRR I/O 1,0 Mirror signal I/O
21 DFCT I/O 1,0 Detect signal I/O
22 FOK I/O 1,0 Focus OK signal I/O
23 PWMI I Spindle motor external control input.
24 LOCK I/O 1,0 GFS is sampled at 460Hz; when GFC is high, this pin outputs a high signal. If GFS is low
eight consecutive samples, this pin outputs low. Input when LKIN=1.
25 MDP O 1,Z,0 Spindle motor servo control output.
26 SSTP I Disc innermost track detection signal input.
27 FSTO O 1,0 2/3 frequency division output for XTAI pin.
28 DVDD1 - - Digital power supply.
29 SFDR O 1,0 Sled drive output.
30 SRDR O 1,0 Sled drive output.
31 TFDR O 1,0 Tracking drive output.
32 TRDR O 1,0 Tracking drive output.
33 FFDR O 1,0 Focus drive output.

XL-SV320SL/305GD/308BU
1-15
Pin No. Pin Name I/O Description
34 FRDR O 1,0 Focus drive output.
35 DVss1 - - DigitalGND.
36 TEST I Test normally, GND
37 TES1 I Testnormally, GND
38 VC I Center voltage input
39 FE I Focus error signal input
40 SE I Sled error signal input
41 TE I Tracking error signal input
42 CE I Center servo analog input
43 RFDC I RF signal input
44 ADIO O Analog Test No. connected
45 AVss0 - - AnalogGND
46 IGEN I Constant current input for operational amplifier
47 AVDD0 - - Analog power supply
48 ASYO O 1,0 EFM full-swing output. (low=Vss, high=VDD)
49 ASYI I Asymmetry comparator voltage input
50 RFAC I EFMsignal input
51 AVss1 - - AnalogGND
52 CLTV I Multiplier VCO1 control voltage input
53 FILO O Analog Master PLL filter output (slave=digital PLL)
54 FILI I Master PLL filter input
55 PCO O 1,Z,0 Master PLL charge pump output
56 AVDD1 - - Analog power supply
57 BIAS I Asymmetry circuit constant current input
58 VCTL I Wide-band EFM PLL VCO2 control voltage input
59 V16M I/O 1,0 Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM PLL clock
input by switching with the command.
60 VPCO O 1,Z,0 Wide-band EFM PLL change pump output
61 DVDD2 - - Digital power supply
62 ASYE I Asymmetry circuit on/off (low=off, high=on)
63 MD2 I Digital Out on/off control (low=off, high=on)
64 DOUT O 1,0 Digital Out output
65 LRCK O 1,0 D/A interface. LR clock output. f=Fs
66 PCMD O 1,0 D/A interface. Serial data output (two’s complement, MSB first)
67 BCK O 1,0 D/A interface. Bit clock output
68 EMPH O 1,0 Outputs a high signal when the playback disc has emphasis, and a low signal when
there is no emphasis.
69 XTSL I Crystal selection input. Low when the crystal is 16.9344MHz; high when it is
33.8688MHz.
70 DVss2 - - DigitalGND
71 XTAI I Crystal oscillation circuit input. When the master clock is input externally, input it from
this pin.
72 XTAO O Crystal oscillation circuit output.
73 SOUT O 1,0 Serial data output in servo block.
74 SOCK O 1,0 Serial data readout clock output in servo block.
75 XOLT O 1,0 Serial data latch output in servo block.
76 SQCO O 1,0 Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.
77 SQCK I SQCO readout clock input.
78 SCSY I GRSCOR resynchronization input.
79 SBSO O 1,0 Sub-Q P to W serial output.
80 EXCK I SBSO readout clock input.

XL-SV320SL/SV305GD
XL-SV308BU
1-16
XL-SV320SL/305GD/308BU
Pin description
Pin No. Pin Name I/O Description
1 AGCVTH - Reference level variable pin for RF level control. The reference level can be varied by the
external resistor.
2 LD O APC amplifier output pin.
3 PD I APC amplifier input pin.
4 PD1 I Inversion input pin for RF I-V amplifiers.
5 PD2 I Connect these pins to the photodiodes A + C and B + D respectively. The current is supplied.
6VEE - //VEE pin
7 F I Inversion input pin for F and E I-V amplifiers
8 E I Connect these pins to the photodiodes F and E respectively. The current is supplied.
9 EI - Gain adjustment pin for I-V amplifier.
10 VC O DC voltage output pin of (Vcc + VEE)/2. Connect to GND for ±1.75 power supply; connect a
smoothing capacitor for single +3.5V Power supply.
11 TE O Tracking error amplifier output pin. E-F signal is output.
12 FE_BIAS I Bias adjustment pin for inverted side of focus error amplifier.
13 FE O Focus error amplifier output pin.
14 FRM I RF amplifier inverted side input pin. RF amplifier gain is determined by the resistor connected
between this pin and RFO pin.
15 RFO O RF amplifier output pin.
16 RFI I The RF amplifier output RFO is input with its capacitance coupled.
17 RFTC - External time-constant pin for RF level control.
18 AGCCONT I RF level control ON (limit level of 50%/30%)/OFF switching pin. OFF for Vcc, 30% for open or Vc
and 50% for VEE.
19 LD_ON I APC amplifier ON/OFF switching pin. OFF for Vcc and ON for VEE.
20 Vcc Vcc pin
Pin configuration
U6: CXA2550N (RF AMPLIFIER)
Block diagram

XL-SV320SL/305GD/308BU
1-17
Pin description
Pin No. Pin Name Description
1 BIASIN Input for Bias-amplifier
2 OPIN1(+) Non inverting input for CH1 OP-AMP
3 OPIN1(-) Inverting input for CH1 OP-AMP
4 OPOUT1 Output for CH1 OP-AMP
5 OPIN2(+) Non inverting input for CH2 OP-AMP
6 OPIN1(-) Non inverting input for CH2 OP-AMP
7 OPOUT2 inverting input for CH2 OP-AMP
8 GND Substrate ground
9 STBY1 Input for CH1/2/3 stand by control
10 PowVcc1 Vcc for CH1/2 power block
11 VO2(-) Inverted output of CH2
12 VO2(+) Non inverted output of CH2
13 VO1(-) Inverted output of CH1
14 VO1(+) Non inverted output of CH1
15 VO4(+) Non inverted output of CH4
16 VO4(-) Inverted output of CH4
17 VO3(+) Non inverted output of CH3
18 VO3(-) Inverted output of CH3
19 PowVcc2 Vcc for CH3/4 power block
20 STBY2 Input for CH4 stand by control
21 GND Substrate ground
22 OPOUT3 Output for CH3 OP-AMP
23 OPIN3(-) Inverting input for CH3 OP-AMP
24 OPIN3(+) Non inverting input for CH3 OP-AMP
25 OPOUT4 Output for CH4 OP-AMP
26 OPOUT4(-) Inverting input for CH4 OP-AMP
27 OPOUT4(+) Non inverting input for CH4 OP-AMP
28 PreVcc Vcc for pre block
U7: AT6392 (BTL DRIVER)
Block diagram

JVC Asia Pte Ltd
101Thomson Road,#28-04 UnitedSquares, Singapore307591
(No:28207) Printed in Singapore
0006(L)
XL-SV320SL/305GD/308BU

XL-SV320SL/305GD/308BU
3-1
Contents
Exploded view diagram and mechanical parts list .........3-2
Electrical parts list ............................................................3-4
Packing list .......................................................................3-8
Parts ordering form ..........................................................3-9
IMPROTANT
PLASETAKE NOTE BEFOREORDERING
1. Order all service parts through JVC Asia Pte Ltd.-Customer Satisfaction Dept.
2. Twoordersare available:Initialorder and lastorder (Before EndOf Line).
3. Minimum order quantity: 100pcs
4. Delivery term: Minimum 2 months upon confirmation of order.
[XL-SV302SL/305GD/308BU]
PARTS LIST

XL-SV320SL/SV305GD
XL-SV308BU
3-2
XL-SV320SL/305GD/308BU
Exploded view diagram and mechanical parts list
Main unit exploded view diagram