JYTEK PXIe-69834 User manual

PXIe-69834
4CH 16-bit 80MS/s PXIe Digitizer
User’s Manual
Manual Rev.: 1.0
Revision Date: September 12, 2019
Part No: 50-17057-1000

ii
Revision History
Revision Release Date Description of Change(s)
1.0 September 12, 2019 Initial release

Preface iii
Preface
Copyright © 2019 JYTEK Technology Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
JYTEK is committed to fulfill its social responsi-
bility to global environmental preservation
through compliance with the European Union's
Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental pro-
tection is a top priority for JYTEK. We have
enforced measures to ensure that our products,
manufacturing processes, components, and raw
materials have as little impact on the environment as possible.
When products are at their end of life, our customers are encour-
aged to dispose of them in accordance with the product disposal
and/or recovery programs prescribed by their nation or company.

iv Preface
Leading EDGE COMPUTING
Battery Labels (for products with battery)
California Proposition 65 Warning
WARNING: This product can expose you to chemicals
including acrylamide, arsenic, benzene, cadmium,
Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4-
Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC,
and vinyl materials, which are known to the State of California to
cause cancer, and acrylamide, benzene, cadmium, lead, mercury,
phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
birth defects or other reproductive harm. For more information go
to www.P65Warnings.ca.gov.
Trademarks
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.
ᘄ㟁ụㄳᅇᨲ

Preface v
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users perform
tasks.
CAUTION:
Information to prevent minor physical injury, component dam-
age, data loss, and/or program corruption when trying to com-
plete a task.
WARNING:
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

vi Preface
Leading EDGE COMPUTING
This page intentionally left blank.

Table of Contents vii
Table of Contents
Preface .................................................................................... iii
List of Figures ........................................................................ ix
List of Tables.......................................................................... xi
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 2
1.3.1 Analog Input ............................................................... 2
1.3.2 Accuracy..................................................................... 3
1.3.3 System Noise ............................................................. 3
1.3.4 Crosstalk, DC to 10MHz ............................................. 3
1.3.5 Spectral Characteristics.............................................. 4
1.3.6 Timebase.................................................................... 6
1.3.7 Triggers ...................................................................... 7
1.3.8 Mechanical and Environmental .................................. 9
1.3.9 Power Consumption ................................................... 9
1.4 Software Support ............................................................... 10
1.4.1 MAPS Core............................................................... 11
1.4.2MAPS/C, C & C++ Support ...................................... 14
1.5 Device Layout and I/O Connectors.................................... 15
2 Getting Started ................................................................. 19
2.1 Installation Environment .................................................... 19
2.2 Package Contents ............................................................. 20
2.3 Installing the Module.......................................................... 21
3 Operations ........................................................................ 23

viii Table of Contents
Leading EDGE COMPUTING
3.1 Functional Block Diagram .................................................. 23
3.2 Analog Input Channel ........................................................ 23
3.2.1 Analog Input Front-End Configuration ...................... 23
3.2.2 Input Range and Data Format .................................. 24
3.2.3 DMA Data Transfer...................................................26
3.3 Trigger Source ................................................................... 27
3.3.1 Software Trigger ....................................................... 28
3.3.2 External Digital Trigger ............................................. 28
3.3.3 Analog Trigger .......................................................... 29
3.3.4 PXI Trigger Bus ........................................................ 30
3.3.5 PXI Star .................................................................... 30
3.3.6 PXIe Differential Trigger ........................................... 30
3.4 Trigger Modes.................................................................... 31
3.4.1 Post Trigger Mode .................................................... 31
3.4.2 Delayed Trigger Mode .............................................. 32
3.4.3 Pre-Trigger Mode...................................................... 32
3.4.4 Middle Trigger Mode.................................................33
3.4.5 Acquisition with Re-Triggering .................................. 34
3.5 Timebase ........................................................................... 35
3.5.1 Internal Sampling Clock............................................35
3.5.3 External Reference Clock ......................................... 36
3.6 Acquisition Timing Control ................................................. 37
3.7 Synchronizing Multiple Modules ........................................ 39
3.7.1 Multi-module Synchronization Interfaces..................43
A Appendix: Calibration....................................................... 45
A.1 Calibration Constant .......................................................... 45
A.2 Auto-Calibration ................................................................. 46
Important Safety Instructions.............................................. 49

List of Figures ix
List of Figures
Figure 1-1: Typical Frequency Response, 1Minput impedance 4
Figure 1-2: Typical Frequency Response, 50input impedance . 5
Figure 1-3: JYTEK MAPS Architecture ....................................... 10
Figure 1-4: JYTEK Connection Explorer (ACE) .......................... 12
Figure 1-5: JYTEK Connection Explorer Soft Front Panel .......... 13
Figure 1-6: PXIe-69834 Dimensions........................................... 15
Figure 1-7: PXIe-69834 Front Panel ........................................... 16
Figure 3-1: Functional Block Diagram......................................... 23
Figure 3-2: Analog Input Architecture ......................................... 23
Figure 3-3: Linked List of PCI Address DMA Descriptors ........... 27
Figure 3-4: Trigger Architecture .................................................. 27
Figure 3-5: External Digital Trigger ............................................. 28
Figure 3-6: Analog Trigger Conditions ....................................... 29
Figure 3-7: Post-Trigger Acquisition ........................................... 31
Figure 3-8: Delayed Trigger Mode Acquisition............................ 32
Figure 3-9: Pre-Trigger Mode Acquisition ................................... 32
Figure 3-10: Middle Trigger Mode Acquisition .............................. 33
Figure 3-11: Re-Trigger Mode Acquisition .................................... 34
Figure 3-12: Timebase Architecture.............................................. 35
Figure 3-13: Varying Sampling Rates via Scan Interval Counter.. 37
Figure 3-14: Non-synched Digitizer Modules................................ 39
Figure 3-15: External Instrument Synchronization........................ 40
Figure 3-16: Module-based Synchronization ................................ 41
Figure 3-17: PXIe Instrumentation Signals ................................... 42
Figure 3-18: Trigger Architecture .................................................. 43
Figure 3-19: PXI_CLK10 as 10MHz Reference ............................ 44
Figure A-1: Auto-Calibration Block Diagram ............................... 46
Figure A-2: Auto-Calibration Flow ............................................... 47

x List of Figures
Leading EDGE COMPUTING
This page intentionally left blank.