Linear Technology LTC2175-12 User manual

1
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
Typical applicaTion
FeaTures
applicaTions
DescripTion
12-Bit, 125Msps/105Msps/
80Msps Low Power Quad ADCs
LTC2175-12, 125Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
TheLTC
®
2175-12/LTC2174-12/LTC2173-12are4-channel,
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSBRMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
The ENC+and ENC–inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n4-Channel Simultaneous Sampling ADC
n70.6dB SNR
n88dB SFDR
nLow Power: 545mW/439mW/369mW Total,
136mW/110mW/92mW per Channel
nSingle 1.8V Supply
nSerial LVDS Outputs: 1 or 2 Bits per Channel
nSelectable Input Ranges: 1VP-P to 2VP-P
n800MHz Full Power Bandwidth S/H
nShutdown and Nap Modes
nSerial SPI Port for Configuration
nPin Compatible 14-Bit and 12-Bit Versions
n52-Pin (7mm ×8mm) QFN Package
nCommunications
nCellular Base Stations
nSoftware Defined Radios
nPortable Medical Imaging
nMultichannel Data Acquisition
nNondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
217512 TA01b
DATA
SERIALIZER
ENCODE
INPUT
SERIALIZED
LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
DATA
CLOCK
OUT
FRAME
OGND
GND
217512 TA01
S/H
CHANNEL 1
ANALOG
INPUT
12-BIT
ADC CORE
S/H
CHANNEL 2
ANALOG
INPUT
12-BIT
ADC CORE
S/H
CHANNEL 3
ANALOG
INPUT
12-BIT
ADC CORE
S/H
CHANNEL 4
ANALOG
INPUT
12-BIT
ADC CORE
PLL

LTC2175-12/
LTC2174-12/LTC2173-12
2
21754312fa
absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTions
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2175CUKG-12#PBF LTC2175CUKG-12#TRPBF LTC2175UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2175IUKG-12#PBF LTC2175IUKG-12#TRPBF LTC2175UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
LTC2174CUKG-12#PBF LTC2174CUKG-12#TRPBF LTC2174UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2174IUKG-12#PBF LTC2174IUKG-12#TRPBF LTC2174UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
LTC2173CUKG-12#PBF LTC2173CUKG-12#TRPBF LTC2173UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C
LTC2173IUKG-12#PBF LTC2173IUKG-12#TRPBF LTC2173UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Supply Voltages
VDD, OVDD................................................ –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
PAR/SER, SENSE) (Note 3).......... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2175C, 2174C, 2173C......................... 0°C to 70°C
LTC2175I, 2174I, 2173I ........................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
1615 17 18 19
TOP VIEW
53
GND
UKG PACKAGE
52-LEAD (7mm ×8mm) PLASTIC QFN
20 21 22 23 24 25 26
5152 50 49 48 47 46 45 44 43 42 41
33
34
35
36
37
38
39
40
8
7
6
5
4
3
2
1AIN1+
AIN1–
VCM12
AIN2+
AIN2–
REFH
REFH
REFL
REFL
AIN3+
AIN3–
VCM34
AIN4+
AIN4–
OUT2A+
OUT2A–
OUT2B+
OUT2B–
DCO+
DCO–
OVDD
OGND
FR+
FR–
OUT3A+
OUT3A–
OUT3B+
OUT3B–
VDD VDD SENSE GND VREF PAR/SER SDO GND OUT1A+ OUT1A– OUT1B+ OUT1B–
VDD VDD
ENC+ ENC–
CS
SCK
SDI
GND
OUT4B–
OUT4B+ OUT4A– OUT4A+
32
31
30
29
28
27
9
10
11
12
13
14
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB

3
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
converTer characTerisTics
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (Note 5)
PARAMETER CONDITIONS
LTC2175-12 LTC2174-12 LTC2173-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l12 12 12 Bits
Integral Linearity Error Differential Analog Input (Note 6) l–1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 LSB
Differential Linearity Error Differential Analog Input l–0.4 ±0.1 0.4 –0.4 ±0.1 0.4 –0.4 ±0.1 0.4 LSB
Offset Error (Note 7) l–12 ±3 12 –12 ±3 12 –12 ±3 12 mV
Gain Error Internal Reference
External Reference
l
–2.8
–1.3
–1.3 0.2 –2.8
–1.3
–1.3 0.2 –2.8
–1.3
–1.3 0.2
%FS
%FS
Offset Drift ±20 ±20 ±20 µV/°C
Full-Scale Drift Internal Reference
External Reference
±35
±25
±35
±25
±35
±25
ppm/°C
ppm/°C
Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS
Offset Matching ±3 ±3 ±3 mV
Transition Noise External Reference 0.3 0.3 0.3 LSBRMS
analog inpuT
The ldenotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+– AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P
VIN(CM) Analog Input Common Mode (AIN++ AIN–)/2 Differential Analog Input (Note 8) lVCM – 100mV VCM VCM + 100mV V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V
IINCM Analog Input Common Mode Current Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
µA
µA
µA
IIN1 Analog Input Leakage Current No Encode 0 < AIN+, AIN–< VDD,l–1 1 µA
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA
IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–6 6 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz

LTC2175-12/
LTC2174-12/LTC2173-12
4
21754312fa
DynaMic accuracy
The ldenotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA= 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2175-12 LTC2174-12 LTC2173-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 5MHz Input
70MHz Input
140MHz Input
l
69.3
70.6
70.6
70.3
69.2
70.6
70.5
70.3
69.3
70.6
70.5
70.3
dBFS
dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
70MHz Input
140MHz Input
l
74
88
85
82
74
88
85
82
76
88
85
82
dBFS
dBFS
dBFS
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
70MHz Input
140MHz Input
l
84
90
90
90
84
90
90
90
85
90
90
90
dBFS
dBFS
dBFS
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
l
68.6
70.6
70.4
70
68.7
70.6
70.4
70
68.9
70.6
70.4
70
dBFS
dBFS
dBFS
Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc
Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc
inTernal reFerence characTerisTics
The ldenotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA= 25°C. AIN = –1dBFS. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V
VCM Output Temperature Drift ±25 ppm/°C
VCM Output Resistance –600µA < IOUT < 1mA 4 Ω
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±25 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7 Ω
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V

5
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
DigiTal inpuTs anD ouTpuTs
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
Differential Encode Mode (ENC–Not Tied to GND)
VID Differential Input Voltage (Note 8) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 8)
l
1.1
1.2
1.6
V
V
VIN Input Voltage Range ENC+, ENC–to GND l0.2 3.6 V
RIN Input Resistance (See Figure 10) 10 kΩ
CIN Input Capacitance 3.5 pF
Single-Ended Encode Mode (ENC–Tied to GND)
VIH High Level Input Voltage VDD = 1.8V l1.2 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
VIN Input Voltage Range ENC+to GND l0 3.6 V
RIN Input Resistance (See Figure 11) 30 kΩ
CIN Input Capacitance 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
IIN Input Current VIN = 0V to 3.6V l–10 10 µA
CIN Input Capacitance 3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
COUT Output Capacitance 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
mV
mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
V
V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

LTC2175-12/
LTC2174-12/LTC2173-12
6
21754312fa
power requireMenTs
The ldenotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA= 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2175-12 LTC2174-12 LTC2173-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IVDD Analog Supply Current Sine Wave Input l276 300 218 240 180 196 mA
IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
27
49
31
54
26
48
31
53
25
47
29
52
mA
mA
PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
545
585
596
637
439
479
488
527
369
409
405
446
mW
mW
PSLEEP Sleep Mode Power 1 1 1 mW
PNAP Nap Mode Power 85 85 85 mW
PDIFFCLK Power Increase With Differential Encode Mode Enabled
(No Increase for Sleep Mode)
20 20 20 mW
TiMing characTerisTics
The ldenotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2175-12 LTC2174-12 LTC2173-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Notes 10,11) l5 125 5 105 5 80 MHz
tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
100
100
4.52
2
4.76
4.76
100
100
5.93
2
6.25
6.25
100
100
ns
ns
tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
100
100
4.52
2
4.76
4.76
100
100
5.93
2
6.25
6.25
100
100
ns
ns
tAP Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL= 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 • fS)
1/(7 • fS)
1/(6 • fS)
1/(16 • fS)
1/(14 • fS)
1/(12 • fS)
s
s
s
s
s
s
tFRAME FR to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s
tDATA DATA to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s
tPD Propagation Delay (Note 8) l0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s
tROutput Rise Time Data, DCO, FR, 20% to 80% 0.17 ns
tFOutput Fall Time Data, DCO, FR, 20% to 80% 0.17 ns
DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P
Pipeline Latency 6 Cycles

7
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode
Readback Mode, CSDO = 20pF, RPULLUP
= 2k
l
l
40
250
ns
ns
tSCS to SCK Setup Time l5 ns
tHSCK to CS Setup Time l5 ns
tDS SDI Setup Time l5 ns
tDH SDI Hold Time l5 ns
tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP
= 2k
l125 ns
TiMing characTerisTics
The ldenotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA= 25°C. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V
DD
= OV
DD
= 1.8V, f
SAMPLE
= 125MHz (LTC2175), 105MHz
(LTC2174), or 80MHz (LTC2173), 2-lane output mode, differential ENC+/
ENC–= 2V
P-P
sine wave, input range = 2V
P-P
with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111
in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz
(LTC2174), or 80MHz (LTC2173), 2-lane output mode, ENC+= single-
ended 1.8V square wave, ENC–= 0V, input range = 2VP-P with differential
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4.
Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and
Ch.2 to Ch.4.

LTC2175-12/
LTC2174-12/LTC2173-12
8
21754312fa
2-Lane Output Mode, 14-Bit Serialization
ANALOG
INPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER
tSER
tSER tPD
tDATA tFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3
N+1
N+2
N
217512 TD02
D5 D3 D1 DX*D11 D9 D7 D5 D3 D1 DX*D11 D9 D7 D5 D3 D1 D11 D9 D7
OUT#A–
OUT#A+
FR–
FR+
D4 D2 D0 DY*D10 D8 D6 D4 D2 D0 DY*
DX*
DY*D10 D8 D6 D4 D2 D0 D10 D8 D6
OUT#B–
OUT#B+
NOTE THAT IN THIS MODE FR+/FR–HAS TWO TIMES THE PERIOD OF ENC+/ENC–
*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
TiMing DiagraMs
2-Lane Output Mode, 16-Bit Serialization
ANALOG
INPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER
tSER
tSER tPD
tDATA tFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1
N
217512 TD01
D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 DX* 0 D11 D9 D7
OUT#A–
OUT#A+
FR–
FR+
D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6
OUT#B–
OUT#B+
*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

9
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
TiMing DiagraMs
2-Lane Output Mode, 12-Bit Serialization
1-Lane Output Mode, 16-Bit Serialization
ANALOG
INPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER
tSER
tSER tPD
tDATA tFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1
N
217512 TD03
D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7
OUT#A–
OUT#A+
FR+
FR–
D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6
OUT#B–
OUT#B+
ANALOG
INPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER tPD
tDATA tFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1
N
tSER
tSER
217512 TD05
DX* DY* DX* DY*0 0 D11 D10 D9 D8 D10 D9 D8D7 D6 D5 D4 D3 D2 D1 D0 0 0 D11
OUT#A–
OUT#A+
FR–
FR+
OUT#B+, OUT#B–ARE DISABLED
*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

LTC2175-12/
LTC2174-12/LTC2173-12
10
21754312fa
TiMing DiagraMs
One-Lane Output Mode, 14-Bit Serialization
ANALOG
INPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER tPD
tDATA tFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1
N
tSER
tSER
217512 TD06
D1 D0 DX* DX* DY*DY*D11 D10 D9 D8 D10 D9 D8D7 D6 D5 D4 D3 D2 D1 D0 D11
OUT#A–
OUT#A+
FR–
FR+
OUT#B+, OUT#B–ARE DISABLED
*DXAND DYARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DXAND DYARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
One-Lane Output Mode, 12-Bit Serialization
ANALOG
INPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER tPD
tDATA tFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1
N
tSER
tSER
217512 TD07
D3 D2 D1 D0 D11 D10 D9 D8 D10 D9D7 D6 D5 D4 D3 D2 D1 D0 D11
OUT#A–
OUT#A+
FR–
FR+
OUT#B+, OUT#B–ARE DISABLED
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
217512 TD04
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)

11
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
Typical perForMance characTerisTics
LTC2175-12: Integral
Nonlinearity (INL)
LTC2175-12: Differential
Nonlinearity (DNL)
LTC2175-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 125Msps
OUTPUT CODE
0
–1.0
–0.4
–0.6
–0.8
INL ERROR (LSB)
–0.2
0
0.2
0.8
0.4
0.6
1.0
1024 2048 3072 4096
217512 G01
OUTPUT CODE
0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
1024 2048 3072 4096
217512 G02
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
217512 G03
010 20 30 40 50 60
LTC2175-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 125Msps
LTC2175-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 125Msps
LTC2175-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 125Msps
LTC2175-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
LTC2175-12: Shorted Input
Histogram
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
217512 G04
10 20 30 40 50 60
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
217512 G05
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
217512 G06
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
217512 G07
OUTPUT CODE
2041 2042 2044
2000
0
10000
8000
6000
4000
COUNT
12000
16000
14000
18000
2043 2045
217512 G08
INPUT FREQUENCY (MHz)
0
72
71
70
69
68
67
66
SNR (dBFS)
50 100 150 200 250 300 350
217512 G09
LTC2175-12: SNR vs Input
Frequency, –1dB, 2V Range,
125Msps

LTC2175-12/
LTC2174-12/LTC2173-12
12
21754312fa
Typical perForMance characTerisTics
LTC2175-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
LTC2175-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
10
0
80
70
SFDR (dBc AND dBFS)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
217512 G12
dBFS
dBc
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR (dBFS)
50 100 150 200 250 300 350
217512 G10
LTC2175-12: SFDR vs Input
Frequency, –1dB, 2V Range,
125Msps
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
LTC2175-12: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2174-12: Integral Nonlinearity
(INL)
LTC2174-12: Differential
Nonlinearity (DNL)
LTC2174-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
SENSE PIN (V)
0.6
71
68
69
70
67
66
72
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
217512 G15
OUTPUT CODE
0
–1.0
–0.4
–0.6
–0.8
INL ERROR (LSB)
–0.2
0
0.2
0.4
0.6
0.8
1.0
1024 2048 3072 4096
217512 G21
OUTPUT CODE
0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
1024 2048 3072 4096
217512 G22
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
217512 G23
SAMPLE RATE (Msps)
290
280
270
260
250
240
230
220
210
IVDD (mA)
0 25 50 75 100 125
217512 G53
SAMPLE RATE (Msps)
50
40
30
20
10
0
IOVDD (mA)
0 25 50 75 100 125
217512 G51
1-LANE, 1.75mA
2-LANE, 3.5mA
2-LANE, 1.75mA
1-LANE, 3.5mA
INPUT LEVEL (dBFS)
60
50
40
30
20
10
0
80
70
SNR (dBc AND dBFS)
–60 –50 –40 –30 –20 –10 0
217512 G50
dBFS
dBc
LTC2175-12: SNR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps

13
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
LTC2174-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2174-12: Shorted Input
Histogram
LTC2174-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
Typical perForMance characTerisTics
OUTPUT CODE
2044
2000
0
6000
4000
COUNT
8000
16000
14000
12000
10000
18000
2046 20472045 2048
217512 G28
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
10
0
80
70
SFDR (dBc AND dBFS)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
217512 G32
dBFS
dBc
INPUT FREQUENCY (MHz)
0
72
71
70
69
68
67
66
SNR (dBFS)
50 100 150 200 250 300 350
217512 G29
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR (dBFS)
50 100 150 200 250 300 350
217512 G23a
LTC2174-12: SNR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2174-12: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2174-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 105Msps
LTC2174-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
217512 G25
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
217512 G26
LTC2174-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
105Msps
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
217512 G27
SAMPLE RATE (Msps)
230
220
210
200
190
180
170
160
IVDD (mA)
0 25 50 75 100
217512 G54
LTC2174-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
217512 G24

LTC2175-12/
LTC2174-12/LTC2173-12
14
21754312fa
LTC2174-12: SNR vs SENSE,
fIN = 5MHz, –1dB
SENSE PIN (V)
0.6
71
68
69
70
67
66
72
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
217512 G35
Typical perForMance characTerisTics
LTC2173-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTC2173-12: Shorted Input
Histogram
LTC2173-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 80Msps
LTC2173-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 80Msps
LTC2173-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 80Msps
LTC2173-12: Integral Nonlinearity
(INL)
LTC2173-12: Differential
Nonlinearity (DNL)
LTC2173-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 80Msps
OUTPUT CODE
0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
1024 2048 3072 4096
217512 G42
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
217512 G43
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
217512 G44
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
217512 G45
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
217512 G46
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
217512 G47
OUTPUT CODE
2052
2000
4000
6000
8000
0
12000
10000
COUNT
14000
16000
18000
20542053 20562055
217512 G48
OUTPUT CODE
0
–1.0
–0.4
–0.6
–0.8
INL ERROR (LSB)
–0.2
0
0.4
0.6
0.2
0.8
1.0
1024 2048 3072 4096
217512 G41

15
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
Typical perForMance characTerisTics
LTC2173-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
DCO Cycle-Cycle Jitter vs Serial
Data Rate
LTC2173-12: SNR vs SENSE,
fIN = 5MHz, –1dB
SENSE PIN (V)
0.6
71
68
69
70
67
66
72
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31.0
217512 G55a
LTC2173-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
10
0
80
70
SFDR (dBc AND dBFS)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
217512 G52
dBFS
dBc
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR (dBFS)
50 100 150 200 250 300 350
217512 G35a
LTC2173-12: SFDR vs Input
Frequency, –1dB, 2V Range,
80Msps
INPUT FREQUENCY (MHz)
0
72
71
70
69
68
67
66
SNR (dBFS)
50 100 150 200 250 300 350
217512 G49
LTC2173-12: SNR vs Input
Frequency, –1dB, 2V Range,
80Msps
SERIAL DATA RATE (Mbps)
350
300
250
200
150
100
50
0
PEAK-TO-PEAK JITTER (ps)
0 200 400 600 800 1000
217512 G52a
SAMPLE RATE (Msps)
190
170
180
160
150
140
IVDD (mA)
0 20 40 8060
217512 G55

LTC2175-12/
LTC2174-12/LTC2173-12
16
21754312fa
pin FuncTions
AIN1+(Pin 1): Channel 1 Positive Differential Analog
Input.
AIN1–(Pin 2): Channel1 NegativeDifferentialAnalogInput.
VCM12 (Pin 3): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 1 and 2. Bypass
to ground with a 0.1µF ceramic capacitor.
AIN2+(Pin 4): Channel 2 Positive Differential Analog
Input.
AIN2–(Pin 5): Channel2 NegativeDifferentialAnalogInput.
REFH (Pins 6,7): ADC High Reference. Bypass to pins 8, 9
with a 2.2µF ceramic capacitor and to ground with a 0.1µF
ceramic capacitor.
REFL (Pins 8,9): ADC Low Reference. Bypass to pins 6, 7
with a 2.2µF ceramic capacitor and to ground with a 0.1µF
ceramic capacitor.
AIN3+(Pin10): Channel 3PositiveDifferentialAnalogInput.
AIN3–(Pin11): Channel3NegativeDifferentialAnalogInput.
VCM34 (Pin 12): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 3 and 4. Bypass
to ground with a 0.1µF ceramic capacitor.
AIN4+(Pin13): Channel 4PositiveDifferentialAnalogInput.
AIN4–(Pin14): Channel4NegativeDifferentialAnalogInput.
VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+(Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC–(Pin 18): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When CS is
low, SCK is enabled for shifting data on SDI into the mode
controlregisters. Inthe parallelprogramming mode(PAR/
SER = VDD), CS selects 2-lane or 1-lane output mode. CS
can be driven with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 21): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data Input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (Pins 22, 45, 49, Exposed Pad Pin 53): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply, 1.7V to 1.9V. Bypass
to ground with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO is an
input that enables internal 100Ω termination resistors on
the digital outputs. When used as an input, SDO can be
driven with 1.8V to 3.3V logic through a 1k series resistor.
PAR/SER (Pin 47): Programming Mode Selection Pin.
Connectto groundto enablethe serialprogrammingmode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.

17
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
pin FuncTions
VREF (Pin48): ReferenceVoltageOutput.Bypasstoground
with a 1µF ceramic capacitor, nominally 1.25V.
SENSE (Pin 50): ReferenceProgrammingPin.Connecting
SENSEtoVDD selectstheinternalreferenceand a ±1Vinput
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
LVDS Outputs
All pins in this section are differential LVDS outputs.
The output current level is programmable. There is an
optional internal 100Ω termination resistor between
the pins of each LVDS output pair.
OUT4B–/OUT4B+, OUT4A–/OUT4A+(Pins 23/24,
Pins 25/26): Serial data outputs for Channel 4. In 1-lane
output mode only OUT4A–/OUT4A+are used.
OUT3B–/OUT3B+, OUT3A–/OUT3A+(Pins 27/28,
Pins 29/30): Serial data outputs for Channel 3. In 1-lane
output mode only OUT3A–/OUT3A+are used.
FR–/FR+(Pins 31/32): Frame Start Outputs.
DCO–/DCO+(Pins 35/36): Data Clock Outputs.
OUT2B–/OUT2B+, OUT2A–/OUT2A+(Pins 37/38,
Pins 39/40): Serial data outputs for Channel 2. In 1-lane
output mode only OUT2A–/OUT2A+are used.
OUT1B–/OUT1B+, OUT1A–/OUT1A+(Pins 41/42,
Pins 43/44): Serial data outputs for Channel 1. In 1-lane
output mode only OUT1A–/OUT1A+are used.

LTC2175-12/
LTC2174-12/LTC2173-12
18
21754312fa
FuncTional block DiagraM
Figure 1. Functional Block Diagram
DIFF
REF
AMP
REF
BUF
2.2µF
0.1µF 0.1µF
0.1µF
0.1µF
REFH REFL
RANGE
SELECT
1.25V
REFERENCE
VDD/2
VDD
1.8V
REFH
GND REFL VCM12 VCM34
DATA
SERIALIZER
OGND
217512 F01
S/H
S/H
S/H
S/H
SENSE
VREF
1µF
0.1µF
12-BIT
ADC CORE
12-BIT
ADC CORE
12-BIT
ADC CORE
12-BIT
ADC CORE
OVDD
1.8V
ENC+ENC–
PLL
OUT1A–
OUT1A+
OUT1B–
OUT1B+
OUT2A–
OUT2A+
OUT2B–
OUT2B+
DATA
CLOCK OUT+
DATA
CLOCK OUT–
OUT3A–
OUT3A+
OUT3B–
OUT3B+
OUT4A–
OUT4A+
OUT4B–
OUT4B+
FRAME+
FRAME–
SDOCS
MODE
CONTROL
REGISTERS
SCKPAR/SER SDI
CHANNEL 1
ANALOG INPUT+
CHANNEL 1
ANALOG INPUT–
CHANNEL 2
ANALOG INPUT+
CHANNEL 2
ANALOG INPUT–
CHANNEL 3
ANALOG INPUT+
CHANNEL 3
ANALOG INPUT–
CHANNEL 4
ANALOG INPUT+
CHANNEL 4
ANALOG INPUT–

19
21754312fa
LTC2175-12/
LTC2174-12/LTC2173-12
applicaTions inForMaTion
CONVERTER OPERATION
The LTC2175-12/LTC2174-12/LTC2173-12 are low power,
4-channel, 12-bit, 125Msps/105Msps/80Msps A/D con-
verters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially for optimal jitter perfor-
mance,orsingle-endedfor lower powerconsumption.The
digital outputs are serial LVDS to minimize the number
of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
perchanneloption(1-lanemode).Manyadditionalfeatures
canbechosenby programmingthemode controlregisters
through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differen-
tially around a common mode voltage set by the VCM12
or VCM34 output pins, which are nominally VDD/2. For the
2V input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
Thefourchannels aresimultaneouslysampled bya shared
encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC low pass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitryfromtheA/Dsample-and-holdswitching,andalso
limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
Figure 2. Equivalent Input Circuit. Only One of the Four
Analog Channels Is Shown.
CSAMPLE
3.5pF
RON
25Ω
RON
25Ω
VDD
VDD
LTC2175-12
AIN+
217512 F02
CSAMPLE
3.5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10Ω
10Ω
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz.
25Ω
25Ω 25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
12pF
0.1µF
VCM
LTC2175-12
ANALOG
INPUT
0.1µF T1
1:1
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
217512 F03

LTC2175-12/
LTC2174-12/LTC2173-12
20
21754312fa
applicaTions inForMaTion
tap is biased with VCM, setting the A/D input at its opti-
mal DC level. At higher input frequencies a transmission
line balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
Figure 4. Recommended Front End Circuit for Input
Frequencies from 70MHz to 170MHz
25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
4.7pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
217512 F04
LTC2175-12
25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
1.8pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
217512 F05
LTC2175-12
25Ω
25Ω
50Ω
0.1µF
2.7nH
2.7nH
AIN+
AIN–
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
217512 F06
LTC2175-12
25Ω
25Ω
200Ω
200Ω
0.1µF AIN+
AIN–
12pF
0.1µF
VCM
LTC2175-12
217512 F07
––
++
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
4 to 6) should convert the signal to differential before
driving the A/D.
Reference
The LTC2175-12/LTC2174-12/LTC2173-12 has an internal
1.25V voltage reference. For a 2V input range using the
internal reference, connect SENSE to VDD. For a 1V input
range using the internal reference, connect SENSE to
Figure 5. Recommended Front End Circuit for Input
Frequencies from 170MHz to 300MHz
Figure 6. Recommended Front End Circuit for Input
Frequencies Above 300MHz
Figure 7. Front End Circuit Using a High Speed
Differential Amplifier