Maxim Integrated MAX32600 User manual

MAX32600
User’s Guide
April 2015

MAX32600 User’s Guide Contents Contents
Contents
1 Main Page 2
1.1 Legal Disclaimer ...................................................................... 2
1.2 Revision Information .................................................................... 2
2 Introduction 4
2.1 Overview ......................................................................... 4
2.2 Core and Architecture ................................................................... 6
2.2.1 Core Parameters ................................................................. 6
2.2.2 Generic Memory Map ............................................................... 8
2.2.3 AHB Buses .................................................................... 9
2.2.4 APB Buses .................................................................... 9
2.2.5 Nested Vectored Interrupt Controller (NVIC) ................................................... 9
2.2.6 ARM Debug .................................................................... 10
2.3 Power Supplies and Modes ................................................................ 10
2.3.1 Digital Supply Voltages .............................................................. 10
2.3.2 Analog Supply Voltage .............................................................. 10
2.3.3 Onboard Core Voltage Regulator ......................................................... 11
2.3.4 Onboard VUSB Voltage Regulator and Automatic Power Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 VRTC Power Supply ............................................................... 11
2.3.6 Power Management Modes ............................................................ 11
2.3.7 Power Supply Monitoring ............................................................. 11
2.4 Clock Inputs ........................................................................ 12
2.4.1 External High Frequency Crystal ......................................................... 12
2.4.2 32kHz Crystal Oscillator ............................................................. 12
2.4.3 48MHz USB Clock PLL .............................................................. 12
2.4.4 Internal 24MHz Trimmed Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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2.4.5 Cryptographic Internal Oscillator ......................................................... 13
2.5 Memory .......................................................................... 13
2.5.1 Internal Flash Program Memory ......................................................... 13
2.5.2 2 KB Instruction Cache .............................................................. 13
2.5.3 Internal Data SRAM ............................................................... 14
2.5.4 Peripheral Management Unit (PMU) ....................................................... 14
2.5.5 Flash Information Block .............................................................. 15
2.5.6 Flash Memory Controller ............................................................. 15
2.6 Analog Peripherals .................................................................... 16
2.6.1 16-Bit ADC with PGA ............................................................... 16
2.6.2 ADC/DAC Internal/External Reference and Programmable Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.3 12-Bit Voltage Output DACs ........................................................... 16
2.6.4 8-Bit Voltage Output DACs ............................................................ 17
2.6.5 Uncommitted Op Amps with Comparator Mode ................................................. 17
2.6.6 Uncommitted SPST Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.7 Temperature Sensor ............................................................... 17
2.7 Digital Peripherals ..................................................................... 17
2.7.1 GPIO Pins w/Interrupt and Wakeup Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7.2 32-Bit Timer/Counters .............................................................. 18
2.7.3 Watchdog Timers ................................................................. 18
2.7.4 32-Bit Real Time Clock with Time of Day Alarm ................................................. 19
2.7.5 SPI (three instances) ............................................................... 19
2.7.6 I²C ......................................................................... 19
2.7.7 USB 2.0 Device Slave with Integrated Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7.8 LCD Controller .................................................................. 20
2.8 Security Features ..................................................................... 21
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2.8.1 Trust Protection Unit (TPU) ............................................................ 21
2.8.2 AES Cryptographic Engine ............................................................ 21
2.8.3 Battery-Backed AES Secure Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8.4 Modular Arithmetic Accelerator (MAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8.5 CRC Hardware Block with CRC16 and CRC32 ................................................. 22
2.8.6 Code Scrambling ................................................................. 22
3 Memory, Register Mapping, and Access 23
3.1 Memory, Register Mapping, and Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Standard Memory Regions ................................................................ 24
3.2.1 Code Space .................................................................... 24
3.2.2 SRAM Space ................................................................... 24
3.2.3 Peripheral Space ................................................................. 25
3.2.4 External RAM Space ............................................................... 26
3.2.5 External Device Space .............................................................. 26
3.2.6 System Area (Private Peripheral Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.7 System Area (Vendor Defined) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Device Memory Instances ................................................................. 26
3.3.1 Main Program Flash Memory ........................................................... 27
3.3.2 Instruction Cache Memory ............................................................ 27
3.3.3 Information Block Flash Memory ......................................................... 27
3.3.4 System SRAM .................................................................. 27
3.3.5 AES Key and Working Space Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.6 Modular Arithmetic Accelerator (MAA) Key and Working Space Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.7 TPU Memory Secure Key Storage Area ..................................................... 27
3.4 AHB Bus Matrix and AHB Bus Interfaces ......................................................... 28
3.4.1 Core AHB Interface - I-Code ........................................................... 28
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3.4.2 Core AHB Interface - D-Code ........................................................... 28
3.4.3 Core AHB Interface - System ........................................................... 28
3.4.4 AHB Master - Peripheral Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.5 AHB Master - USB Endpoint Buffer Manager ................................................... 28
4 System Configuration and Management 29
4.1 Power Ecosystem and Operating Modes ......................................................... 29
4.1.1 Power Ecosystem ................................................................. 29
4.1.2 Low Power Modes (LP0: STOP and LP1: STANDBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.2.1 Low Power Mode 0 (LP0: STOP) ................................................... 31
4.1.2.2 Low Power Mode 1 (LP1: STANDBY) ................................................. 31
4.1.2.3 Entering LP0: STOP or LP1: STANDBY ............................................... 32
4.1.2.4 Wakeup Events from LP0: STOP and LP1: STANDBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.3 Low Power Modes (LP2: PMU and LP3: RUN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3.1 Low Power Mode 2 (LP2: Peripheral Management Unit) ....................................... 35
4.1.3.2 Low Power Mode 3 (LP3: RUN) .................................................... 35
4.1.4 Power State Matrix Control Options ....................................................... 35
4.1.5 Power Domains .................................................................. 37
4.1.6 Power Manager .................................................................. 38
4.1.7 Power Sequencer ................................................................. 38
4.1.7.1 Power Mode Transitioning to Low Power Modes ............................................ 38
4.1.7.2 Supply Voltage Monitoring During LP0: STOP and LP1: STANDBY ................................. 38
4.1.7.3 SVM Periodic Monitoring ........................................................ 39
4.1.7.4 First Boot Power Up .......................................................... 39
4.1.7.5 Brownout Detector ........................................................... 40
4.1.8 Trickle Charger .................................................................. 40
4.1.8.1 Trickle Charger Configuration ..................................................... 40
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4.1.9 Low-Dropout Regulators (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.9.1 1.8V LDO ............................................................... 41
4.1.9.2 3.3V USB LDO ............................................................. 41
4.1.10 Reset Pins .................................................................... 42
4.1.11 Power Pins .................................................................... 42
4.1.12 Registers (PWRMAN) ............................................................... 43
4.1.12.1 Module PWRMAN Registers ...................................................... 43
4.1.13 Registers (PWRSEQ) ............................................................... 70
4.1.13.1 Module PWRSEQ Registers ...................................................... 70
4.2 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.3 Resets and Reset Sources ................................................................ 102
4.3.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.3.2 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.3.3 RTC POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4 Registers (IOMAN) .................................................................... 103
4.4.1 Module IOMAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.1.1 IOMAN_WUD_REQ0 ......................................................... 105
4.4.1.2 IOMAN_WUD_REQ1 ......................................................... 106
4.4.1.3 IOMAN_WUD_ACK0 ......................................................... 107
4.4.1.4 IOMAN_WUD_ACK1 ......................................................... 108
4.4.1.5 IOMAN_ALI_REQ0 .......................................................... 109
4.4.1.6 IOMAN_ALI_REQ1 .......................................................... 110
4.4.1.7 IOMAN_ALI_ACK0 ........................................................... 111
4.4.1.8 IOMAN_ALI_ACK1 ........................................................... 112
4.4.1.9 IOMAN_SPI0_REQ .......................................................... 113
4.4.1.10 IOMAN_SPI0_ACK .......................................................... 116
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4.4.1.11 IOMAN_SPI1_REQ .......................................................... 119
4.4.1.12 IOMAN_SPI1_ACK .......................................................... 122
4.4.1.13 IOMAN_SPI2_REQ .......................................................... 124
4.4.1.14 IOMAN_SPI2_ACK .......................................................... 127
4.4.1.15 IOMAN_UART0_REQ ......................................................... 130
4.4.1.16 IOMAN_UART0_ACK ......................................................... 131
4.4.1.17 IOMAN_UART1_REQ ......................................................... 132
4.4.1.18 IOMAN_UART1_ACK ......................................................... 133
4.4.1.19 IOMAN_I2CM0_REQ ......................................................... 134
4.4.1.20 IOMAN_I2CM0_ACK ......................................................... 135
4.4.1.21 IOMAN_I2CS0_REQ .......................................................... 136
4.4.1.22 IOMAN_I2CS0_ACK .......................................................... 136
4.4.1.23 IOMAN_LCD_COM_REQ ....................................................... 137
4.4.1.24 IOMAN_LCD_COM_ACK ....................................................... 137
4.4.1.25 IOMAN_LCD_SEG_REQ0 ....................................................... 137
4.4.1.26 IOMAN_LCD_SEG_REQ1 ....................................................... 145
4.4.1.27 IOMAN_LCD_SEG_ACK0 ....................................................... 147
4.4.1.28 IOMAN_LCD_SEG_ACK1 ....................................................... 155
4.4.1.29 IOMAN_CRNT_REQ .......................................................... 157
4.4.1.30 IOMAN_CRNT_ACK .......................................................... 158
4.4.1.31 IOMAN_CRNT_MODE ......................................................... 160
4.4.1.32 IOMAN_ALI_CONNECT0 ....................................................... 161
4.4.1.33 IOMAN_ALI_CONNECT1 ....................................................... 161
4.4.1.34 IOMAN_I2CM1_REQ ......................................................... 161
4.4.1.35 IOMAN_I2CM1_ACK ......................................................... 162
4.4.1.36 IOMAN_PADX_CONTROL ...................................................... 162
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5 Pin Configurations, Packages, and Special Function Multiplexing 165
5.1 Pin Layout ......................................................................... 165
5.2 Pin Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.2.1 Compact Package GPIO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.2.2 Standard Package GPIO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.3 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.4 GPIO Pins and Peripheral Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.5 Registers (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.5.1 Module GPIO Registers .............................................................. 180
5.5.1.1 GPIO_FREE_Pn ............................................................ 183
5.5.1.2 GPIO_OUT_MODE_Pn ........................................................ 184
5.5.1.3 GPIO_OUT_VAL_Pn ......................................................... 185
5.5.1.4 GPIO_FUNC_SEL_Pn ......................................................... 185
5.5.1.5 GPIO_IN_MODE_Pn ......................................................... 189
5.5.1.6 GPIO_IN_VAL_Pn ........................................................... 190
5.5.1.7 GPIO_INT_MODE_Pn ......................................................... 191
5.5.1.8 GPIO_INTFL_Pn ............................................................ 191
5.5.1.9 GPIO_INTEN_Pn ........................................................... 192
6 Peripheral Management Unit (PMU) 193
6.1 Overview ......................................................................... 193
6.2 PMU Operation ...................................................................... 195
6.2.1 PMU Channel Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.2.2 PMU Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3 PMU Programming Details ................................................................ 196
6.3.1 PMU Op Code: MOVE (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.3.2 PMU Op Code: WRITE (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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6.3.3 PMU Op Code: WAIT (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.4 PMU Op Code: JUMP (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.5 PMU Op Code: LOOP (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.6 PMU Op Code: POLL (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.3.7 PMU Op Code: BRANCH (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.3.8 PMU Op Code: TRANSFER (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.4 Registers (PMU) ...................................................................... 208
6.4.1 Module PMU Registers .............................................................. 208
6.4.1.1 PMUn_DSCADR ............................................................ 210
6.4.1.2 PMUn_CFG .............................................................. 211
6.4.1.3 PMUn_LOOP ............................................................. 214
6.4.1.4 PMUn_OP ............................................................... 214
6.4.1.5 PMUn_DSC1 .............................................................. 215
6.4.1.6 PMUn_DSC2 .............................................................. 215
6.4.1.7 PMUn_DSC3 .............................................................. 215
6.4.1.8 PMUn_DSC4 .............................................................. 215
7 Communication Peripherals 216
7.1 I²C ............................................................................. 216
7.1.1 I²C Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.1.2 I²C Features .................................................................... 216
7.1.3 I²C Port and Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.1.3.1 Compact Layout (7mm x 7mm) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.1.3.2 Standard Layout (12mm x 12mm) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.1.4 I²C Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7.1.5 Protocol ...................................................................... 223
7.1.6 Peripheral Clock Selection and Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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7.1.6.1 Peripheral Clock Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.1.7 Communication and Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.1.7.1 FIFO-Based I²C Master ........................................................ 228
7.1.8 Registers (I2CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.1.8.1 Module I2CM Registers ........................................................ 230
7.1.9 Registers (I2CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
7.1.9.1 Module I2CS Registers ........................................................ 240
7.2 SPI ............................................................................. 256
7.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.2.2 SPI Port and Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.2.2.1 Compact Layout (7mm x 7mm) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.2.2.2 Standard Layout (12mm x 12mm) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.2.3 Clock Selection and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
7.2.3.1 Clock Gating .............................................................. 263
7.2.4 Configuration Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
7.2.4.1 Static Configuration .......................................................... 264
7.2.4.2 Dynamic Configuration ......................................................... 264
7.2.5 SPI Fast Mode .................................................................. 267
7.2.6 Communication and Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.2.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
7.2.8 SPI: FIFOs .................................................................... 268
7.2.9 Registers (SPI) .................................................................. 269
7.2.9.1 Module SPI Registers ......................................................... 269
7.3 UART ........................................................................... 283
7.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.3.2 UART Port and Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
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7.3.2.1 Compact Layout Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.3.2.2 Standard Layout Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.3.3 Port Register Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.3.4 UART Clock Selection and Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.3.5 Format and Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.3.6 Transferring and Receiving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
7.3.7 UART: Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
7.3.8 Hardware Flow Control .............................................................. 288
7.3.8.1 Clear to Send ............................................................. 288
7.3.8.2 Ready to Send ............................................................. 289
7.3.9 Registers (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
7.3.9.1 Module UART Registers ........................................................ 289
7.4 USB Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
7.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
7.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
7.4.2.1 USB Reset Definitions ......................................................... 301
7.4.3 USB Endpoints .................................................................. 302
7.4.3.1 Endpoint Control Register ....................................................... 303
7.4.3.2 Endpoint Buffer Descriptor ....................................................... 304
7.4.4 Registers (USB) .................................................................. 305
7.4.4.1 Module USB Registers ......................................................... 305
8 Analog Front End 340
8.1 AFE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
8.1.1 AFE Analog Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
8.2 AFE Reconfiguration Matrix ................................................................ 342
8.2.1 AFE Reconfiguration Matrix Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
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8.2.1.1 DAC .................................................................. 350
8.2.1.2 Op Amps ................................................................ 350
8.2.1.3 Comparators .............................................................. 351
8.2.2 Registers (AFE) .................................................................. 353
8.2.2.1 Module AFE Registers ......................................................... 353
8.3 ADC ............................................................................ 403
8.3.1 ADC Overview .................................................................. 403
8.3.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
8.3.3 ADC Operation .................................................................. 405
8.3.4 ADC Configuration ................................................................ 406
8.3.4.1 Peripheral Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
8.3.4.2 Reference Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
8.3.4.3 Input Modes .............................................................. 409
8.3.4.4 Input Multiplexer ............................................................ 410
8.3.4.5 Scan Modes .............................................................. 413
8.3.4.6 Interrupts ................................................................ 414
8.3.4.7 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
8.3.4.8 Sample Rate Calculation ........................................................ 417
8.3.4.9 Start the Measurement ........................................................ 422
8.3.5 Registers (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
8.3.5.1 Module ADC Registers ......................................................... 422
8.4 DAC ............................................................................ 451
8.4.1 DAC Overview .................................................................. 451
8.4.2 DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
8.4.3 DAC Operation .................................................................. 453
8.4.3.1 Common DAC Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
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8.4.3.2 Individual DAC Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
8.4.3.3 DAC Voltage Generation ........................................................ 459
8.4.4 Additional Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
8.4.4.1 Reduced Power Level Modes for 12-bit DAC Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
8.4.4.2 Correcting for Distortion at High Output Frequency .......................................... 461
8.4.5 Registers (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
8.4.5.1 Module DAC Registers ......................................................... 462
8.5 LED ............................................................................ 470
8.5.1 LED Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
8.5.1.1 LED Driver Details ........................................................... 471
8.5.2 LED Configuration ................................................................ 472
8.5.2.1 Basic LED Configuration ........................................................ 473
8.5.2.2 Multiple LED Configuration ...................................................... 474
8.5.2.3 H-bridge LED Configuration ...................................................... 475
8.5.2.4 Independent Loop H-bridge LED Configuration ............................................ 476
8.5.2.5 Integrated Feedback Loops LED Configuration ............................................ 477
8.5.2.6 Internal Feedback with Common Sense Resistor LED Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
8.5.2.7 Double H-bridge LED Configuration .................................................. 479
8.5.2.8 Multiple High Voltage LED Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
8.5.2.9 3x3 LED Matrix Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
8.5.3 Register Configurations .............................................................. 482
8.5.3.1 Current Mode Request ......................................................... 482
8.5.4 Control Loop Setup ................................................................ 485
8.5.5 Fault Detection Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
8.5.6 Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
8.5.7 Considerations .................................................................. 487
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8.5.7.1 Design Current ............................................................. 487
8.5.7.2 Average and Peak Current ....................................................... 487
9 Pulse Train Engine 489
9.1 Pulse Train Engine (PTE) Overview ............................................................ 489
9.2 Output Mode Selection .................................................................. 489
9.3 Pulse Train Peripheral Clock Rate Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
9.4 Enabling and Disabling Pulse Train Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
9.4.1 Master Enable/Disable .............................................................. 490
9.4.2 Enabling and Disabling Individual Pulse Train Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
9.5 Pulse Train Engine Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
9.5.1 Pulse Train Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
9.5.2 Square Wave Mode ................................................................ 492
9.6 Synchronization ...................................................................... 492
9.7 Registers (PT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.7.1 Module PT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.7.1.1 PTG_CTRL .............................................................. 494
9.7.1.2 PTG_RESYNC ............................................................. 494
9.7.1.3 PTn_RATE_LENGTH ......................................................... 496
9.7.1.4 PTn_TRAIN .............................................................. 496
10 System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 498
10.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
10.1.1 System Clocks Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
10.1.1.1 External High-Frequency Crystal Oscillator .............................................. 500
10.1.1.2 32kHz Crystal Oscillator ........................................................ 500
10.1.1.3 48MHz USB Clock PLL ........................................................ 500
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10.1.1.4 48MHz Internal 24MHz Trimmed Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
10.1.1.5 Cryptographic Internal Oscillator .................................................... 500
10.1.2 System Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
10.1.3 System Clock Sources .............................................................. 501
10.1.3.1 External Clock ............................................................. 502
10.1.3.2 External High Frequency Clock (Crystal or Resonator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
10.1.3.3 External 32kHz Clock (Crystal or Resonator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
10.1.3.4 Phase Lock Loop ........................................................... 505
10.1.3.5 Relaxation Oscillator .......................................................... 507
10.1.3.6 Crypto Clock Relaxation Oscillator .................................................. 508
10.1.4 ADC Clock Source Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
10.1.5 Registers (CLKMAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
10.1.5.1 Module CLKMAN Registers ...................................................... 510
10.2 Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
10.2.1 Watchdog Timers Overview ............................................................ 555
10.2.2 Clock Source Selection and Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
10.2.3 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
10.2.3.1 Locking and Unlocking the Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
10.2.3.2 Enabling and Disabling the Watchdog Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
10.2.4 Watchdog Timer Operation ............................................................ 557
10.2.5 Registers (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
10.2.5.1 Module WDT Registers ........................................................ 557
10.3 Real Time Clock (RTC) .................................................................. 563
10.3.1 Real Time Clock Overview ............................................................ 563
10.3.1.1 Real Time Clock Features ....................................................... 563
10.3.2 RTC Resets .................................................................... 564
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10.3.3 RTC Interrupts .................................................................. 564
10.3.4 RTC Configuration ................................................................ 565
10.3.5 Registers (RTCTMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
10.3.5.1 Module RTCTMR Registers ...................................................... 568
10.3.6 Registers (RTCCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
10.3.6.1 Module RTCCFG Registers ...................................................... 582
10.4 Timers/Counters ...................................................................... 585
10.4.1 Timers/Counters Overview ............................................................ 586
10.4.2 32-bit Mode Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
10.4.2.1 One-Shot Mode ............................................................ 588
10.4.2.2 Continuous Mode ........................................................... 589
10.4.2.3 Counter Mode ............................................................. 590
10.4.2.4 PWM Mode .............................................................. 591
10.4.2.5 Capture Mode ............................................................. 593
10.4.2.6 Compare Mode ............................................................ 593
10.4.2.7 Gated Mode .............................................................. 594
10.4.2.8 Capture/Compare Mode ........................................................ 595
10.4.3 16 bit Mode Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
10.4.3.1 One-Shot Mode ............................................................ 597
10.4.3.2 Continuous Mode ........................................................... 597
10.4.4 Registers (TMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
10.4.4.1 Module TMR Registers ........................................................ 598
11 Trust Protection Unit (TPU) 608
11.1 AES Cryptographic Engine ................................................................ 608
11.1.1 Registers (AES) .................................................................. 608
11.1.1.1 Module AES Registers ......................................................... 608
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11.2 Modular Arithmetic Accelerator (MAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
11.2.1 Registers (MAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
11.2.1.1 Module MAA Registers ........................................................ 618
11.3 Registers (TPU) ...................................................................... 626
11.3.1 Module TPU Registers .............................................................. 626
11.3.1.1 TPU_PRNG_USER_ENTROPY .................................................... 626
11.3.1.2 TPU_PRNG_RND_NUM ........................................................ 627
11.3.1.3 TPU_TSR_STATUS .......................................................... 627
11.3.1.4 TPU_TSR_CTRL0 ........................................................... 627
11.3.1.5 TPU_TSR_CTRL1 ........................................................... 629
11.3.1.6 TPU_TSR_SKS0 ............................................................ 630
11.3.1.7 TPU_TSR_SKS1 ............................................................ 630
11.3.1.8 TPU_TSR_SKS2 ............................................................ 630
11.3.1.9 TPU_TSR_SKS3 ............................................................ 630
12 CRC16 and CRC32 Hardware Accelerator 631
12.1 Overview ......................................................................... 631
12.2 CRC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
12.3 CRC Operation ...................................................................... 631
12.4 CRC-16-CCITT Example Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
12.5 CRC-32 Example Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
12.6 Registers (CRC) ...................................................................... 632
12.6.1 Module CRC Registers .............................................................. 632
12.6.1.1 CRC_RESEED ............................................................. 633
12.6.1.2 CRC_SEED16 ............................................................. 633
12.6.1.3 CRC_SEED32 ............................................................. 634
12.6.1.4 CRC_DATA_VALUE16 ........................................................ 634
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12.6.1.5 CRC_DATA_VALUE32 ........................................................ 634
13 LCD Controller 635
13.1 LCD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
13.2 LCD Operation ...................................................................... 636
13.3 LCD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
13.3.1 LCD Clock .................................................................... 637
13.3.2 LCD Power Control ................................................................ 637
13.3.3 LCD Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
13.3.4 LCD Internal Register Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
13.3.5 LCD Port Configuration .............................................................. 640
13.3.6 LCD Memory Configuration ............................................................ 641
13.4 Registers (LCD) ...................................................................... 642
13.4.1 Module LCD Registers .............................................................. 642
13.4.1.1 LCD_LCFG .............................................................. 642
13.4.1.2 LCD_LCRA .............................................................. 644
13.4.1.3 LCD_LPCF ............................................................... 646
13.4.1.4 LCD_LCADDR ............................................................. 646
13.4.1.5 LCD_LCDATA ............................................................. 647
13.4.1.6 LCD_LPWRCTRL ........................................................... 647
14 Flash Controller and Instruction Cache 650
14.1 Registers (FLC) ...................................................................... 650
14.1.1 Module FLC Registers .............................................................. 650
14.1.1.1 FLC_FADDR .............................................................. 651
14.1.1.2 FLC_FCKDIV ............................................................. 651
14.1.1.3 FLC_CTRL ............................................................... 652
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14.1.1.4 FLC_INTR ............................................................... 655
14.1.1.5 FLC_FDATA .............................................................. 656
14.1.1.6 FLC_PERFORM ............................................................ 656
14.1.1.7 FLC_STATUS ............................................................. 657
14.1.1.8 FLC_SECURITY ............................................................ 658
14.1.1.9 FLC_BYPASS ............................................................. 659
14.1.1.10 FLC_USER_OPTION ......................................................... 660
14.1.1.11 FLC_CTRL2 .............................................................. 661
14.1.1.12 FLC_INTFL1 .............................................................. 662
14.1.1.13 FLC_INTEN1 .............................................................. 663
14.1.1.14 FLC_DISABLE_XR0 .......................................................... 663
14.1.1.15 FLC_DISABLE_XR1 .......................................................... 664
14.1.1.16 FLC_DISABLE_XR2 .......................................................... 664
14.1.1.17 FLC_DISABLE_XR3 .......................................................... 665
14.1.1.18 FLC_DISABLE_WE0 ......................................................... 665
14.1.1.19 FLC_DISABLE_WE1 ......................................................... 666
14.1.1.20 FLC_DISABLE_WE2 ......................................................... 666
14.1.1.21 FLC_DISABLE_WE3 ......................................................... 666
14.2 Registers (ICC) ...................................................................... 667
14.2.1 Module ICC Registers .............................................................. 667
14.2.1.1 ICC_ID ................................................................. 667
14.2.1.2 ICC_MEM_CFG ............................................................ 668
14.2.1.3 ICC_CTRL_STAT ........................................................... 668
14.2.1.4 ICC_INVDT_ALL ............................................................ 669
Rev.1.3 April 2015 Maxim Integrated Page 1

MAX32600 User’s Guide Main Page
1 Main Page
1.1 Legal Disclaimer
LIFE SUPPORT POLICY
MAXIM’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF MAXIM INTEGRATED PRODUCTS, INC.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical
component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system or to affect its safety or effectiveness.
Document Disclaimer
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suggest possible uses and may be superseded. MAXIM INTEGRATED PRODUCTS, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTAT−
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Copyright
2015 Maxim Integrated
1.2 Revision Information
Version Section Changes
1.2 Initial Public Release
1.3 2.2.6 Added the JTAG TAP device ID value.
4.4.1.36 IOMAN_PADX_CONTROL: Changed "three-state" to "High Impedance" when describing pin driver output states.
Rev.1.3 April 2015 Maxim Integrated Page 2