Maxim Integrated MAX32660 User manual

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MAX32660 USER GUIDE
UG6659; Rev 0; 7/18
Abstract: This user guide provides application developers information on how to use the memory and
peripherals of the MAX32660 microcontroller. Detailed information for all registers and fields in the
device are covered. Guidance is given for managing the clocks, power and initialization of the product.

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Table of Contents
1 Introduction................................................................................................................................................. 13
2 Overview...................................................................................................................................................... 13
3 Memory, Register Mapping, and Access ..................................................................................................... 15
4 System Clocks, Reset, and Power Management ......................................................................................... 21

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5 Flash Controller ........................................................................................................................................... 51
6 General-Purpose I/O and Alternate Function Pins...................................................................................... 58
7 DMA Controller............................................................................................................................................ 71

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8 UART............................................................................................................................................................ 84
9 Real-Time Clock (RTC).................................................................................................................................. 96
10 Timers................................................................................................................................................... 105

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11 Watchdog Timer (WDT) ....................................................................................................................... 126
12 I2C Master/Slave Serial Controller........................................................................................................ 131

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13 Serial Peripheral Interface 0 (SPI0) ...................................................................................................... 159
14 SPIMSS (SPI1/I2S).................................................................................................................................. 178

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15 Trademarks .......................................................................................................................................... 195
16 Revision History.................................................................................................................................... 195

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List of Figures
Figure 2-1: MAX32660 High Level Block Diagram ................................................................................................... 14
Figure 3-1: Code Memory Mapping ........................................................................................................................ 15
Figure 3-2: Data Memory Map ................................................................................................................................ 16
Figure 4-1: Clock Tree Diagram ............................................................................................................................... 24
Figure 7-1: DMAC Block Diagram ............................................................................................................................ 71
Figure 9-1. RTC Block Diagram ................................................................................................................................ 97
Figure 10-1: One-Shot Mode Diagram .................................................................................................................. 107
Figure 10-2: Continuous Mode Diagram ............................................................................................................... 109
Figure 10-3: Counter Mode Diagram..................................................................................................................... 111
Figure 10-4: Capture Mode Diagram..................................................................................................................... 115
Figure 10-5: Counter Mode Diagram..................................................................................................................... 117
Figure 10-6: Gated Mode Diagram........................................................................................................................ 119
Figure 11-1: Watchdog Timer Block Diagram........................................................................................................ 126
Figure 12-1: The Roles of I2C Devices and the Direction the I2C Signals................................................................ 132
Figure 12-2: I2C Write Data Transfer ..................................................................................................................... 134
Figure 12-3: I2C Specification Minimum and Maximum Clock Parameters for Standard and Fast Mode ............ 136
Figure 12-4: I2C Clock Period ................................................................................................................................. 142
Figure 13-1: SPI0 Block Diagram............................................................................................................................ 159
Figure 13-2: 4-Wire SPI Connection Diagram........................................................................................................ 160
Figure 13-3: 3-Wire SPI Connection Diagram........................................................................................................ 161
Figure 13-4: SCK Clock Rate Control...................................................................................................................... 163
Figure 13-5: SPI Clock Polarity............................................................................................................................... 164
Figure 13-6. SPI Timing (SPI0_CTRL2.clk_pha = 0)................................................................................................. 165
Figure 13-7. SPI Timing (SPI0_CTRL2.clk_pha = 1)................................................................................................. 166
Figure 13-8: Three-Wire SPI Read ......................................................................................................................... 167
Figure 13-9: Three-Wire SPI Write ........................................................................................................................ 167
Figure 14-1. SPIMSS Block Diagram....................................................................................................................... 179
Figure 14-2: 4-Wire SPI Connection Diagram........................................................................................................ 180
Figure 14-3: I2S Audio Data in Standard I2S Operation.......................................................................................... 186
Figure 14-4: I2S Mode (i2s_en=1, i2s_lj=1)............................................................................................................ 186

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List of Tables
Table 3-1: APB Peripheral Base Address Map......................................................................................................... 19
Table 4-1: Operating Voltage Range Selection and the Effect on VCORE and fHFIO .................................................... 21
Table 4-2: Minimum Flash Wait State Setting for Each OVR Setting (fSYSCLK = fHFIO)................................................. 23
Table 4-3: Reset Sources and Effect on Oscillator Status........................................................................................ 25
Table 4-4: Reset Sources and Effect on System Oscillator Selection and Prescaler................................................ 25
Table 4-5: Wake-Up Sources for Each Low-Power Mode........................................................................................ 28
Table 4-6: Reset and Low Power Mode Effects....................................................................................................... 29
Table 4-7: Instruction Cache Controller Register Addresses and Descriptions....................................................... 31
Table 4-8: ICC Cache ID Register.............................................................................................................................. 31
Table 4-9: ICC Memory Size Register....................................................................................................................... 31
Table 4-10: ICC Cache Control Register................................................................................................................... 32
Table 4-11: ICC Invalidate Register.......................................................................................................................... 32
Table 4-12: Global Control Registers, Offsets and Descriptions.............................................................................. 33
Table 4-13: System Control Register ....................................................................................................................... 33
Table 4-14: Reset 0 Register.................................................................................................................................... 34
Table 4-15: System Clock Control Register.............................................................................................................. 36
Table 4-16: Power Management Register............................................................................................................... 38
Table 4-17: Peripheral Clock Disable 0 Register...................................................................................................... 38
Table 4-18: Memory Clock Control Register ........................................................................................................... 40
Table 4-19: Memory Zeroization Control Register.................................................................................................. 42
Table 4-20: System Status Flag Register.................................................................................................................. 42
Table 4-21: Reset Register 1.................................................................................................................................... 43
Table 4-22: Peripheral Clock Disable Register 1...................................................................................................... 43
Table 4-23: Event Enable Register........................................................................................................................... 44
Table 4-24: Revision Register .................................................................................................................................. 44
Table 4-25: System Status Interrupt Enable Register.............................................................................................. 44
Table 4-26: System Initialization Registers, Offsets and Descriptions .................................................................... 44
Table 4-27: Function Control Register 0.................................................................................................................. 45
Table 4-28: System Initialization Address Error Register ........................................................................................ 45
Table 4-29: Function Control Registers, Offsets and Descriptions.......................................................................... 45
Table 4-30: Function Control Register 0.................................................................................................................. 45
Table 4-31: Power Sequencer Low Power Control Registers, Offsets, Access and Descriptions ............................ 46
Table 4-32: Low Power Voltage Control Register.................................................................................................... 47
Table 4-33: Low Power Mode Wakeup Flags for GPIO0 ......................................................................................... 49
Table 4-34: Low Power Wakeup Enable for GPIO0 Register................................................................................... 49
Table 4-35: RAM Shut Down Register ..................................................................................................................... 49
Table 5-1: Internal Flash Memory Organization...................................................................................................... 51
Table 5-2: Valid Addresses for 32-bit and 128-bit Internal Flash Writes ................................................................ 52
Table 5-3: Page Boundary Address Range for Page Erase Operations.................................................................... 53
Table 5-4: Flash Controller Registers, Offsets, Access and Descriptions................................................................. 54
Table 5-5: Flash Controller Interrupt Register......................................................................................................... 56
Table 5-6: Flash Controller Data Register 0............................................................................................................. 57
Table 5-7: Flash Controller Data Register 1............................................................................................................. 57
Table 5-8: Flash Controller Data Register 2............................................................................................................. 57
Table 5-9: Flash Controller Data Register 3............................................................................................................. 57
Table 6-1: GPIO Port, Pin Name and Alternate Function Matrix, 16-WLP .............................................................. 59

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Table 6-2: GPIO Port, Pin Name and Alternate Function Matrix, 20-TQFN ............................................................ 59
Table 6-3: Standard GPIO Drive Strength Selection ................................................................................................ 61
Table 6-4: GPIO with I2C Alternate Function Drive Strength Selection ................................................................... 61
Table 6-5: GPIO Mode and Alternate Function Selection ....................................................................................... 61
Table 6-6: GPIO Port Interrupt Vector Mapping ..................................................................................................... 62
Table 6-7: GPIO Wakeup Interrupt Vector .............................................................................................................. 62
Table 6-8: GPIO Port 0 Registers ............................................................................................................................. 63
Table 6-9: GPIO Alternate Function 0 Select Register............................................................................................. 63
Table 6-10: GPIO Output Enable Register ............................................................................................................... 64
Table 6-11: GPIO Output Register ........................................................................................................................... 64
Table 6-12: GPIO Input Register .............................................................................................................................. 65
Table 6-13: GPIO Port Interrupt Mode Register...................................................................................................... 65
Table 6-14: GPIO Port Interrupt Polarity Registers ................................................................................................. 65
Table 6-15: GPIO Port Interrupt Enable Registers................................................................................................... 65
Table 6-16: GPIO Interrupt Flag Register................................................................................................................. 66
Table 6-17: GPIO Wakeup Enable Registers............................................................................................................ 66
Table 6-18: GPIO Interrupt Dual Edge Mode Registers........................................................................................... 66
Table 6-19: GPIO Pullup/Pulldown Enable Register ................................................................................................ 67
Table 6-20: GPIO Alternate Function Select Register.............................................................................................. 67
Table 6-21: GPIO Input Hysteresis Enable Register................................................................................................. 67
Table 6-22: GPIO Slew Rate Enable Register ........................................................................................................... 67
Table 6-23: GPIO Drive Strength 0 Select Register.................................................................................................. 68
Table 6-24: GPIO Drive Strength 1 Select Register.................................................................................................. 69
Table 6-25: GPIO Pullup/Pulldown Select Register ................................................................................................. 70
Table 7-1: DMA Channel Registers .......................................................................................................................... 71
Table 7-2: Channel Reload Registers ....................................................................................................................... 72
Table 7-3: Source and Destination Address Definition ........................................................................................... 73
Table 7-4: Data movement from source to DMA FIFO............................................................................................ 73
Table 7-5: Data movement from the DMA FIFO to destination.............................................................................. 74
Table 7-6: Standard DMA Control Registers, Offsets, Access and Descriptions...................................................... 77
Table 7-7: DMA Interrupt Enable Register .............................................................................................................. 77
Table 7-8: DMA Interrupt Flag Register................................................................................................................... 77
Table 7-9: Standard DMA Channel 0 to Channel 15 Offsets ................................................................................... 78
Table 7-10: DMAn Channel Registers, Offsets, Access and Descriptions................................................................ 78
Table 7-11: DMA Configuration Register................................................................................................................. 79
Table 7-12: DMA Status Register............................................................................................................................. 81
Table 7-13: DMA Source Register............................................................................................................................ 82
Table 7-14: DMA Destination Register .................................................................................................................... 82
Table 7-15: DMA Count Register ............................................................................................................................. 82
Table 7-16: DMA Source Reload Register................................................................................................................ 83
Table 7-17: DMA Destination Reload Register........................................................................................................ 83
Table 7-18: DMA Count Reload Register................................................................................................................. 83
Table 8-1: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps, fPCLK=48MHz................................ 86
Table 8-2: UART Registers, Offset Addresses and Descriptions .............................................................................. 87
Table 8-3: UART Control 0 Register ......................................................................................................................... 87
Table 8-4: UART Control 1 Register ......................................................................................................................... 89
Table 8-5: UART Status Register.............................................................................................................................. 90
Table 8-6: UART Interrupt Enable Register ............................................................................................................. 91

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Table 8-7: UART Interrupt Flags Register ................................................................................................................ 92
Table 8-8: UART Rate Integer Register .................................................................................................................... 93
Table 8-9: UART Baud Rate Decimal Register.......................................................................................................... 93
Table 8-10: UART FIFO Register............................................................................................................................... 94
Table 8-11: UART DMA Configuration Register....................................................................................................... 94
Table 8-12: UART TX FIFO Data Output Register..................................................................................................... 94
Table 9-1. RTC Registers, Offsets and Descriptions............................................................................................... 100
Table 9-2: RTC Seconds Counter Register ............................................................................................................. 100
Table 9-3: RTC Sub-Seconds Counter Register ...................................................................................................... 101
Table 9-4: RTC Sub-Seconds Counter Register ...................................................................................................... 101
Table 9-5: RTC Sub-Second Alarm Register ........................................................................................................... 101
Table 9-6: RTC Control Register............................................................................................................................. 101
Table 9-7: RTC Trim Register ................................................................................................................................. 103
Table 10-1: Timer Register Offsets, Names, Access and Descriptions .................................................................. 122
Table 10-2: Timer Count Registers ........................................................................................................................ 122
Table 10-3: Timer Compare Registers ................................................................................................................... 122
Table 10-4: Timer PWM Registers......................................................................................................................... 123
Table 10-5: Timer Interrupt Registers ................................................................................................................... 123
Table 10-6: Timer Control Registers...................................................................................................................... 123
Table 11-1: Watchdog Timer Interrupt Period with fSYSCLK = 96MHz and fPCLK = 48MHz........................................ 127
Table 11-2: Watchdog Timer Registers ................................................................................................................. 129
Table 11-3: Watchdog Timer Control Register...................................................................................................... 129
Table 11-4: Watchdog Timer Reset Register......................................................................................................... 130
Table 12-1: I2C Bus Terminology............................................................................................................................ 131
Table 12-2: I2C Address Byte Format..................................................................................................................... 138
Table 12-3: I2C Registers........................................................................................................................................ 144
Table 12-4: I2C Control Registers 0........................................................................................................................ 145
Table 12-5: I2C Status Registers............................................................................................................................. 147
Table 12-6: I2C Interrupt Status Flags Registers 0 ................................................................................................. 148
Table 12-7: I2C Interrupt Enable 0 Registers.......................................................................................................... 150
Table 12-8: I2C Interrupt Status Flags 1 Registers ................................................................................................. 151
Table 12-9: I2C Interrupt Enable Registers 1.......................................................................................................... 151
Table 12-10: I2C FIFO Length Registers.................................................................................................................. 152
Table 12-11: I2C Receive Control Registers 0......................................................................................................... 152
Table 12-12: I2C Receive Control 1 Registers......................................................................................................... 153
Table 12-13: I2C Transmit Control Registers 0....................................................................................................... 153
Table 12-14: I2C Transmit Control Registers 1....................................................................................................... 154
Table 12-15: I2C Data Registers ............................................................................................................................. 155
Table 12-16: I2C Master Mode Control Registers.................................................................................................. 155
Table 12-17: I2C SCL Low Control Register ............................................................................................................ 156
Table 12-18: I2C SCL High Control Register............................................................................................................ 156
Table 12-19: I2C Timeout Registers ....................................................................................................................... 156
Table 12-20: I2C Timeout Registers ....................................................................................................................... 157
Table 12-21: I2C Slave Address Register ................................................................................................................ 157
Table 12-22: I2C DMA Register .............................................................................................................................. 158
Table 13-1: Four-Wire SPI Signals.......................................................................................................................... 160
Table 13-2: Three-Wire SPI Signals........................................................................................................................ 161
Table 13-3: SPI0 Pins.............................................................................................................................................. 162

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Table 13-4. Clock Phase and Polarity Operation ................................................................................................... 164
Table 13-5: SPI0 Master Register Addresses and Descriptions ............................................................................. 169
Table 13-6: SPI FIFO Data Registers....................................................................................................................... 169
Table 13-7: SPI Master Signals Control Registers.................................................................................................. 169
Table 13-8: SPI Transmit Packet Size Register....................................................................................................... 171
Table 13-9: SPI Static Configuration Registers ...................................................................................................... 171
Table 13-10: SPI Slave Select Timing Register ....................................................................................................... 172
Table 13-11: SPI Master Clock Configuration Registers ........................................................................................ 172
Table 13-12: SPI DMA Control Registers ............................................................................................................... 173
Table 13-13: SPI Interrupt Flag Registers .............................................................................................................. 174
Table 13-14: SPI Interrupt Enable Registers.......................................................................................................... 176
Table 13-15: SPI Wakeup Status Flags Registers ................................................................................................... 177
Table 13-16: SPI Wakeup Enable Registers ........................................................................................................... 177
Table 13-17: SPI Status Registers .......................................................................................................................... 177
Table 14-1: Four-Wire SPI Signals.......................................................................................................................... 179
Table 14-2: I2S Signals............................................................................................................................................ 180
Table 14-3: SPIMSS Pins for SPI1 and I2S ............................................................................................................... 181
Table 14-4. Clock Phase and Polarity Operation ................................................................................................... 182
Table 14-5: SPIMSS Register Offsets, Access and Descriptions............................................................................. 189
Table 14-6. SPIMSS Data Register ......................................................................................................................... 189
Table 14-7: SPIMSS Control Register..................................................................................................................... 189
Table 14-8: SPIMSS Interrupt Flag Register........................................................................................................... 190
Table 14-9: SPIMSS Mode Register ....................................................................................................................... 191
Table 14-10: SPIMSS Bit Rate Generator Register................................................................................................. 192
Table 14-11: SPIMSS DMA Register....................................................................................................................... 192
Table 14-12: SPIMSS I2S Control Register.............................................................................................................. 194

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1Introduction
For ordering information, mechanical and electrical characteristics for the MAX32660 family of devices please refer to the
datasheet. For information on the Arm® Cortex®-M4 with FPU core, please refer to the Cortex-M4 with FPU Technical
Reference Manual.
1.1 Related Documentation
The MAX32660 datasheet and errata are available from the Maxim Integrated website, http://www.maximintegrated.com.
2Overview
The MAX32660 is an ultra-low power, cost effective highly integrated microcontroller designed for battery-powered devices
and wireless sensors. It combines a flexible and versatile power management unit with the powerful Arm Cortex-M4 with
FPU (Floating Point Unit). The device enables designs with complex sensor processing without compromising battery life. It
also offers legacy designs an easy and cost optimal upgrade path from 8 or 16-bit microcontrollers. The device integrates up
to 256KB of flash memory and 96KB of SRAM to accommodate application and sensor code.
The device features four powerful and flexible power modes. It can operate from a single supply battery voltage, or a dual
supply typically provided by a PMIC. The I2C (Inter-Integrated Circuit) port supports standard, fast, fast-plus and high-speed
modes operating up to 3400Kbps. The SPI ports can run up to 48MHz in both master and slave mode, and the UARTs can
run up to 4Mbps. Three general-purpose 32-bit timers, a watchdog timer, and a real-time clock are also provided. An
I2S (Inter-IC Sound) interface provides audio streaming to or from an external audio codec.

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Figure 2-1: MAX32660 High Level Block Diagram

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3Memory, Register Mapping, and Access
3.1 Overview
The Arm Cortex-M4 with FPU core defines a standard memory space for unified code and data access. This memory space is
addressed in units of single bytes but is most typically accessed in 32-bit (4 byte) units. It may also be accessed, depending
on the implementation, in 8-bit (1 byte) or 16-bit (2 byte) widths. The total range of the memory space is 32-bits in width
(4GB addressable total), from addresses 0x0000 0000 to 0xFFFF FFFF.
It is important to note, however, that the architectural definition does not require the entire 4GB memory range to be
populated with addressable memory instances.
Figure 3-1: Code Memory Mapping
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Figure 3-2: Data Memory Map
3.2 Standard Memory Regions
Many standard memory regions are defined for the Arm Cortex-M4 architecture; the use of many of these is optional for
the system integrator. At a minimum, the MAX32660 must contain code and data memory for application code, stack and
heap usage, as well as certain components which are part of the implemented architecture.
3.2.1 Code Space
The code space area of memory is designed to contain the primary memory used for code execution by the device. This
memory area is defined from byte address range 0x0000 0000 to 0x1FFF FFFF (0.5GB maximum). Two different standard
core bus masters are used by the Arm Cortex-M4 core and the Arm debugger to access this memory area. The I-Code AHB
bus master is used for instruction decode fetching from code memory, while the D-Code AHB bus master is used for data
fetches from code memory. This is arranged so that data fetches avoid interfering with instruction execution.
On the MAX32660, the code space memory area contains the main internal flash memory that typically contains the
instruction code that will be executed on the device. The internal flash memory is mapped into both code and data space
from 0x0000 0000 to 0x0003 FFFF. This program memory area must also contain the default system vector table and the
initial settings for all system exception handlers and interrupt handlers. The reset vector for the device is 0x0000 0000.
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MAX32660 User Guide
Maxim Integrated Page 17 of 195
3.2.2 SRAM Space
The SRAM area of memory is intended to contain the primary SRAM data memory of the device and is defined from byte
address range 0x2000 0000 to 0x3FFF FFFF (0.5GB maximum). This memory can be used for general purpose variable and
data storage, code execution, and the Arm Cortex-M4 stack.
On the MAX32660, this memory area contains the main system SRAM 96KB, which is mapped from 0x2000 0000 to
0x2001 7FFF.
The entirety of the SRAM memory space on the MAX32660 is contained within the dedicated Arm Cortex-M4 
SRAM bit-banding region from 0x2000 0000 to 0x200F FFFF (1MB maximum for bit-banding). This means that the CPU can
access the entire SRAM either using standard byte/word/doubleword access or using bit-banding operations. The bit-
banding mechanism allows any single bit of any given SRAM byte address location to be set, cleared, or read individually by
reading from or writing to a corresponding doubleword (32-bit wide) location in the bit-banding alias area.
The alias area for the SRAM bit-banding is located beginning at 0x2200 0000 and is a total of 32MB maximum, which allows
the entire 1MB bit banding area to be accessed. Each 32-bit (4 byte aligned) address location in the bit-banding alias area
translates into a single bit access (read or write) in the bit-banding primary area. Reading from the location performs a
single bit read, while writing either a 1 or 0 to the location performs a single bit set or clear.
Note: The Arm Cortex-M4 with FPU translates the access in the bit-banding alias area into the appropriate read cycle (for a
single bit read) or a read-modify-write cycle (for a single bit set or clear) of the bit-banding primary area. This means that
bit-banding is a core function (i.e., not a function of the SRAM memory interface layer or the AHB bus layer), and thus is only
applicable to accesses generated by the core itself. Reads/writes to the bit-banding alias area by other (non-Arm -core) bus
masters such as the Standard DMA AHB bus master will not trigger a bit-banding operation and will instead result in an AHB
bus error.
The SRAM area on the MAX32660 is capable code execution. Code stored in the SRAM is accessed directly for execution
using the system bus and is not cached. The SRAM is where the Arm Cortex-M4 stack must be located, as it is the only
general-purpose SRAM memory on the device. A valid stack location inside the SRAM must be set in the vector table stored
at address 0x0000 0000 in the internal flash memory. Refer to the Cortex-M4 with FPU Technical Reference Manual. The
MAX32660 specific AHB Bus Masters can also access the SRAM to use as general storage or working space.
3.2.3 Peripheral Space
The peripheral space area of memory is intended for mapping of control registers, internal buffers/working space, and
other features needed for the firmware control of non-core peripherals. It is defined from byte address range 0x4000 0000
to 0x5FFF FFFF (0.5GB maximum). On the MAX32660, all device-specific module registers are mapped to this memory area,
as well as any local memory buffers or FIFOs which are required by modules.
As with the SRAM region, there is a dedicated 1MB area at the bottom of this memory region (from 0x4000 0000 to
0x400F FFFF) that is used for bit-banding operations by the Arm Cortex-M4 with FPU. Four-byte-aligned read/write
operations in the peripheral bit-banding alias area (32MB in length, from 0x4200 0000 to 0x43FF FFFF) are translated by the
core into read/mask/shift or read/modify/write operation sequences to the appropriate byte location in the bit-banding
area.
Note: The bit-banding operation within peripheral memory space is, like bit-banding function in SRAM space, a core
remapping function. As such, it is only applicable to operations performed directly by the Arm Cortex-M4 core. If another
memory bus master (such as the Standard DMA AHB master) accesses the peripheral bit-banding alias region, the bit-
banding remapping operation will not take place. In this case, the bit-banding alias region will appear to be a non-
implemented memory area (causing an AHB bus error).

MAX32660 User Guide
Maxim Integrated Page 18 of 195
On the MAX32660, access to the region that contains most peripheral registers (0x4000 0000 to 0x400F FFFF) goes from the
AHB bus through an AHB-to-APB bridge. This allows the peripheral modules to operate on the slower, easier to handle APB
bus matrix. This also ensures that peripherals with slower response times do not tie up bandwidth on the AHB bus, which
must necessarily have a faster response time since it handles main application instruction and data fetching.
Note: The APB bus supports 32-bit width access only. All access to the APB peripheral register area (0x4000 0000 to
0x400F FFFF) must be 32-bit width only with 32-bit (4 byte) alignment. Access using 8-bit or 16-bit width to this memory
region is not supported and will result in an AHB memory fault exception (returned by the AHB-to-APB bridge interface).
3.2.4 System Area (Private Peripheral Bus)
The system area (private peripheral bus) memory space contains register areas for functions that are only accessible by the
Arm Cortex-M4 core itself (and the Arm debugger, in certain instances). It is defined from byte address range 0xE000 0000
to 0xE00F FFFF. This APB bus is restricted and can only be accessed by the Arm core and core-internal functions. It cannot
be accessed by other modules which implement AHB memory masters, such as the Standard DMA.
In addition to being restricted to the core, application code is only allowed to access this area when running in the
privileged execution mode (as opposed to the standard user thread execution mode). This helps ensure that critical system
settings controlled in this area are not altered inadvertently or by errant code that should not have access to this area.
Core functions controlled by registers mapped to this area include the SysTick timer, debug and tracing functions, the NVIC
(interrupt handler) controller, and the Flash Breakpoint controller.
3.3 Device Memory Instances
This section details physical memory instances on the MAX32660 (including internal flash memory and SRAM instances)
that are accessible as standalone memory regions using either the AHB or APB bus matrix. Memory areas which are only
accessible via FIFO interfaces, or memory areas consisting of only a few registers for a peripheral, are not covered here.
3.3.1 Main Program Flash Memory
The main program flash memory is 256KB in size and consists of 32 logical pages of 8KB each.
3.3.2 Instruction Cache Memory
The internal flash memory instruction cache is 16KB in size and is used to cache instructions fetched using the I-Code bus.
This includes instructions fetched from the internal flash memory. Note that the cache is used for instruction fetches only.
Data fetches (including code literal values) from the internal flash memory do not use the instruction cache.
3.3.3 System SRAM
The system SRAM is 96KB in size and can be used for general purpose data storage, the Arm system stack, USB data
transfers (endpoints), and Standard DMA operations, as well as code execution if desired.
3.3.4 AHB Bus Matrix and AHB Bus Interfaces
This section details memory accessibility on the AHB bus matrix and the organization of AHB master and slave instances.

MAX32660 User Guide
Maxim Integrated Page 19 of 195
3.3.5 Core AHB Interface
3.3.5.1 I-Code
This AHB master is used by the Arm core for instruction fetching from memory instances located in code space from byte
addresses 0x0000 0000 to 0x1FFF FFFF. This bus master is used to fetch instructions from the internal flash memory.
Instructions fetched by this bus master are returned by the instruction cache, which in turn triggers a cache line fill cycle to
fetch instructions from the internal flash memory when a cache miss occurs.
3.3.5.2 D-Code
This AHB master is used by the Arm Cortex-M4 with FPU core for data fetches from memory instances located in code space
from byte addresses 0x0000 0000 to 0x1FFF FFFF. The D-Code AHB master has access to the full internal flash memory.
3.3.5.3 System
This AHB master is used by the Arm core for all instruction fetches and data read and write operations involving the SRAM.
The APB mapped peripherals (through the AHB-to-APB bridge) and AHB mapped peripheral and memory areas are also
accessed using this bus master.
3.3.6 AHB Master
3.3.6.1 Standard DMA
The Standard DMA bus master has access to all off-core memory areas accessible by the System bus. It does not have
access to the Arm Private Peripheral Bus area.
3.4 Peripheral Register Map
Table 3-1, below, contains the base address for each of the APB mapped peripherals. The base address for a given
peripheral is the start of the register map for the peripheral. For a given peripheral, the address for a register within the
peripheral is defined as the peripheral base address 
Table 3-1: APB Peripheral Base Address Map
Peripheral
Peripheral
Register Prefix
Base Address
End Address
Global Control
GCR_
0x4000 0000
0x4000 03FF
System Interface
SIR_
0x4000 0400
0x4000 07FF
Function Control
FCR_
0x4000 0800
0x4000 0BFF
Watchdog Timer 0
WDT0_
0x4000 3000
0x4000 33FF
Real-Time Clock
RTC_
0x4000 6000
0x4000 63FF
Power Sequencer
PWRSEQ_
0x4000 6800
0x4000 6BFF
GPIO Port 0
GPIO0_
0x4000 8000
0x4000 8FFF
Timer 0
TMR0_
0x4001 0000
0x4001 0FFF
Timer 1
TMR1_
0x4001 1000
0x4001 1FFF
Timer 2
TMR2_
0x4001 2000
0x4001 2FFF
SPIMSS
SPIMSS_
0x4001 9000
0x4001 9FFF

MAX32660 User Guide
Maxim Integrated Page 20 of 195
Peripheral
Peripheral
Register Prefix
Base Address
End Address
I2C 0
I2C0_
0x4001 D000
0x4001 DFFF
I2C 1
I2C1_
0x4001 E000
0x4001 EFFF
Standard DMA
DMA_
0x4002 8000
0x4002 8FFF
Flash Controller
FLC_
0x4002 9000
0x4002 93FF
Internal Cache Controller
ICC_
0x4002 A000
0x4002 AFFF
UART 0
UART0_
0x4004 2000
0x4004 2FFF
UART 1
UART1_
0x4004 3000
0x4004 3FFF
SPI0
SPI0_
0x4004 6000
0x4004 6FFF