Maxim Integrated MAX32650 User manual

MAX32650–MAX32652 USER GUIDE
UG6766; Rev 0; 9/18
Abstract: This user guide provides application developers information on how to use the memory and
peripherals of the MAX32650MAX32652 microcontroller. Detailed information for all registers and fields in
the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the
device family.

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MAX32650–MAX32652 User Guide
Table of Contents
1Overview.................................................................................................................................23
1.1 Block Diagram ........................................................................................................................................ 24
2Memory, Register Mapping, and Access................................................................................26
2.1 Memory, Register Mapping, and Access Overview ............................................................................... 26
2.2 Standard Memory Regions..................................................................................................................... 28
Code Space.........................................................................................................................................................28
SRAM Space .......................................................................................................................................................29
Peripheral Space ................................................................................................................................................30
External RAM Space...........................................................................................................................................30
External Device Space........................................................................................................................................30
System Area (Private Peripheral Bus) ................................................................................................................31
System Area (Vendor Defined) ..........................................................................................................................31
2.3 Device Memory Instances...................................................................................................................... 31
Main Program Flash Memory ............................................................................................................................31
Cache Memories ................................................................................................................................................31
External Memory Cache Controller (EMCC).......................................................................................................31
Information Block Flash Memory.......................................................................................................................31
System SRAM .....................................................................................................................................................32
AES Key and Working Space Memory................................................................................................................32
MAA Key and Working Space Memory ..............................................................................................................32
TPU Memory ......................................................................................................................................................32
2.4 AHB Interfaces........................................................................................................................................ 32
Core AHB Interfaces...........................................................................................................................................32
AHB Masters ......................................................................................................................................................32
2.5 Peripheral Register Map ........................................................................................................................ 33
APB Peripheral Base Address Map.....................................................................................................................33
AHB Peripheral Base Address Map ....................................................................................................................35
3System Clocks, Reset, and Power Management....................................................................36
3.1 Oscillator Sources and Clock Switching.................................................................................................. 37
120MHz Internal Main High-Speed Oscillator ...................................................................................................37
40MHz Low Power Internal Oscillator ...............................................................................................................37
7.3728MHz Internal Oscillator ...........................................................................................................................37

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32.768kHz External Crystal Oscillator ................................................................................................................38
8kHz Ultra-Low Power Nano-Ring Internal Oscillator........................................................................................38
3.2 System Oscillators Reset ........................................................................................................................ 39
3.3 Power Management............................................................................................................................... 40
3.4 Operating Modes ................................................................................................................................... 40
ACTIVE Mode .....................................................................................................................................................40
SLEEP Low Power Mode.....................................................................................................................................40
BACKGROUND Low Power Mode.......................................................................................................................42
DEEPSLEEP Low Power Mode ............................................................................................................................44
BACKUP Low Power Mode.................................................................................................................................46
3.5 Shutdown State...................................................................................................................................... 48
3.6 Device Resets ......................................................................................................................................... 48
Peripheral Reset.................................................................................................................................................48
Soft Reset...........................................................................................................................................................48
System Reset......................................................................................................................................................48
Power-On Reset .................................................................................................................................................48
3.7 Cache...................................................................................................................................................... 50
3.8 Instruction Cache Controller.................................................................................................................. 51
Enabling ICC0/ICC1.............................................................................................................................................51
Disabling ICC0/ICC1............................................................................................................................................51
Flushing the ICC0/ICC1 Cache ............................................................................................................................52
3.9 Instruction Cache Controller Registers .................................................................................................. 52
3.10 Instruction Cache Controller Register Details........................................................................................ 52
3.11 External Memory Cache Controller........................................................................................................ 53
3.12 RAM Memory Management .................................................................................................................. 53
RAM Zeroization ................................................................................................................................................53
RAM Low Power Modes.....................................................................................................................................54
3.13 Global Control Registers (GCR) .............................................................................................................. 54
3.14 Global Control Register Details.............................................................................................................. 55
3.15 Function Control Registers..................................................................................................................... 74
3.16 Function Control Register Details .......................................................................................................... 75
3.17 AES Key Registers................................................................................................................................... 77
3.18 AES Key Register Details......................................................................................................................... 78
3.19 Power Supply Monitoring ...................................................................................................................... 78
3.20 AOD Low Power Control Registers......................................................................................................... 79
3.21 AOD Low Power Control Register Details .............................................................................................. 79

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4Interrupts and Exceptions ......................................................................................................84
4.1 Features ................................................................................................................................................. 84
4.2 Interrupt Vector Table ........................................................................................................................... 84
5General-Purpose I/O and Alternate Function Pins ................................................................87
5.1 Features ................................................................................................................................................. 87
5.2 General Description ............................................................................................................................... 87
5.3 GPIO ....................................................................................................................................................... 99
Input mode configuration..................................................................................................................................99
Output Mode Configuration ..............................................................................................................................99
Alternate Function Configuration ......................................................................................................................99
5.4 Input Modes and Pulldown/Pullup Strength Selection........................................................................ 100
5.5 Configuring GPIO (External) Interrupts................................................................................................ 100
GPIO Interrupt Vectors ....................................................................................................................................100
Using GPIO for Wakeup from Low Power Modes............................................................................................101
5.6 GPIO Registers...................................................................................................................................... 101
5.7 GPIO Register Details ........................................................................................................................... 103
6Flash Controller ....................................................................................................................115
6.1 Overview .............................................................................................................................................. 115
6.2 Usage.................................................................................................................................................... 115
Clock Configuration..........................................................................................................................................115
Lock Protection ................................................................................................................................................116
Flash Write Width ............................................................................................................................................116
Flash Write.......................................................................................................................................................116
Page Erase........................................................................................................................................................117
Mass Erase .......................................................................................................................................................117
6.3 Flash Controller Registers .................................................................................................................... 117
6.4 Flash Controller Register Details.......................................................................................................... 118
7External Memory..................................................................................................................122
7.1 Overview .............................................................................................................................................. 122
7.2 SPI Execute-in-Place Flash.................................................................................................................... 122
SPIXF Master Controller...................................................................................................................................122
SPI Pin Configuration........................................................................................................................................123
SPIXF Master ....................................................................................................................................................137
7.3 SPI Execute-in-Place RAM .................................................................................................................... 146
SPIXR Master Controller Registers...................................................................................................................146

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SPIXR Register Details ......................................................................................................................................147
7.4 External Memory Cache Controller (EMCC)......................................................................................... 157
Features ...........................................................................................................................................................157
Enabling the EMCC...........................................................................................................................................157
Disabling the EMCC..........................................................................................................................................157
EMCC Registers ................................................................................................................................................157
EMCC Register Details......................................................................................................................................158
7.5 Secure Digital Host Controller.............................................................................................................. 160
Overview..........................................................................................................................................................160
Features ...........................................................................................................................................................160
Signals and Pins................................................................................................................................................161
SDHC Peripheral Clock Selection......................................................................................................................162
Usage ...............................................................................................................................................................162
SD Command Generation ................................................................................................................................164
SDHC Registers.................................................................................................................................................164
SDHC Register Details ......................................................................................................................................166
7.6 HyperBus/Xccela High Speed Memory Controller Interface................................................................ 202
HyperBus/Xccela Signal Descriptions...............................................................................................................203
Related Specifications......................................................................................................................................203
Reading and Writing to a Slave Device from Firmware ...................................................................................204
Data Cache .......................................................................................................................................................204
HyperBus/Xccela Memory Transfers ...............................................................................................................205
External Memory Reset ...................................................................................................................................206
HyperBus/Xccela Interrupts .............................................................................................................................206
HyperBus/Xccela Registers ..............................................................................................................................206
8Standard DMA Controller.....................................................................................................212
8.1 DMA channel operation....................................................................................................................... 212
8.2 DMA Channel Arbitration and DMA Bursts.......................................................................................... 213
8.3 DMA Source and Destination Addressing............................................................................................ 214
8.4 Data Movement from Source to DMA FIFO......................................................................................... 215
8.5 Data Movement from the DMA FIFO to Destination........................................................................... 215
8.6 Count-To-Zero Condition ..................................................................................................................... 216
8.7 Chaining Buffers................................................................................................................................... 216
8.8 DMA Interrupts .................................................................................................................................... 217
8.9 Channel Timeouts ................................................................................................................................ 217
8.10 10-bit Timer.......................................................................................................................................... 217

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8.11 Channel and Register Access Restrictions............................................................................................ 218
8.12 Memory-to-Memory DMA................................................................................................................... 218
8.13 Standard DMA Registers ...................................................................................................................... 218
8.14 Standard DMA Register Details............................................................................................................ 219
8.15 Standard DMA Channel Register Offsets ............................................................................................. 219
8.16 Standard DMA Channel Registers........................................................................................................ 220
8.17 Standard DMA Channel Register Details.............................................................................................. 220
9CRC Engine............................................................................................................................226
9.1 Overview .............................................................................................................................................. 226
Linear Feedback Shift Register.........................................................................................................................227
9.2 CRC Registers ....................................................................................................................................... 228
9.3 CRC Register Details............................................................................................................................. 229
10 Analog to Digital Converter ..............................................................................................234
10.1 Features ............................................................................................................................................... 234
10.2 Architecture ......................................................................................................................................... 234
10.3 Clock Configuration.............................................................................................................................. 235
10.4 Power-Up Sequence............................................................................................................................. 236
10.5 Conversion ........................................................................................................................................... 237
10.6 Reference Scaling and Input Scaling .................................................................................................... 237
AIN0 AIN3 Scale Limitations..........................................................................................................................237
AIN7 AIN8 Scale Limitations..........................................................................................................................237
Scale Limitations for All Other Input Channels ................................................................................................237
Data Conversion Output Alignment.................................................................................................................238
Data Conversion Value Equations....................................................................................................................238
Data Limits and Out of Range Interrupts .........................................................................................................240
Power-Down Sequence....................................................................................................................................241
10.7 ADC Registers....................................................................................................................................... 241
10.8 ADC Register Details............................................................................................................................. 242
11 Color LCD-TFT Controller ..................................................................................................246
11.1 Features ............................................................................................................................................... 246
11.2 Functional Overview ............................................................................................................................ 247
AHB Master Interface and DMA FIFO Operation .............................................................................................248
11.3 Signals and Pins.................................................................................................................................... 249
11.4 Pixel Process Engine............................................................................................................................. 250
11.5 Palette RAM ......................................................................................................................................... 252

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11.6 8-Bit Color STN Output Format............................................................................................................ 252
11.7 Panel/Pixel Clock Generation............................................................................................................... 253
11.8 LCD Panel Timing Generation .............................................................................................................. 254
11.9 Interrupt Operation ............................................................................................................................. 255
11.10 TFT Controller Registers....................................................................................................................... 255
11.11 TFT Controller Register Details............................................................................................................. 255
12 UART..................................................................................................................................262
12.1 UART Frame Characters ....................................................................................................................... 262
12.2 UART Interrupts ................................................................................................................................... 263
12.3 Alternate Bit Rate Clock Source ........................................................................................................... 263
12.4 UART Bit Rate Calculation.................................................................................................................... 263
12.5 UART DMA Using the TX and RX FIFOs ................................................................................................ 264
RX FIFO DMA Operation...................................................................................................................................264
TX FIFO DMA Operation...................................................................................................................................265
12.6 Flushing the UART FIFOs ...................................................................................................................... 265
12.7 Hardware Flow Control........................................................................................................................ 265
12.8 UART Registers..................................................................................................................................... 265
12.9 UART Register Details........................................................................................................................... 266
13 I2C Master/Slave Serial Communications Peripheral........................................................273
13.1 I²C Master/Slave Features.................................................................................................................... 273
13.2 I2C Bus Speeds...................................................................................................................................... 273
13.3 I2C Transfer Protocol Operation........................................................................................................... 274
13.4 START and STOP Conditions................................................................................................................. 274
13.5 I2C Master/Slave Overview .................................................................................................................. 274
13.6 Slave Addressing .................................................................................................................................. 274
13.7 Acknowledge and Not Acknowledge ................................................................................................... 274
13.8 Bit Transfer Process.............................................................................................................................. 275
13.9 SCL and SDA Bus Drivers ...................................................................................................................... 275
I2C Interrupt Sources .......................................................................................................................................276
SCL Clock Configurations..................................................................................................................................276
Clock Synchronization ......................................................................................................................................276
Transmit and Receive FIFOs .............................................................................................................................277
13.10 Clock Stretching ................................................................................................................................... 277
13.11 I2C Bus Timeout.................................................................................................................................... 278
13.12 I2C Addressing ...................................................................................................................................... 278

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13.13 I2C TX FIFO and RX FIFO Management................................................................................................. 279
13.14 Interactive Receive Mode .................................................................................................................... 279
13.15 I2C DMA Control................................................................................................................................... 280
13.16 I2C Master Mode Transmit Operation.................................................................................................. 280
13.17 I2C Master Mode Transmit Bus Arbitration.......................................................................................... 281
13.18 SCL Clock Generation ........................................................................................................................... 282
13.19 TX FIFO Preloading............................................................................................................................... 282
13.20 Master Mode Receiver Operation ....................................................................................................... 283
13.21 I2C Registers ......................................................................................................................................... 283
13.22 I2C Register Details............................................................................................................................... 284
14 Pulse Train Engine.............................................................................................................297
14.1 Pulse Train Engine Features................................................................................................................. 297
14.2 Engine................................................................................................................................................... 297
Pulse Train Output Modes ...............................................................................................................................297
14.3 Enabling and Disabling a Pulse Train Output....................................................................................... 299
14.4 Atomic Pulse Train Output Enable and Disable ................................................................................... 299
Pulse Train Atomic Enable ...............................................................................................................................299
Pulse Train Atomic Disable...............................................................................................................................299
14.5 Pulse Train Halt and Disable................................................................................................................. 300
14.6 Pulse Train Interrupts........................................................................................................................... 300
14.7 Pulse Train Engine Registers ................................................................................................................ 300
14.8 Pulse Train Engine Register Details...................................................................................................... 300
Pulse Train Engine Safe Enable Register ..........................................................................................................309
Pulse Train Engine Safe Disable Register .........................................................................................................311
15 Timers................................................................................................................................316
15.1 Features ............................................................................................................................................... 316
15.2 Basic Operation.................................................................................................................................... 316
15.3 Timer Pin Functionality ........................................................................................................................ 317
15.4 One-Shot Mode (000b) ........................................................................................................................ 318
One-Shot Mode Timer Period ..........................................................................................................................318
One-Shot Mode Configuration.........................................................................................................................319
15.5 Continuous Mode (001b)..................................................................................................................... 320
Continuous Mode Timer Period.......................................................................................................................320
Continuous Mode Configuration .....................................................................................................................321
15.6 Counter Mode (010b) .......................................................................................................................... 322

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Counter Mode Timer Period ............................................................................................................................322
Counter Mode Configuration...........................................................................................................................323
15.7 PWM Mode (011b)............................................................................................................................... 324
PWM Mode Timer Period ................................................................................................................................324
PWM Mode Configuration...............................................................................................................................324
15.8 Capture Mode (100b)........................................................................................................................... 326
Capture Mode Timer Period ............................................................................................................................326
Capture Mode Configuration ...........................................................................................................................327
15.9 Compare Mode (101b)......................................................................................................................... 328
Compare Mode Timer Period ..........................................................................................................................328
Compare Mode Configuration .........................................................................................................................329
15.10 Gated Mode (110b).............................................................................................................................. 330
Gated Mode Timer Period...........................................................................................................................330
Gated Mode Configuration .........................................................................................................................330
15.11 Capture/Compare Mode (111b) .......................................................................................................... 331
Capture/Compare Timer Period..................................................................................................................331
Capture/Compare Configuration ................................................................................................................331
15.12 Timer Registers .................................................................................................................................... 332
15.13 Timer Register Details.......................................................................................................................... 332
16 Watchdog Timer (WDT) ....................................................................................................336
16.1 Features ............................................................................................................................................... 337
16.2 Usage.................................................................................................................................................... 337
16.3 Interrupt and Reset Period Timeout Configuration............................................................................. 337
16.4 Enabling the Watchdog Timer.............................................................................................................. 338
Enable sequence ..............................................................................................................................................338
16.5 Disabling the Watchdog Timer............................................................................................................. 338
Manual Disable ................................................................................................................................................338
Automatic Disable............................................................................................................................................338
16.6 Resetting the Watchdog Timer ............................................................................................................ 338
Reset Sequence................................................................................................................................................338
16.7 Detection of a Watchdog Reset Event ................................................................................................. 339
16.8 Watchdog Timer Registers................................................................................................................... 339
16.9 Watchdog Timer Register Details......................................................................................................... 339
17 1-Wire Master...................................................................................................................342
17.1 Features ............................................................................................................................................... 342
17.2 Pins and Configuration......................................................................................................................... 342

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Pin Configuration .............................................................................................................................................343
I/O ....................................................................................................................................................................343
Pullup Enable ...................................................................................................................................................343
17.3 Clock Configuration.............................................................................................................................. 343
17.4 1-Wire Protocol.................................................................................................................................... 343
Networking Layers ...........................................................................................................................................344
Bus Interface (Physical Layer) ..........................................................................................................................344
Reset, Presence Detect, and Data Transfer (Link Layer) ..................................................................................344
17.5 Read and Write Time Slots................................................................................................................... 345
OWM Write Time Slot......................................................................................................................................345
OWM Read Time Slot.......................................................................................................................................346
17.6 Standard Speed and Overdrive Speed ................................................................................................. 347
ROM Commands (Network Layer) ...................................................................................................................347
Read ROM Command.......................................................................................................................................348
Skip ROM and Overdrive Skip ROM Commands ..............................................................................................348
Match ROM and Overdrive Match ROM Commands.......................................................................................349
Search ROM Command....................................................................................................................................349
Search ROM Accelerator Operation.................................................................................................................349
Resume Communication Command ................................................................................................................350
17.7 1-Wire Operation................................................................................................................................. 350
Resetting the OWM .........................................................................................................................................351
1-Wire Data Writes ..........................................................................................................................................351
17.8 1-Wire Data Reads ............................................................................................................................... 351
Reading a Single Bit Value from the 1-Wire Bus ..............................................................................................351
Reading an 8-Bit Value from the 1-Wire Bus ...................................................................................................352
17.9 OWM Registers .................................................................................................................................... 352
17.10 OWM Register Details.......................................................................................................................... 353
18 USBHS 2.0 Hi-Speed Host Interface with PHY ..................................................................357
18.1 USBHS Bus Signals................................................................................................................................ 358
18.2 USBHS Device Endpoints...................................................................................................................... 359
18.3 USBHS Reset......................................................................................................................................... 360
18.4 USBHS SUSPEND and RESUME States.................................................................................................. 360
18.5 Packet Size............................................................................................................................................ 360
18.6 Endpoint 0 Control Transactions.......................................................................................................... 360
Endpoint 0 Error Handling ...............................................................................................................................361
18.7 Bulk Endpoints Operation and Options ............................................................................................... 361