Maxim Integrated MAX32650 User manual

MAX32650–MAX32652 USER GUIDE
UG6766; Rev 0; 9/18
Abstract: This user guide provides application developers information on how to use the memory and
peripherals of the MAX32650MAX32652 microcontroller. Detailed information for all registers and fields in
the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the
device family.

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MAX32650–MAX32652 User Guide
Table of Contents
1Overview.................................................................................................................................23
1.1 Block Diagram ........................................................................................................................................ 24
2Memory, Register Mapping, and Access................................................................................26
2.1 Memory, Register Mapping, and Access Overview ............................................................................... 26
2.2 Standard Memory Regions..................................................................................................................... 28
Code Space.........................................................................................................................................................28
SRAM Space .......................................................................................................................................................29
Peripheral Space ................................................................................................................................................30
External RAM Space...........................................................................................................................................30
External Device Space........................................................................................................................................30
System Area (Private Peripheral Bus) ................................................................................................................31
System Area (Vendor Defined) ..........................................................................................................................31
2.3 Device Memory Instances...................................................................................................................... 31
Main Program Flash Memory ............................................................................................................................31
Cache Memories ................................................................................................................................................31
External Memory Cache Controller (EMCC).......................................................................................................31
Information Block Flash Memory.......................................................................................................................31
System SRAM .....................................................................................................................................................32
AES Key and Working Space Memory................................................................................................................32
MAA Key and Working Space Memory ..............................................................................................................32
TPU Memory ......................................................................................................................................................32
2.4 AHB Interfaces........................................................................................................................................ 32
Core AHB Interfaces...........................................................................................................................................32
AHB Masters ......................................................................................................................................................32
2.5 Peripheral Register Map ........................................................................................................................ 33
APB Peripheral Base Address Map.....................................................................................................................33
AHB Peripheral Base Address Map ....................................................................................................................35
3System Clocks, Reset, and Power Management....................................................................36
3.1 Oscillator Sources and Clock Switching.................................................................................................. 37
120MHz Internal Main High-Speed Oscillator ...................................................................................................37
40MHz Low Power Internal Oscillator ...............................................................................................................37
7.3728MHz Internal Oscillator ...........................................................................................................................37

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32.768kHz External Crystal Oscillator ................................................................................................................38
8kHz Ultra-Low Power Nano-Ring Internal Oscillator........................................................................................38
3.2 System Oscillators Reset ........................................................................................................................ 39
3.3 Power Management............................................................................................................................... 40
3.4 Operating Modes ................................................................................................................................... 40
ACTIVE Mode .....................................................................................................................................................40
SLEEP Low Power Mode.....................................................................................................................................40
BACKGROUND Low Power Mode.......................................................................................................................42
DEEPSLEEP Low Power Mode ............................................................................................................................44
BACKUP Low Power Mode.................................................................................................................................46
3.5 Shutdown State...................................................................................................................................... 48
3.6 Device Resets ......................................................................................................................................... 48
Peripheral Reset.................................................................................................................................................48
Soft Reset...........................................................................................................................................................48
System Reset......................................................................................................................................................48
Power-On Reset .................................................................................................................................................48
3.7 Cache...................................................................................................................................................... 50
3.8 Instruction Cache Controller.................................................................................................................. 51
Enabling ICC0/ICC1.............................................................................................................................................51
Disabling ICC0/ICC1............................................................................................................................................51
Flushing the ICC0/ICC1 Cache ............................................................................................................................52
3.9 Instruction Cache Controller Registers .................................................................................................. 52
3.10 Instruction Cache Controller Register Details........................................................................................ 52
3.11 External Memory Cache Controller........................................................................................................ 53
3.12 RAM Memory Management .................................................................................................................. 53
RAM Zeroization ................................................................................................................................................53
RAM Low Power Modes.....................................................................................................................................54
3.13 Global Control Registers (GCR) .............................................................................................................. 54
3.14 Global Control Register Details.............................................................................................................. 55
3.15 Function Control Registers..................................................................................................................... 74
3.16 Function Control Register Details .......................................................................................................... 75
3.17 AES Key Registers................................................................................................................................... 77
3.18 AES Key Register Details......................................................................................................................... 78
3.19 Power Supply Monitoring ...................................................................................................................... 78
3.20 AOD Low Power Control Registers......................................................................................................... 79
3.21 AOD Low Power Control Register Details .............................................................................................. 79

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4Interrupts and Exceptions ......................................................................................................84
4.1 Features ................................................................................................................................................. 84
4.2 Interrupt Vector Table ........................................................................................................................... 84
5General-Purpose I/O and Alternate Function Pins ................................................................87
5.1 Features ................................................................................................................................................. 87
5.2 General Description ............................................................................................................................... 87
5.3 GPIO ....................................................................................................................................................... 99
Input mode configuration..................................................................................................................................99
Output Mode Configuration ..............................................................................................................................99
Alternate Function Configuration ......................................................................................................................99
5.4 Input Modes and Pulldown/Pullup Strength Selection........................................................................ 100
5.5 Configuring GPIO (External) Interrupts................................................................................................ 100
GPIO Interrupt Vectors ....................................................................................................................................100
Using GPIO for Wakeup from Low Power Modes............................................................................................101
5.6 GPIO Registers...................................................................................................................................... 101
5.7 GPIO Register Details ........................................................................................................................... 103
6Flash Controller ....................................................................................................................115
6.1 Overview .............................................................................................................................................. 115
6.2 Usage.................................................................................................................................................... 115
Clock Configuration..........................................................................................................................................115
Lock Protection ................................................................................................................................................116
Flash Write Width ............................................................................................................................................116
Flash Write.......................................................................................................................................................116
Page Erase........................................................................................................................................................117
Mass Erase .......................................................................................................................................................117
6.3 Flash Controller Registers .................................................................................................................... 117
6.4 Flash Controller Register Details.......................................................................................................... 118
7External Memory..................................................................................................................122
7.1 Overview .............................................................................................................................................. 122
7.2 SPI Execute-in-Place Flash.................................................................................................................... 122
SPIXF Master Controller...................................................................................................................................122
SPI Pin Configuration........................................................................................................................................123
SPIXF Master ....................................................................................................................................................137
7.3 SPI Execute-in-Place RAM .................................................................................................................... 146
SPIXR Master Controller Registers...................................................................................................................146

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SPIXR Register Details ......................................................................................................................................147
7.4 External Memory Cache Controller (EMCC)......................................................................................... 157
Features ...........................................................................................................................................................157
Enabling the EMCC...........................................................................................................................................157
Disabling the EMCC..........................................................................................................................................157
EMCC Registers ................................................................................................................................................157
EMCC Register Details......................................................................................................................................158
7.5 Secure Digital Host Controller.............................................................................................................. 160
Overview..........................................................................................................................................................160
Features ...........................................................................................................................................................160
Signals and Pins................................................................................................................................................161
SDHC Peripheral Clock Selection......................................................................................................................162
Usage ...............................................................................................................................................................162
SD Command Generation ................................................................................................................................164
SDHC Registers.................................................................................................................................................164
SDHC Register Details ......................................................................................................................................166
7.6 HyperBus/Xccela High Speed Memory Controller Interface................................................................ 202
HyperBus/Xccela Signal Descriptions...............................................................................................................203
Related Specifications......................................................................................................................................203
Reading and Writing to a Slave Device from Firmware ...................................................................................204
Data Cache .......................................................................................................................................................204
HyperBus/Xccela Memory Transfers ...............................................................................................................205
External Memory Reset ...................................................................................................................................206
HyperBus/Xccela Interrupts .............................................................................................................................206
HyperBus/Xccela Registers ..............................................................................................................................206
8Standard DMA Controller.....................................................................................................212
8.1 DMA channel operation....................................................................................................................... 212
8.2 DMA Channel Arbitration and DMA Bursts.......................................................................................... 213
8.3 DMA Source and Destination Addressing............................................................................................ 214
8.4 Data Movement from Source to DMA FIFO......................................................................................... 215
8.5 Data Movement from the DMA FIFO to Destination........................................................................... 215
8.6 Count-To-Zero Condition ..................................................................................................................... 216
8.7 Chaining Buffers................................................................................................................................... 216
8.8 DMA Interrupts .................................................................................................................................... 217
8.9 Channel Timeouts ................................................................................................................................ 217
8.10 10-bit Timer.......................................................................................................................................... 217

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8.11 Channel and Register Access Restrictions............................................................................................ 218
8.12 Memory-to-Memory DMA................................................................................................................... 218
8.13 Standard DMA Registers ...................................................................................................................... 218
8.14 Standard DMA Register Details............................................................................................................ 219
8.15 Standard DMA Channel Register Offsets ............................................................................................. 219
8.16 Standard DMA Channel Registers........................................................................................................ 220
8.17 Standard DMA Channel Register Details.............................................................................................. 220
9CRC Engine............................................................................................................................226
9.1 Overview .............................................................................................................................................. 226
Linear Feedback Shift Register.........................................................................................................................227
9.2 CRC Registers ....................................................................................................................................... 228
9.3 CRC Register Details............................................................................................................................. 229
10 Analog to Digital Converter ..............................................................................................234
10.1 Features ............................................................................................................................................... 234
10.2 Architecture ......................................................................................................................................... 234
10.3 Clock Configuration.............................................................................................................................. 235
10.4 Power-Up Sequence............................................................................................................................. 236
10.5 Conversion ........................................................................................................................................... 237
10.6 Reference Scaling and Input Scaling .................................................................................................... 237
AIN0 AIN3 Scale Limitations..........................................................................................................................237
AIN7 AIN8 Scale Limitations..........................................................................................................................237
Scale Limitations for All Other Input Channels ................................................................................................237
Data Conversion Output Alignment.................................................................................................................238
Data Conversion Value Equations....................................................................................................................238
Data Limits and Out of Range Interrupts .........................................................................................................240
Power-Down Sequence....................................................................................................................................241
10.7 ADC Registers....................................................................................................................................... 241
10.8 ADC Register Details............................................................................................................................. 242
11 Color LCD-TFT Controller ..................................................................................................246
11.1 Features ............................................................................................................................................... 246
11.2 Functional Overview ............................................................................................................................ 247
AHB Master Interface and DMA FIFO Operation .............................................................................................248
11.3 Signals and Pins.................................................................................................................................... 249
11.4 Pixel Process Engine............................................................................................................................. 250
11.5 Palette RAM ......................................................................................................................................... 252

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11.6 8-Bit Color STN Output Format............................................................................................................ 252
11.7 Panel/Pixel Clock Generation............................................................................................................... 253
11.8 LCD Panel Timing Generation .............................................................................................................. 254
11.9 Interrupt Operation ............................................................................................................................. 255
11.10 TFT Controller Registers....................................................................................................................... 255
11.11 TFT Controller Register Details............................................................................................................. 255
12 UART..................................................................................................................................262
12.1 UART Frame Characters ....................................................................................................................... 262
12.2 UART Interrupts ................................................................................................................................... 263
12.3 Alternate Bit Rate Clock Source ........................................................................................................... 263
12.4 UART Bit Rate Calculation.................................................................................................................... 263
12.5 UART DMA Using the TX and RX FIFOs ................................................................................................ 264
RX FIFO DMA Operation...................................................................................................................................264
TX FIFO DMA Operation...................................................................................................................................265
12.6 Flushing the UART FIFOs ...................................................................................................................... 265
12.7 Hardware Flow Control........................................................................................................................ 265
12.8 UART Registers..................................................................................................................................... 265
12.9 UART Register Details........................................................................................................................... 266
13 I2C Master/Slave Serial Communications Peripheral........................................................273
13.1 I²C Master/Slave Features.................................................................................................................... 273
13.2 I2C Bus Speeds...................................................................................................................................... 273
13.3 I2C Transfer Protocol Operation........................................................................................................... 274
13.4 START and STOP Conditions................................................................................................................. 274
13.5 I2C Master/Slave Overview .................................................................................................................. 274
13.6 Slave Addressing .................................................................................................................................. 274
13.7 Acknowledge and Not Acknowledge ................................................................................................... 274
13.8 Bit Transfer Process.............................................................................................................................. 275
13.9 SCL and SDA Bus Drivers ...................................................................................................................... 275
I2C Interrupt Sources .......................................................................................................................................276
SCL Clock Configurations..................................................................................................................................276
Clock Synchronization ......................................................................................................................................276
Transmit and Receive FIFOs .............................................................................................................................277
13.10 Clock Stretching ................................................................................................................................... 277
13.11 I2C Bus Timeout.................................................................................................................................... 278
13.12 I2C Addressing ...................................................................................................................................... 278

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13.13 I2C TX FIFO and RX FIFO Management................................................................................................. 279
13.14 Interactive Receive Mode .................................................................................................................... 279
13.15 I2C DMA Control................................................................................................................................... 280
13.16 I2C Master Mode Transmit Operation.................................................................................................. 280
13.17 I2C Master Mode Transmit Bus Arbitration.......................................................................................... 281
13.18 SCL Clock Generation ........................................................................................................................... 282
13.19 TX FIFO Preloading............................................................................................................................... 282
13.20 Master Mode Receiver Operation ....................................................................................................... 283
13.21 I2C Registers ......................................................................................................................................... 283
13.22 I2C Register Details............................................................................................................................... 284
14 Pulse Train Engine.............................................................................................................297
14.1 Pulse Train Engine Features................................................................................................................. 297
14.2 Engine................................................................................................................................................... 297
Pulse Train Output Modes ...............................................................................................................................297
14.3 Enabling and Disabling a Pulse Train Output....................................................................................... 299
14.4 Atomic Pulse Train Output Enable and Disable ................................................................................... 299
Pulse Train Atomic Enable ...............................................................................................................................299
Pulse Train Atomic Disable...............................................................................................................................299
14.5 Pulse Train Halt and Disable................................................................................................................. 300
14.6 Pulse Train Interrupts........................................................................................................................... 300
14.7 Pulse Train Engine Registers ................................................................................................................ 300
14.8 Pulse Train Engine Register Details...................................................................................................... 300
Pulse Train Engine Safe Enable Register ..........................................................................................................309
Pulse Train Engine Safe Disable Register .........................................................................................................311
15 Timers................................................................................................................................316
15.1 Features ............................................................................................................................................... 316
15.2 Basic Operation.................................................................................................................................... 316
15.3 Timer Pin Functionality ........................................................................................................................ 317
15.4 One-Shot Mode (000b) ........................................................................................................................ 318
One-Shot Mode Timer Period ..........................................................................................................................318
One-Shot Mode Configuration.........................................................................................................................319
15.5 Continuous Mode (001b)..................................................................................................................... 320
Continuous Mode Timer Period.......................................................................................................................320
Continuous Mode Configuration .....................................................................................................................321
15.6 Counter Mode (010b) .......................................................................................................................... 322

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Counter Mode Timer Period ............................................................................................................................322
Counter Mode Configuration...........................................................................................................................323
15.7 PWM Mode (011b)............................................................................................................................... 324
PWM Mode Timer Period ................................................................................................................................324
PWM Mode Configuration...............................................................................................................................324
15.8 Capture Mode (100b)........................................................................................................................... 326
Capture Mode Timer Period ............................................................................................................................326
Capture Mode Configuration ...........................................................................................................................327
15.9 Compare Mode (101b)......................................................................................................................... 328
Compare Mode Timer Period ..........................................................................................................................328
Compare Mode Configuration .........................................................................................................................329
15.10 Gated Mode (110b).............................................................................................................................. 330
Gated Mode Timer Period...........................................................................................................................330
Gated Mode Configuration .........................................................................................................................330
15.11 Capture/Compare Mode (111b) .......................................................................................................... 331
Capture/Compare Timer Period..................................................................................................................331
Capture/Compare Configuration ................................................................................................................331
15.12 Timer Registers .................................................................................................................................... 332
15.13 Timer Register Details.......................................................................................................................... 332
16 Watchdog Timer (WDT) ....................................................................................................336
16.1 Features ............................................................................................................................................... 337
16.2 Usage.................................................................................................................................................... 337
16.3 Interrupt and Reset Period Timeout Configuration............................................................................. 337
16.4 Enabling the Watchdog Timer.............................................................................................................. 338
Enable sequence ..............................................................................................................................................338
16.5 Disabling the Watchdog Timer............................................................................................................. 338
Manual Disable ................................................................................................................................................338
Automatic Disable............................................................................................................................................338
16.6 Resetting the Watchdog Timer ............................................................................................................ 338
Reset Sequence................................................................................................................................................338
16.7 Detection of a Watchdog Reset Event ................................................................................................. 339
16.8 Watchdog Timer Registers................................................................................................................... 339
16.9 Watchdog Timer Register Details......................................................................................................... 339
17 1-Wire Master...................................................................................................................342
17.1 Features ............................................................................................................................................... 342
17.2 Pins and Configuration......................................................................................................................... 342

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Pin Configuration .............................................................................................................................................343
I/O ....................................................................................................................................................................343
Pullup Enable ...................................................................................................................................................343
17.3 Clock Configuration.............................................................................................................................. 343
17.4 1-Wire Protocol.................................................................................................................................... 343
Networking Layers ...........................................................................................................................................344
Bus Interface (Physical Layer) ..........................................................................................................................344
Reset, Presence Detect, and Data Transfer (Link Layer) ..................................................................................344
17.5 Read and Write Time Slots................................................................................................................... 345
OWM Write Time Slot......................................................................................................................................345
OWM Read Time Slot.......................................................................................................................................346
17.6 Standard Speed and Overdrive Speed ................................................................................................. 347
ROM Commands (Network Layer) ...................................................................................................................347
Read ROM Command.......................................................................................................................................348
Skip ROM and Overdrive Skip ROM Commands ..............................................................................................348
Match ROM and Overdrive Match ROM Commands.......................................................................................349
Search ROM Command....................................................................................................................................349
Search ROM Accelerator Operation.................................................................................................................349
Resume Communication Command ................................................................................................................350
17.7 1-Wire Operation................................................................................................................................. 350
Resetting the OWM .........................................................................................................................................351
1-Wire Data Writes ..........................................................................................................................................351
17.8 1-Wire Data Reads ............................................................................................................................... 351
Reading a Single Bit Value from the 1-Wire Bus ..............................................................................................351
Reading an 8-Bit Value from the 1-Wire Bus ...................................................................................................352
17.9 OWM Registers .................................................................................................................................... 352
17.10 OWM Register Details.......................................................................................................................... 353
18 USBHS 2.0 Hi-Speed Host Interface with PHY ..................................................................357
18.1 USBHS Bus Signals................................................................................................................................ 358
18.2 USBHS Device Endpoints...................................................................................................................... 359
18.3 USBHS Reset......................................................................................................................................... 360
18.4 USBHS SUSPEND and RESUME States.................................................................................................. 360
18.5 Packet Size............................................................................................................................................ 360
18.6 Endpoint 0 Control Transactions.......................................................................................................... 360
Endpoint 0 Error Handling ...............................................................................................................................361
18.7 Bulk Endpoints Operation and Options ............................................................................................... 361

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Bulk IN Endpoints.............................................................................................................................................361
Bulk OUT Endpoints .........................................................................................................................................362
18.8 Interrupt Endpoints.............................................................................................................................. 362
Interrupt IN Endpoints .....................................................................................................................................362
Interrupt OUT Endpoints..................................................................................................................................362
18.9 Isochronous Endpoints......................................................................................................................... 363
Isochronous IN Endpoints ................................................................................................................................363
Isochronous OUT Endpoints.............................................................................................................................363
18.10 USBHS Device Registers ....................................................................................................................... 364
18.11 USBHS Device Register Details............................................................................................................. 365
Endpoint Register Access Control ...............................................................................................................373
USBHS IN Endpoint Maximum Packet Size Registers ..................................................................................374
USBHS IN Endpoint Lower Control & Status Registers................................................................................374
USBHS Endpoint 0 Control Status Register .................................................................................................375
USBHS IN Endpoint Upper Control Registers ..............................................................................................376
19 Quad Serial Peripheral Interface (SPI3) ............................................................................384
19.1 Features ............................................................................................................................................... 384
SPI Signals ........................................................................................................................................................385
19.2 SPI Configuration.................................................................................................................................. 385
SPI3 FIFOs.........................................................................................................................................................386
SPI3 Interrupts and Wakeups ..........................................................................................................................386
19.3 Timing Diagrams................................................................................................................................... 387
SPI Mode 0 .......................................................................................................................................................387
SPI Mode 1 .......................................................................................................................................................387
SPI Mode 2 .......................................................................................................................................................388
SPI Mode 3 .......................................................................................................................................................389
19.4 Quad SPI Master(SPI3) Registers.......................................................................................................... 389
19.5 Quad SPI Master Register Details ........................................................................................................ 390
20 SPIMSS for I2S....................................................................................................................399
20.1 Overview .............................................................................................................................................. 399
Features ...........................................................................................................................................................399
20.2 SPIMSS Clock Phase and Polarity Control ............................................................................................ 401
20.3 Data Movement ................................................................................................................................... 401
20.4 I2S (Inter-IC Sound) Mode .................................................................................................................... 402
Mute.................................................................................................................................................................402
Pause................................................................................................................................................................402

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Mono................................................................................................................................................................402
Left Justify ........................................................................................................................................................403
20.5 Error Detection..................................................................................................................................... 403
Transmit Overrun.............................................................................................................................................403
Mode Fault (Multi-Master Collision)................................................................................................................404
Slave Mode Abort ............................................................................................................................................404
Receive Overrun...............................................................................................................................................404
20.6 SPIMSS Interrupts ................................................................................................................................ 404
Data Interrupt ..................................................................................................................................................404
Forced Interrupt...............................................................................................................................................404
Error Condition Interrupt.................................................................................................................................404
Bit Rate Generator Timeout Interrupt .............................................................................................................404
20.7 SPIMSS Bit Rate Generator .................................................................................................................. 405
Slave Mode ......................................................................................................................................................405
Master Mode ...................................................................................................................................................405
Timer Mode .....................................................................................................................................................405
20.8 SPIMSS Registers.................................................................................................................................. 405
20.9 SPIMSS Register Details........................................................................................................................ 406
21 Trademarks .......................................................................................................................411
22 Revision History ................................................................................................................411

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List of Figures
Figure 1-1: MAX32650MAX32652 Block Diagram................................................................................................. 24
Figure 2-1: MAX32650MAX32652 Code Memory Mapping.................................................................................. 27
Figure 2-2 Code Memory Mapping ......................................................................................................................... 28
Figure 3-1: Clock Block Diagram.............................................................................................................................. 39
Figure 3-2: SLEEP Mode Clock Control .................................................................................................................... 41
Figure 3-3: BACKGROUND Mode Clock Control ...................................................................................................... 43
Figure 3-4: DEEPSLEEP Clock Control ...................................................................................................................... 45
Figure 3-5: BACKUP Mode Clock Control ................................................................................................................ 47
Figure 3-6: MAX32650MAX32652 Cache Controllers Diagram............................................................................. 51
Figure 7-1. Simplified Block Diagram..................................................................................................................... 123
Figure 7-2. SPIXF Mode.......................................................................................................................................... 127
Figure 7-3. SPIXF Transaction Delay ...................................................................................................................... 128
Figure 7-4. Supported SPI configuration ............................................................................................................... 138
Figure 7-5. SPIXF Delay Configuration................................................................................................................... 139
Figure 7-6: SDHC Block Diagram............................................................................................................................ 161
Figure 7-7: SD Bus Protocol - No Response and No Data Operations................................................................... 163
Figure 7-8: SD Bus Protocol - Multi-Block Read Operation................................................................................... 163
Figure 7-9: SD Bus Protocol - Multi Block Write Operation .................................................................................. 164
Figure 7-10: HyperBus Command-Address Sequence........................................................................................... 205
Figure 8-1: DMAC Block Diagram .......................................................................................................................... 212
Figure 9-1: Galois Field CRC and LFSR Architecture .............................................................................................. 228
Figure 10-1: Analog to Digital Converter Block Diagram....................................................................................... 235
Figure 10-2: ADC Limit Engine ............................................................................................................................... 240
Figure 11-1: Color LCD Block Diagram................................................................................................................... 248
Figure 13-1: I2C Write Data Transfer ..................................................................................................................... 275
Figure 13-2: I2C Specification Min and Max Clock Parameters ............................................................................. 276
Figure 13-3: I2C Clock Period ................................................................................................................................. 282
Figure 15-1: One-Shot Mode Diagram .................................................................................................................. 318
Figure 15-2: Continuous Mode Diagram ............................................................................................................... 320
Figure 15-3: Counter Mode Diagram..................................................................................................................... 322
Figure 15-4: Capture Mode Diagram..................................................................................................................... 326
Figure 15-5: Counter Mode Diagram..................................................................................................................... 328
Figure 15-6: Gated Mode Diagram........................................................................................................................ 330
Figure 16-1: Watchdog Timer Block Diagram........................................................................................................ 336
Figure 17-1: 1-Wire Signal Interface...................................................................................................................... 344
Figure 17-2: 1-Wire Reset Pulse ............................................................................................................................ 345
Figure 17-3: 1-Wire Write Time Slot...................................................................................................................... 346
Figure 17-4: 1-Wire Read Tme Slot ....................................................................................................................... 346
Figure 17-5: 1-Wire ROM ID FIelds........................................................................................................................ 347
Figure 19-1: SPI Modes of Operation .................................................................................................................... 384
Figure 19-2: SPI Mode 0, Four-Wire Communication ........................................................................................... 387
Figure 19-3: SPI Mode 0, Three-Wire Communication ......................................................................................... 387
Figure 19-4: SPI Mode 1, Four-Wire Communication ........................................................................................... 387
Figure 19-5: SPI Mode 1, Three-Wire Communication ......................................................................................... 388
Figure 19-6: SPI Mode 2, Four-Wire Communication ........................................................................................... 388
Figure 19-7: SPI Mode 2, Three-Wire Communication ......................................................................................... 388

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Figure 19-8: SPI Mode 3, Four-Wire Communication ........................................................................................... 389
Figure 19-9: SPI Mode 3, Three-Wire Communication ......................................................................................... 389
Figure 20-1. SPIMSS Block Diagram....................................................................................................................... 399
Figure 20-2. SPI Single-Master, Single-Slave ......................................................................................................... 400
Figure 20-3. SPI Multi-Master, Multi-Slave ........................................................................................................... 400
Figure 20-4. SPI Slave............................................................................................................................................. 400
Figure 20-5: I2S Mode Right Justify Mode ............................................................................................................. 403
Figure 20-6: I2S Mode Left Justify Mode ............................................................................................................... 403

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List of Tables
Table 2-1: APB Peripheral Base Address Map......................................................................................................... 33
Table 2-2: AHB Peripheral Base Address Map......................................................................................................... 35
Table 3-1: Reset and Low Power Mode Effects....................................................................................................... 49
Table 3-2: Instruction Cache Controller Register Addresses and Descriptions....................................................... 52
Table 3-3: ICC Cache ID Register.............................................................................................................................. 52
Table 3-4: ICC Memory Size Register....................................................................................................................... 52
Table 3-5: ICC Cache Control Register..................................................................................................................... 53
Table 3-6: ICC Invalidate Register............................................................................................................................ 53
Table 3-7: Global Control Register Addresses and Descriptions............................................................................. 54
Table 3-8: System Control Register ......................................................................................................................... 55
Table 3-9: Reset Register 0...................................................................................................................................... 57
Table 3-10: System Clock Control Register.............................................................................................................. 59
Table 3-11: Power Management Register............................................................................................................... 61
Table 3-12: Peripheral Clock Divisor Register.......................................................................................................... 62
Table 3-13: Peripheral Clock Disable Register 0...................................................................................................... 63
Table 3-14: Memory Clock Control Register ........................................................................................................... 65
Table 3-15: Memory Zeroization Control Register.................................................................................................. 67
Table 3-16: System Status Flag Register.................................................................................................................. 69
Table 3-17: Reset Register 1.................................................................................................................................... 69
Table 3-18: Peripheral Clock Disable Register 1...................................................................................................... 71
Table 3-19: Event Enable Register........................................................................................................................... 73
Table 3-20: Revision Register .................................................................................................................................. 74
Table 3-21: System Status Interrupt Enable Register.............................................................................................. 74
Table 3-22: Function Control Registers ................................................................................................................... 75
Table 3-23: Function Control Register 0.................................................................................................................. 75
Table 3-24: Autocalibration Function Control Register 1........................................................................................ 76
Table 3-25: Autocalibration Function Control Register 2........................................................................................ 76
Table 3-26: Autocalibration Function Control Register 3........................................................................................ 77
Table 3-27: HyperBus/Xccela Clock Control Register.............................................................................................. 77
Table 3-28: AES Key Register Addresses and Descriptions...................................................................................... 77
Table 3-29: AES Key 0 and 1 Registers..................................................................................................................... 78
Table 3-30: AES Key 2 and 3 Registers..................................................................................................................... 78
Table 3-31: Always-on-Domain Power Control Registers, Offsets, and Descriptions............................................. 79
Table 3-32: Low Power Voltage Control Register.................................................................................................... 79
Table 3-33: Low Power GPIO Wakeup Interrupt Enable Registers ......................................................................... 81
Table 3-34: Low Power GPIO Wakeup Flag Registers ............................................................................................. 81
Table 3-35: USB Wakeup Status Register................................................................................................................ 81
Table 3-36: Low Power USB Wakeup Enable Register ............................................................................................ 82
Table 3-37: Low Power RAM Power Control Register............................................................................................. 82
Table 4-1: MAX32650 Interrupt Vector Table......................................................................................................... 84
Table 5-1: GPIO Port, Pin Name and Alternate Function Matrix, 140 WLP............................................................. 89
Table 5-2: GPIO Port, Pin Name and Alternate Function Matrix, 144 TQFP ........................................................... 92
Table 5-3: GPIO Port, Pin Name and Alternate Function Matrix, 96 WLP............................................................... 95
Table 5-4: Input Mode Configuration.................................................................................................................... 100
Table 5-5: GPIO Port Interrupt Vector Mapping ................................................................................................... 100
Table 5-6: GPIO Wakeup Interrupt Vector ............................................................................................................ 101

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Table 5-7: GPIO Registers...................................................................................................................................... 101
Table 5-8: GPIO Port 0 Enable Register................................................................................................................. 103
Table 5-9: GPIO Port 1 to Port 3 Enable Registers ................................................................................................ 104
Table 5-10: GPIO Port 0 to Port 3 Enable Atomic Set Registers............................................................................ 104
Table 5-11: GPIO Port 0 to Port 3 Enable Atomic Clear Registers......................................................................... 104
Table 5-12: GPIO Port 0 Output Enable Register................................................................................................... 104
Table 5-13: GPIO Port 1 to Port 3 Output Enable Registers.................................................................................. 105
Table 5-14: GPIO Port 0 to Port 3 Output Enable Atomic Set Registers................................................................ 105
Table 5-15: GPIO Port 0 to Port 3 Output Enable Atomic Clear Registers ............................................................ 106
Table 5-16: GPIO Port 0 to Port 3 Output Registers.............................................................................................. 106
Table 5-17: GPIO Port 0 to Port 3 Output Atomic Set Registers ........................................................................... 106
Table 5-18: GPIO Port 0 to Port 3 Output Atomic Clear Registers ........................................................................ 106
Table 5-19: GPIO Port 0 to Port 3 Input Registers................................................................................................. 107
Table 5-20: GPIO Port 0 to Port 3 Interrupt Mode Registers ................................................................................ 107
Table 5-21: GPIO Port 0 to Port 3 Interrupt Polarity Registers ............................................................................. 107
Table 5-22: GPIO Port 0 to Port 3 Input Enable Registers..................................................................................... 108
Table 5-23: GPIO Port 0 to Port 3 Interrupt Enable Registers............................................................................... 108
Table 5-24: GPIO Port 0 to Port 3 Interrupt Enable Atomic Set Registers ............................................................ 108
Table 5-25: GPIO Port 0 to Port 3 Interrupt Enable Atomic Clear Registers ......................................................... 108
Table 5-26: GPIO Port 0 to Port 3 Interrupt Status Registers................................................................................ 109
Table 5-27: GPIO Port 0 to Port 3 Interrupt Clear Registers ................................................................................. 109
Table 5-28: GPIO Port 0 to Port 3 Wakeup Enable Registers................................................................................ 109
Table 5-29: GPIO Port 0 to Port 3 Wakeup Enable Atomic Set Registers.............................................................. 109
Table 5-30: GPIO Port 0 to Port 3 Wakeup Enable Clear Registers....................................................................... 110
Table 5-31: GPIO Port 0 to Port 3 Interrupt Dual Edge Mode Registers ............................................................... 110
Table 5-32: GPIO Port 0 to Port 3 Pullup Pulldown Selection 0 Registers............................................................. 110
Table 5-33: GPIO Port 0 to Port 3 Pullup Pulldown Selection 1 Registers............................................................. 110
Table 5-34: GPIO Port 0 to Port 3 Alternate Function Select Registers ................................................................ 111
Table 5-35: GPIO Port 0 to Port 3 Alternate Function Select Atomic Set Registers.............................................. 111
Table 5-36: GPIO Port 0 to Port 3 Alternate Function Select Clear Registers ....................................................... 111
Table 5-37: GPIO Port 0 to Port 3 Drive Strength Selection 0 Registers ............................................................... 112
Table 5-38: GPIO Port 0 to Port 3 Drive Strength Selection 1 Registers ............................................................... 112
Table 5-39: GPIO Port 0 to Port 3 Pulldown/Pullup Select Registers.................................................................... 112
Table 5-40: GPIO Port 0 Supply Voltage Select Register ....................................................................................... 112
Table 5-41: GPIO Port 1 Supply Voltage Select Register ....................................................................................... 113
Table 5-42: GPIO Port 2 Supply Voltage Select Register ....................................................................................... 113
Table 5-43: GPIO Port 3 Supply Voltage Select Register ....................................................................................... 113
Table 6-1: Internal Flash Memory Organization.................................................................................................... 115
Table 6-2: Valid Addresses for 32-bit and 128-bit Internal Flash Writes .............................................................. 116
Table 6-3: Page Boundary Address Range for Page Erase Operations.................................................................. 117
Table 6-4: Flash Controller Registers..................................................................................................................... 117
Table 6-5: Flash Controller Interrupt Register....................................................................................................... 120
Table 6-6: Flash Controller Data Register 0........................................................................................................... 120
Table 6-7: Flash Controller Data Register 1........................................................................................................... 121
Table 6-8: Flash Controller Data Register 2........................................................................................................... 121
Table 6-9: Flash Controller Data Register 3........................................................................................................... 121
Table 7-1: SPI Header Format................................................................................................................................ 124
Table 7-2: Clock Polarity and Phase Combinations ............................................................................................... 126

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Table 7-3: Encrypted Data Write Order to SPIX Flash Memory ............................................................................ 129
Table 7-4. SPIXF Master Controller Register Offsets, Names, Access and Description......................................... 129
Table 7-5. SPIXF Controller Configuration Register............................................................................................... 129
Table 7-6. SPIXF Controller Slave Select Polarity Register..................................................................................... 131
Table 7-7. SPIXF Controller General Control Register ........................................................................................... 131
Table 7-8. SPIXF Controller FIFO Control and Status Register............................................................................... 133
Table 7-9. SPIXF Controller Special Control Register............................................................................................. 134
Table 7-10. SPIXF Controller Interrupt Status Register ......................................................................................... 134
Table 7-11. SPIXF Controller Interrupt Enable Register ........................................................................................ 135
Table 7-12. SPIXF Master Controller FIFO Register Offsets, Names, Access and Description............................... 136
Table 7-13. SPIXF Master Controller TX FIFO Register .......................................................................................... 136
Table 7-14. SPIXF Master Controller TX FIFO Register .......................................................................................... 137
Table 7-15. SPIXF Master Register Addresses (Base ADDR = 0x4002 6000) ......................................................... 141
Table 7-16. SPIXF Configuration Register.............................................................................................................. 141
Table 7-17. SPIXF Fetch Control Register .............................................................................................................. 142
Table 7-18. SPIXF Mode Control Register.............................................................................................................. 143
Table 7-19. SPIXF Mode Data Register.................................................................................................................. 144
Table 7-20. SPIXF SCK Feedback Control Register................................................................................................. 144
Table 7-21. SPIXF I/O Control Register.................................................................................................................. 144
Table 7-22. SPIXF Memory Security Control Register ........................................................................................... 145
Table 7-23. SPIXF Bus Idle Detection..................................................................................................................... 145
Table 7-24. SPIXR Master Controller Register Offsets, Names, Access and Descriptions..................................... 146
Table 7-25. SPIXR FIFO Data Register.................................................................................................................... 147
Table 7-26. SPIXR Master Signals Control Register ............................................................................................... 147
Table 7-27. SPIXR Transmit Packet Size Register................................................................................................... 148
Table 7-28. SPIXR Static Configuration Register.................................................................................................... 149
Table 7-29. SPIXR Slave Select Timing Register..................................................................................................... 150
Table 7-30. SPIXR Master Baud Rate Generator ................................................................................................... 150
Table 7-31. SPIXR DMA Control Register............................................................................................................... 152
Table 7-32. SPIXR Interrupt Status Flag Register................................................................................................... 153
Table 7-33. SPIXR Interrupt Enable Register ......................................................................................................... 154
Table 7-34. SPIXR Wakeup Flag Register............................................................................................................... 155
Table 7-35. SPIXR Wakeup Enable Register........................................................................................................... 155
Table 7-36. SPIXR Active Status Register............................................................................................................... 156
Table 7-37. SPIXR External Memory Control Register........................................................................................... 156
Table 7-38: External Memory Cache Controller Register Addresses and Descriptions ........................................ 158
Table 7-39: EMCC Cache ID Register ..................................................................................................................... 158
Table 7-40: EMCC Memory Size Register .............................................................................................................. 158
Table 7-41: EMCC Cache Control Register............................................................................................................. 158
Table 7-42: EMCC Invalidate Register ................................................................................................................... 159
Table 7-43: SDHC Alternate Function Mapping to SDHC Specification Pin Names............................................... 161
Table 7-44: Registers Used to Generate SD Commands ....................................................................................... 164
Table 7-45: SDHC Register Offsets, Names and Descriptions ............................................................................... 164
Table 7-46: SDHC SDMA System Address / Argument Register............................................................................ 166
Table 7-47: SDHC SDMA Block Size Register ......................................................................................................... 166
Table 7-48: SDHC SDMA Block Count Register...................................................................................................... 168
Table 7-49: SDHC SDMA Argument 1 Register...................................................................................................... 168
Table 7-50: SDHC SDMA Transfer Mode Register ................................................................................................. 168

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Table 7-51: Summary of how register settings determine type of data transfer ................................................. 170
Table 7-52: SDHC Command Register ................................................................................................................... 170
Table 7-53: Relationship between Parameters and the Name of Response Type................................................ 171
Table 7-54: SDHC Response 0 Register.................................................................................................................. 171
Table 7-55: SDHC Response 1 Register.................................................................................................................. 171
Table 7-56: SDHC Response 2 Register.................................................................................................................. 172
Table 7-57: SDHC Response 3 Register.................................................................................................................. 172
Table 7-58: SDHC Response 4 Register.................................................................................................................. 172
Table 7-59: SDHC Response 5 Register.................................................................................................................. 172
Table 7-60: SDHC Response 6 Register.................................................................................................................. 173
Table 7-61: SDHC Response 7 Register.................................................................................................................. 173
Table 7-62: SDHC Response Register Mapping to SD Host Controller Response Register Convention................ 173
Table 7-63: Kind of SD Card Response Mapping to SDHC Response Registers..................................................... 173
Table 7-64: SDHC Buffer Data Port Register.......................................................................................................... 174
Table 7-65: SDHC Present State Register .............................................................................................................. 174
Table 7-66: SDHC Host Control 1 Register............................................................................................................. 176
Table 7-67: SDHC Power Control Register............................................................................................................. 177
Table 7-68: SDHC Block Gap Control Register....................................................................................................... 177
Table 7-69: SDHC Wakeup Control Register.......................................................................................................... 179
Table 7-70: SDHC Clock Control Register .............................................................................................................. 180
Table 7-71: SDHC Timeout Control Register.......................................................................................................... 181
Table 7-72: SDHC Software Reset Register............................................................................................................ 181
Table 7-73: SDHC Normal Interrupt Status Register ............................................................................................. 183
Table 7-74: Transfer Complete and Data Timeout Error Priority and Status........................................................ 185
Table 7-75: Command Complete and Command Timeout Error Priority and Status............................................ 185
Table 7-76: SDHC Error Interrupt Status Register ................................................................................................. 185
Table 7-77: SDHC Normal Interrupt Status Register ............................................................................................. 187
Table 7-78: SDHC Error Interrupt Status Enable Register ..................................................................................... 188
Table 7-79: SDHC Normal Interrupt Signal Enable Register.................................................................................. 189
Table 7-80: SDHC Error Interrupt Signal Enable Register...................................................................................... 190
Table 7-81: SDHC Auto CMD Error Status Register ............................................................................................... 191
Table 7-82: SDHC Host Control 2 Register............................................................................................................. 192
Table 7-83: SDHC Capabilities Register 0 .............................................................................................................. 193
Table 7-84: SDHC Capabilities Register 1 .............................................................................................................. 195
Table 7-85: SDHC Maximum Current Capabilities Register................................................................................... 196
Table 7-86: SDHC Force Event Register for Auto CMD Error Status Register........................................................ 196
Table 7-87: SDHC Force Event Register for Error Interrupt Status........................................................................ 197
Table 7-88: SDHC ADMA Error Status Register...................................................................................................... 197
Table 7-89: SDHC ADMA System Address Register 0 ............................................................................................ 199
Table 7-90: SDHC ADMA System Address Register 1 ............................................................................................ 199
Table 7-91: Preset Value Register Example........................................................................................................... 199
Table 7-92: Preset Value Register Selection Conditions ....................................................................................... 200
Table 7-93: SDHC Preset Value 0 to Preset Value 7 Registers............................................................................... 200
Table 7-94: SDHC Slot Interrupt Status Register ................................................................................................... 201
Table 7-95: SDHC Host Controller Version Register.............................................................................................. 201
Table 7-96: HyperBus, Xccela Bus Pin Mapping and Signal Descriptions.............................................................. 203
Table 7-97: HyperBus Register Names, Offsets, Access and Descriptions ............................................................ 206
Table 7-98: HBMC Status Register......................................................................................................................... 206

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Table 7-99: HBMC Interrupt Enable Control Register ........................................................................................... 207
Table 7-100: HBMC Interrupt Status Flags Register.............................................................................................. 208
Table 7-101: HBMC CS0# Memory Base Address Register.................................................................................... 208
Table 7-102: HBMC Memory Configuration 0 Registers ....................................................................................... 209
Table 7-103: HBMC Memory Timing Register 0.................................................................................................... 210
Table 7-104: Latency Value Mapped to HyperRAM and Xccela PSRAM Latency Cycles....................................... 211
Table 8-1: DMA Channel Registers........................................................................................................................ 212
Table 8-2: Channel Reload Registers..................................................................................................................... 213
Table 8-3: Source and Destination Address Definition ......................................................................................... 214
Table 8-4: Data movement from source to DMA FIFO.......................................................................................... 215
Table 8-5: Data movement from the DMA FIFO to destination............................................................................ 215
Table 8-6: DMA Channel Timer Frequency Selection............................................................................................ 217
Table 8-7: Standard DMA Registers, Offsets, Access and Descriptions................................................................. 218
Table 8-8: DMA Control Register........................................................................................................................... 219
Table 8-9: DMA Interrupt Register........................................................................................................................ 219
Table 8-10: Standard DMA Channel 0 to Channel 15 Offsets ............................................................................... 219
Table 8-11: DMAn Channel Registers, Offsets, Access and Descriptions.............................................................. 220
Table 8-12: DMA Configuration Register............................................................................................................... 220
Table 8-13: DMA Status Register........................................................................................................................... 222
Table 8-14: DMA Source Register.......................................................................................................................... 223
Table 8-15: DMA Destination Register .................................................................................................................. 224
Table 8-16: DMA Count Register........................................................................................................................... 224
Table 8-17: DMA Source Reload Register.............................................................................................................. 224
Table 8-18: DMA Destination Reload Register...................................................................................................... 224
Table 8-19: DMA Count Reload Register............................................................................................................... 225
Table 9-1: Common CRC Polynomials ................................................................................................................... 227
Table 9-2: CRC Registers........................................................................................................................................ 228
Table 9-3: CRC Control Register............................................................................................................................. 231
Table 9-4: CRC DMA Source Register .................................................................................................................... 231
Table 9-5: CRC DMA Destination Register............................................................................................................. 231
Table 9-6: CRC DMA Count Register...................................................................................................................... 231
Table 9-7: CRC Data Input Registers...................................................................................................................... 232
Table 9-8: CRC Data Output Registers................................................................................................................... 232
Table 9-9: CRC Polynomial Register....................................................................................................................... 232
Table 9-10: CRC Value Register ............................................................................................................................. 233
Table 9-11: CRC Pseudo-Random Number Generator Register............................................................................ 233
Table 10-1: ADC Clock Frequency and ADC Conversion Time (, ) ....... 236
Table 10-2: Input and Reference Scale Support by ADC Input Channel................................................................ 238
Table 10-3: ADC Data Register Alignment Options ............................................................................................... 238
Table 10-4. ADC Registers, Offsets and Descriptions............................................................................................ 241
Table 10-5: ADC Control Register.......................................................................................................................... 242
Table 10-6: ADC Status Register............................................................................................................................ 243
Table 10-7: ADC Data Register .............................................................................................................................. 243
Table 10-8: ADC Interrupt Control Register .......................................................................................................... 244
Table 10-9: ADC Limit 0 to 3 Registers .................................................................................................................. 244
Table 11-1: CLCD Pins and Signal Description ....................................................................................................... 249
Table 11-2: CLCD Data Format Little Endian Byte, Little Endian Pixel (LBLP)........................................................ 251
Table 11-3: CLCD Data Format Big Endian Byte, Big Endian Pixel (BBBP) ............................................................. 251

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Table 11-4: CLCD Data Format Little Endian Byte, Big Endian Pixel (LBBP)........................................................... 252
Table 11-5 Palette RAM Data Format for CLCD_PALETTE_RAM[0:255] Registers................................................ 252
Table 11-6 STN Data Output Format per Clock Cycle............................................................................................ 253
Table 11-7 LCD Panel Signals................................................................................................................................. 253
Table 11-8 PCLK to PIXEL Clock Divide Ratios....................................................................................................... 254
Table 11-9 LCD Interface Register Offsets, Names and Descriptions.................................................................... 255
Table 11-10: CLCD Clock Register.......................................................................................................................... 255
Table 11-11: CLCD Vertical Timing Register 0 ....................................................................................................... 256
Table 11-12: CLCD Vertical Timing Register 1 ....................................................................................................... 257
Table 11-13: CLCD Horizontal Timing Register...................................................................................................... 258
Table 11-14: CLCD Control Register ...................................................................................................................... 258
Table 11-15: CLCD Frame Buffer Register ............................................................................................................. 260
Table 11-16: CLCD Interrupt Enable Register........................................................................................................ 260
Table 11-17: CLCD Interrupt Status Register......................................................................................................... 261
Table 11-18: CLCD Palette RAM Registers 0 to 255 .............................................................................................. 261
Table 12-1: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps ................................................. 264
Table 12-2: UART Register Offsets, Names, Access and Descriptions................................................................... 265
Table 12-3: UART Control 0 Register..................................................................................................................... 266
Table 12-4: UART Control 1 Register..................................................................................................................... 267
Table 12-5: UART Status Register.......................................................................................................................... 267
Table 12-6: UART Interrupt Enable Register ......................................................................................................... 269
Table 12-7: UART Interrupt Flags Register ............................................................................................................ 269
Table 12-8: UART Rate Integer Register................................................................................................................ 271
Table 12-9: UART Baud Rate Decimal Register ..................................................................................................... 271
Table 12-10: UART FIFO Register........................................................................................................................... 271
Table 12-11: UART DMA Configuration Register................................................................................................... 272
Table 12-12: UART TX FIFO Data Output Register................................................................................................. 272
Table 13-1: I2C Address Byte Format..................................................................................................................... 278
Table 13-2: I2C Registers....................................................................................................................................... 283
Table 13-3: I2C Control 0 Register.......................................................................................................................... 284
Table 13-4: I2C Status Register .............................................................................................................................. 285
Table 13-5: I2C Interrupt Flag 0 Register ............................................................................................................... 286
Table 13-6: I2C Interrupt Enable 0 Register........................................................................................................... 288
Table 13-7: I2C Interrupt Flag 1 Register ............................................................................................................... 290
Table 13-8: I2C Interrupt Enable 1 Register........................................................................................................... 290
Table 13-9: I2C FIFO Length Register ..................................................................................................................... 291
Table 13-10: I2C Receive Control 0 Register.......................................................................................................... 291
Table 13-11: I2C Receive Control 1 Register.......................................................................................................... 292
Table 13-12: I2C Transmit Control 0 Register ........................................................................................................ 292
Table 13-13: I2C Transmit Control 1 Register ........................................................................................................ 293
Table 13-14: I2C Data Register............................................................................................................................... 293
Table 13-15: I2C Master Mode Control Register.................................................................................................... 294
Table 13-16: I2C SCL Low Control Register ............................................................................................................ 294
Table 13-17: I2C SCL High Control Register............................................................................................................ 294
Table 13-18: I2C Timeout Register......................................................................................................................... 295
Table 13-19: I2C Slave Address Register ................................................................................................................ 295
Table 13-20: I2C DMA Register .............................................................................................................................. 296
Table 14-1: Pulse Train Engine Registers............................................................................................................... 300