Microchip Technology dsPIC33 series User manual

2013-2019 Microchip Technology Inc. DS30003035B-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ...................................................................................................................... 2
2.0 Registers.......................................................................................................................... 3
3.0 Register Map.................................................................................................................... 4
4.0 Time Base Generator..................................................................................................... 17
8.0 Module Sync Outputs..................................................................................................... 57
9.0 Sync and Triggered Operation ....................................................................................... 58
5.0 Timer Modes ..................................................................................................................18
10.0 Operation During Sleep and Idle Modes........................................................................ 64
10.0 Operation During Sleep and Idle Modes........................................................................ 64
10.0 Operation During Sleep and Idle Modes........................................................................ 64
11.0 Effects of a Reset........................................................................................................... 64
12.0 Related Application Notes.............................................................................................. 65
13.0 Revision History ............................................................................................................. 66
Capture/Compare/PWM/Timer (MCCP and SCCP)

dsPIC33/PIC24 Family Reference Manual
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1.0 INTRODUCTION
Select dsPIC33/PIC24 family devices include one or more Capture/Compare/PWM/Timer (CCP)
modules. These modules are similar to the multipurpose timer modules found on many other
16-bit microcontrollers. They also provide the functionality of the comparable Input Capture, Output
Compare and General Purpose Timer peripherals found in all other devices.
CCP modules can operate in one of three major modes:
• General Purpose Timer
• Input Capture
• Output Compare/PWM
There are two different forms of the module, distinguished by the number of PWM outputs that
the module can generate. Single output modules (SCCPs) provide only one PWM output.
Multiple output modules (MCCPs) can provide up to six outputs and an extended range of output
control features, depending on the pin count of the particular device.
All modules (SCCP and MCCP) include these features.
• User-Selectable Clock Inputs, Including System Clock and External Clock Input Pins
• Input Clock Prescaler for Time Base
• Output Postscaler for Module Interrupt Events or Triggers
• Synchronization Output Signal for Coordinating Other MCCP/SCCP Modules
with User-Configurable Alternate and Auxiliary Source Options
• Fully Asynchronous Operation in All Modes and in Low-Power Operation
• Special Output Trigger for A/D Conversions
• 16-Bit and 32-Bit General Purpose Timer Modes with Optional Gated Operation for Simple
Time Measurements
• Capture Modes:
- Backward compatible with previous Input Capture peripherals of the dsPIC33/PIC24 families
- 16-bit or 32-bit capture of time base on external event
- Up to four-level deep FIFO capture buffer
- Capture source input multiplexer
- Gated capture operation to reduce noise-induced false captures
• Output Compare/PWM Modes:
- Backward compatible with previous Output Compare peripherals of the dsPIC33/PIC24 families
- Single Edge and Dual Edge Compare modes
- Center-Aligned Compare mode
- Variable Frequency Pulse mode
- External Input mode
MCCP modules also include these extended PWM features:
• Single Output Steerable mode
• Brush DC Motor (Forward and Reverse) Modes
• Half-Bridge with Dead-Time Delay
• Push-Pull PWM Mode
• Output Scan Mode
• Auto-Shutdown with Programmable Source and Shutdown State
• Programmable Output Polarity
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the “Capture/Compare/PWM/Timer
Modules (SCCP/MCCP)” chapter in the current device data sheet to check
whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Website at: http://www.microchip.com

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Capture/Compare/PWM/Timer (MCCP and SCCP)
The SCCP and MCCP modules can be operated only in one of the three major modes (Capture,
Compare or Timer) at any time. The other modes are not available unless the module is
reconfigured.
A conceptual block diagram for the module is shown in Figure 1-1. All three modes use the Time
Base Generator and the common Timer register pair (CCPxTMRH/L). Other shared hardware
components, such as comparators and buffer registers, are activated and used as a particular
mode requires.
Figure 1-1: MCCP/SCCP Conceptual Block Diagram
2.0 REGISTERS
Each MCCP/SCCP module has up to seven control and status registers and eight buffer/counter
registers:
• CCPxTMRH and CCPxTMRL are the 32-Bit Timer/Counter register pair
• CCPxPRH and CCPxPRL are the 32-Bit Timer Period register pair
• CCPxRA is the 16-bit primary data buffer for Output Compare operations
• CCPxRB is the 16-bit secondary data buffer for Output Compare operations
• CCPxBUFH and CCPxBUFL are the 32-Bit Buffer register pair, which are used in Input
Capture FIFO operations
Time Base
Generator
Clock
Sources
Input Capture
Output Compare/
PWM
T32
CCSEL
MOD[3:0]
Sync and
Gating
Sources
16/32-Bit
Auxiliary Output
CCPxIF
CCTxIF
External
Capture
Compare/PWM
Output(s)
OCFA/OCFB
Timer
CCP Sync Out
Special Event Trigger Out (A/D)
Input
CCPxTMRH/L

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3.0 REGISTER MAP
A summary of the registers associated with the CCP modules (MCCP and SCCP) is shown in Tab le 3 -1 . This represents the superset
MCCP module; registers and individual bits that are not implemented in the SCCP module are noted.
Table 3-1: MCCP/SCCP Module Register Map
Register
Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
CCPxCON1L CCPON — CCPSIDL CCPSLP TMRSYNC CLKSEL[2:0] TMRPS[1:0] T32 CCSEL MOD[3:0] 0000
CCPxCON1H OPSSRC RTRGEN —— OPS[3:0] TRIGEN ONESHOT ALTSYNC SYNC[4:0] 0000
CCPxCON2L PWMRSEN ASDGM — SSDG — — — —ASDG[7:0]0000
CCPxCON2H OENSYNC — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN ICGSM[1:0] — AUXOUT[1:0] ICS[2:0] 0100
CCPxCON3L — — — — — — — — — —DT[5:0]0000
CCPxCON3H OETRIG OSCNT[2:0] —OUTM[2:0}—— POLACE POLBDF PSSACE[1:0] PSSBDF[1:0] 0000
CCPxSTATL — — — — — — — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000
CCPxTMRL CCPx Time Base Register, Low Word 0000
CCPxTMRH CCPx Time Base Register, High Word 0000
CCPxPRL CCPx Period Register, Low Word FFFF
CCPxPRH CCPx Period Register, High Word FFFF
CCPxRA CCPx Primary Compare Register 0000
CCPxRB CCPx Secondary Compare Register 0000
CCPxBUFL CCPx Capture Buffer Register, Low Word 0000
CCPxBUFH CCPx Capture Buffer Register, High Word 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-1: CCPxCON1L: Capture/Compare/PWMx Control 1 Low Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCPON — CCPSIDL CCPSLP TMRSYNC CLKSEL[2:0](1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMRPS[1:0] T32 CCSEL MOD[3:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CCPON: CCPx Module Enable
1= Module is enabled with operating mode specified by MOD[3:0]
0= Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 CCPSIDL: CCPx Stop in Idle Mode Bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12 CCPSLP: CCPx Sleep Mode Enable bit
1= Module continues to operate in Sleep modes
0= Module does not operate in Sleep modes
bit 11 TMRSYNC: Time Base Clock Synchronization bit
1= Module time base clock is synchronized to internal system clocks; timing restrictions apply
0= Module time base clock is not synchronized to internal system clocks
bit 10-8 CLKSEL[2:0]: CCPx Time Base Clock Select bits(1)
111 = Clock 7
110 = Clock 6
101 = Clock 5
100 = Clock 4
011 = Clock 3
010 = Clock 2
001 = Clock 1
000 = System Clock (TCY)
bit 7-6 TMRPS[1:0]: CCPx Time Base Prescale Select bits
11 = 1:64 Prescaler
10 = 1:16 Prescaler
01 = 1:4 Prescaler
00 = 1:1 Prescaler
bit 5 T32: 32-Bit Time Base Select bit
1= 32-bit time base for timer, single edge Output Compare or Input Capture function
0= 16-bit time base for timer, single edge Output Compare or Input Capture function
bit 4 CCSEL: Capture/Compare Mode Select bit
1= Input Capture mode
0= Output Compare/PWM or Timer mode (exact function selected by MOD[3:0] bits)
Note 1: Refer to the device data sheet for available clock sources for a specific device family.

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bit 3-0 MOD[3:0]: CCPx Mode Select bits
CCSEL = 1(Input Capture modes):
1xxx = Reserved
011x = Reserved
0101 = Capture every 16th rising edge
0100 = Capture every 4th rising edge
0011 = Capture every rising and falling edge
0010 = Capture every falling edge
0001 = Capture every rising edge
0000 = Capture every rising and falling edge (Edge Detect mode)
CCSEL = 0(Output Compare modes):
1111 = External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110 = Reserved
110x = Reserved
10xx = Reserved
0111 = Variable Frequency Pulse mode
0110 = Center-Aligned Pulse Compare mode, buffered
0101 = Dual Edge Compare mode, buffered
0100 = Dual Edge Compare mode
0011 = 16-Bit/32-Bit Single Edge mode: Toggles output on compare match
0010 = 16-Bit/32-Bit Single Edge mode: Drives output low on compare match
0001 = 16-Bit/32-Bit Single Edge mode: Drives output high on compare match
0000 = 16-Bit/32-Bit Timer mode: Output functions are disabled
Register 3-1: CCPxCON1L: Capture/Compare/PWMx Control 1 Low Register (Continued)
Note 1: Refer to the device data sheet for available clock sources for a specific device family.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-2: CCPxCON1H: Capture/Compare/PWMx Control 1 High Register
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
OPSSRC(1)RTRGEN(2)—— OPS[3:0](3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRIGEN ONESHOT ALTSYNC SYNC[4:0](3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OPSSRC: Output Postscaler Source Select bit(1)
1= Output postscaler scales Special Event Trigger output events
0= Output postscaler scales timer interrupt events
bit 14 RTRGEN: Retrigger Enable bit(2)
1= Time base can be retriggered when CCPTRIG = 1
0= Time base may not be retriggered when CCPTRIG = 1
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 OPS[3:0]: CCPx Interrupt Output Postscale Select bits(3)
1111 = Interrupt every 16th time base period match
1110 = Interrupt every 15th time base period match
...
0100 = Interrupt every 5th time base period match
0011 = Interrupt every 4th time base period match or 4th Input Capture event
0010 = Interrupt every 3rd time base period match or 3rd Input Capture event
0001 = Interrupt every 2nd time base period match or 2nd Input Capture event
0000 = Interrupt after each time base period match or Input Capture event
bit 7 TRIGEN: CCPx Triggered Enable bit
1= Triggered operation of timer is enabled
0= Triggered operation of timer is disabled
bit 6 ONESHOT: One-Shot Mode Enable bit
1= One-Shot Triggered mode is enabled; trigger duration is set by OSCNT[2:0]
0= One-Shot Triggered mode is disabled
bit 5 ALTSYNC: CCPx Alternate Synchronization Output Signal Select bit
1= An alternate signal is used as the module synchronization output signal
0= The module synchronization output signal is the Time Base Reset/rollover event
bit 4-0 SYNC[4:0]: CCPx Synchronization Source Select bits(4)
11111 = Timer is in the Free-Running mode and rolls over at FFFFh (period register is ignored)
11110 = Timer is synchronized to Source #30
...
00001 = Time base is synchronized to Source #1
00000 = No external synchronization; timer rolls over at FFFFh or matches with period register
Note 1: Control bit has no function in Input Capture modes.
2: Control bit has no function when TRIGEN = 0.
3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.
4: Refer to the device data sheet for Sync sources for a specific device family.

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Register 3-3: CCPxCON2L: Capture/Compare/PWMx Control 2 Low Register
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
PWMRSEN ASDGM — SSDG — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ASDG[7:0](1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWMRSEN: CCPx PWM Restart Enable bit
1= ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input
has ended
0= ASEVT bit must be cleared in software to resume PWM activity on output pins
bit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit
1= Waits until next Time Base Reset or rollover for shutdown to occur
0= Shutdown event occurs immediately
bit 13 Unimplemented: Read as ‘0’
bit 12 SSDG: CCPx Software Shutdown/Gate Control bit
1= Manually forces auto-shutdown, timer clock gate or Input Capture signal gate event (setting of
ASDGM bit still applies)
0= Normal module operation
bit 11-8 Unimplemented: Read as ‘0’
bit 7-0 ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits(1)
1= Auto-Shutdown/Gating Source n is enabled
0= Auto-Shutdown/Gating Source n is disabled
Note 1: Refer to the device data sheet for the specific gating sources implemented for a device family.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-4: CCPxCON2H: Capture/Compare/PWMx Control 2 High Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
OENSYNC —OCFEN
(1)OCEEN(1)OCDEN(1)OCCEN(1)OCBEN(1)OCAEN
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ICGSM[1:0] — AUXOUT[1:0](2)ICS[2:0](3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OENSYNC: Output Enable Synchronization bit
1= Update by output enable bits occurs on the next Time Base Reset or rollover
0= Update by output enable bits occurs immediately
bit 14 Unimplemented: Read as ‘0’
bit 13-8 OC[F:A]EN: Output Enable/Steering Control bits(1)
1= OCx pin is controlled by the CCPx module and produces an Output Compare or PWM signal
0= OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
bit 7-6 ICGSM[1:0]: Input Capture Gating Source Mode Control bits
11 = Reserved
10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low
level will disable future capture events.
bit 5 Unimplemented: Read as ‘0’
bit 4-3 AUXOUT[1:0]: Auxiliary Output Signal on Event Selection bits(2)
11 = Input Capture or Output Compare event; no signal in Timer mode
10 = Signal output depends on module operating mode (see Tabl e 8 -2)
01 = Time base rollover event (all modes)
00 = Disabled
bit 2-0 ICS[2:0]: Input Capture Source Select bits(3)
111 = Capture Source 8
110 = Capture Source 7
101 = Capture Source 6
100 = Capture Source 5
011 = Capture Source 4
010 = Capture Source 3
001 = Capture Source 2
000 = Capture Source 1 (ICx pin)
Note 1: OCFEN through OCBEN (bits[13:9]) are implemented in MCCP modules only.
2: Auxiliary output is not implemented in all devices. Refer to the device data sheet for details.
3: Refer to the device data sheet for specific Input Capture sources.

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Register 3-5: CCPxCON3L: Capture Compare PWMx Control 3 Low Register(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——DT[5:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 DT[5:0]: PWM Dead-Time Select bits
111111 = Inserts 63 dead-time delay periods between complementary output signals
111110 = Inserts 62 dead-time delay periods between complementary output signals
...
000010 = Inserts 2 dead-time delay periods between complementary output signals
000001 = Inserts 1 dead-time delay period between complementary output signals
000000 = Dead-time logic is disabled
Note 1: This register is implemented in MCCP modules only.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-6: CCPxCON3H: Capture/Compare/PWMx Control 3 High Register
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
OETRIG OSCNT[2:0] —OUTM[2:0]
(1)
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——POLACEPOLBDF
(1)PSSACE[1:0] PSSBDF[1:0](1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OETRIG: PWM Dead-Time Select bit
1= For Triggered mode (TRIGEN = 1), module does not drive enabled output pins until triggered
0= Normal output pin operation
bit 14-12 OSCNT[2:0]: One-Shot Event Count bits
Extends the duration of a one-shot trigger event by an additional n clock cycles (n+1 total cycles)
111 = 7 timer count periods (8 cycles total)
110 = 6 timer count periods (7 cycles total)
101 = 5 timer count periods (6 cycles total)
100 = 4 timer count periods (5 cycles total)
011 = 3 timer count periods (4 cycles total)
010 = 2 timer count periods (3 cycles total)
001 = 1 timer count period (2 cycles total)
000 = Does not extend one-shot trigger event (the event takes 1 timer count period)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 OUTM[2:0]: PWMx Output Mode Control bits(1)
111 = Reserved
110 = Output Scan mode
101 = Brush DC Output mode, forward
100 = Brush DC Output mode, reverse
011 = Reserved
010 = Half-Bridge Output mode
001 = Push-Pull Output mode
000 = Steerable Single Output mode
bit 7-6 Unimplemented: Read as ‘0’
bit 5 POLACE: CCPx Output Pins, OCxA, OCxC and OCxE, Polarity Control bit
1= Output pin polarity is active-low
0= Output pin polarity is active-high
bit 4 POLBDF: CCPx Output Pins, OCxB, OCxD and OCxF, Polarity Control bit(1)
1= Output pin polarity is active-low
0= Output pin polarity is active-high
bit 3-2 PSSACE[1:0]: PWMx Output Pins, OCxA, OCxC and OCxE, Shutdown State Control bits
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are in high-impedance state when a shutdown event occurs
bit 1-0 PSSBDF[1:0]: PWMx Output Pins, OCxB, OCxD, and OCxF, Shutdown State Control bits(1)
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are in high-impedance state when a shutdown event occurs
Note 1: These bits are implemented in MCCP modules only.

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Register 3-7: CCPxSTATL: Capture/Compare/PWMx Status Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0 W1-0 W1-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE
bit 7 bit 0
Legend: C = Clearable Only bit
R = Readable bit W1 = Write ‘1’ Only bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 CCPTRIG: CCPx Trigger Status bit
1= Timer has been triggered and is running (set by hardware or writing to TRSET)
0= Timer has not been triggered and is held in Reset (cleared by writing to TRCLR)
bit 6 TRSET: CCPx Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1(location always reads ‘0’).
bit 5 TRCLR: CCPx Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1(location always reads ‘0’).
bit 4 ASEVT: CCPx Auto-shutdown Event Status/Control bit
1= A shutdown event is in progress; CCPx outputs are in the Shutdown state
0= CCPx outputs operate normally
bit 3 SCEVT: Single Edge Compare Event Status bit
1= A single edge compare event has occurred
0= A single edge compare event has not occurred
bit 2 ICDIS: Input Capture Disable bit
1= Event on Input Capture pin does not generate a capture event
0= Event on Input Capture pin will generate a capture event
bit 1 ICOV: Input Capture Buffer Overflow Status bit
1= The Input Capture FIFO buffer has overflowed
0= The Input Capture FIFO buffer has not overflowed
bit 0 ICBNE: Input Capture Buffer Status bit
1= Input Capture buffer has data available
0= Input Capture buffer is empty

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-8: CCPxTMRL: CCPx Time Base Low Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TMRL[15:0]: 16-Bit Time Base Value bits
Register 3-9: CCPxTMRH: CCPx Time Base High Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR[31:24]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TMRH[31:16]: 16-Bit Time Base Value bits

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Register 3-10: CCPxPRL: CCPx Period Low Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRL[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRL[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PRL[15:0]: Period Register bits
Register 3-11: CCPxPRH: CCPx Period High Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRH[31:24]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRH[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PRH[31:16]: Period Register bits

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-12: CCPxRA: CCPx Primary Compare Register (Timer/Compare Modes Only)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMP[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMP[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CMP[15:0]: Compare Value bits
The 16-bit value to be compared against the CCPx time base.
Register 3-13: CCPxRB: CCPx Secondary Compare Register (Timer/Compare Modes Only)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMP[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMP[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CMP[15:0]: Compare Value bits
The 16-bit value to be compared against the CCPx time base.

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Register 3-14: CCPxBUFL: CCPx Capture Buffer Low Register (Capture Modes Only)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUF[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUF[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 BUF[15:0]: Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
Register 3-15: CCPxBUFH: CCPx Capture Buffer High Register (Capture Modes Only)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUF[31:24]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUF[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 BUF[31:16]: Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.

2013-2019 Microchip Technology Inc. DS30003035B-page 17
Capture/Compare/PWM/Timer (MCCP and SCCP)
4.0 TIME BASE GENERATOR
The Time Base Generator (TBG) provides a time base for the rest of the module using clock sig-
nals available on the microcontroller. This serves not only as the time base for the Timer modes,
but also allows Input Capture and Output Compare pre-modes to operate without depending on
another on-chip timer module.
Up to eight clock inputs are available to the clock generator, including the system clock (TCY) and
other on-chip oscillator sources. Depending on the device, external clock inputs may also be
available. A prescaler divides the selected clock source to a suitable frequency for use by the
module.
The TBG has the ability to synchronize its operation with the selected clock source, subject to
input timing restrictions or the module’s operating conditions. Setting the TMRSYNC bit
(CCPxCON1L[11]) enables synchronization of the time base with the clock input.
The TBG is shown in Figure 4-1.
Figure 4-1: Time Base Clock Generator
4.1 Gating Logic
The Time Base Generator incorporates a hardware gate that can disable the timer increment
clock to the timer gate, which is available on Timer modes only.
Gating is controlled using the ASDG[7:0] control bits (CCPxCON2L[7:0]) and the SSDG bit
(CCPxCON2L[12]). All of these bits are logically ORed together to generate a gating enable
signal for the TBG.
Setting any one of the ASDGx bits enables its corresponding hardware trigger; any or all of the
bits may be set to select multiple sources. The available sources for gating and auto-shutdown
are device-dependent, and typically include such sources as comparator outputs, I/O pins
(including OCFA and OCFB for PWM operation), software control and so on. Any output signal
from any of the enabled sources disables the TBG output. Events are generally level-sensitive
and not edge-triggered.
The SSDG bit is simply a gating source that can be manipulated in software. Setting SSDG has
the same effect as an input from any of the hardware sources.
The gating feature is described in the following sections:
• Timer Gating (see Section 5.3 “Clock Gating For Timer Modes”)
• Auto-Shutdown for Output Compare, MCCP modules (see Section 7.6.11 “Auto-Shutdown
Control”)
• Gated Input Capture (see Section 6.4.1 “Input Capture Signal Gating”)
Regardless of the operating mode, interrupt events are not generated by the CCP module based
on the status of the gating inputs. If an interrupt is required for a gating event, the gating source
itself must be used to generate the interrupt.
CLKSEL[2:0]
TMRPS[1:0]
Prescaler Clock
Synchronizer
TMRSYNC
Gate
SSDG
Clock
Sources
To R e st
of Module

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5.0 TIMER MODES
When CCSEL = 0and MOD[3:0] = 0000, the module functions as a timer. There are two basic
Timer modes, selected by the T32 bit (CCPxCON1L[5]); these are shown in Table 5- 1. In either
mode, the timer can operate as a free-running timer/counter, operate synchronously with other
modules, or be triggered by other modules or external events.
Table 5-1: Timer Operating Modes
5.1 Dual 16-Bit Timer Mode
Dual 16-Bit Timer mode is selected when T32 = 0. This mode is useful for the following functions:
• Periodic CPU Interrupts
• Master Time Base Function for Synchronizing Other CCP Modules
• Triggering Periodic A/D Conversion
• Periodic Wake from Sleep (if an appropriate clock source is available)
Dual 16-Bit Timer mode provides a simple timer function with two independent 16-bit timer/counters,
as shown in Figure 5-1. The primary timer, based on the lower word of the CCPxTMR pair
(CCPxTMRL), is fully functional and can interact with other modules on the device. It can generate
the CCP Sync signals for use by other MCCP modules. It can also use the SYNC[4:0] signal gener-
ated by other modules. The secondary timer, based on the upper word of CCPxTMR (CCPxTMRH),
has limited functionality. It is intended to be used only as a periodic interrupt source for scheduling
CPU events. It does not generate an output trigger signal like the primary time base.
Figure 5-1: 16-Bit Dual Timer Mode
T32 Operating Mode
0Dual Timer Mode (16-bit)
1Timer Mode (32-bit)
Note: The CCPxTMRH/L registers may not be readable by the user if a high-speed
asynchronous clock source is used to clock the time base. For a low-speed read, a
double read can be done and the results compared.
Comparator
CCPxTMRL
Comparator
CCPxPRL
CCPxRB
CCPxTMRH
CCPxPRH
Comparator
Clock
Sources
Set CCTxIF
Special Event Trigger
Set CCPxIF
Reset/
Trigger
Control
SYNC[4:0]
Time Base
Generator

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Both the primary and secondary timers use the same clock source from the TBG, as selected by
CLKSEL[2:0]. The CCPxTMRH/L registers provide user access to the two 16-bit time bases.
Both Timer registers (CCPxTMRL and CCPxTMRH) increment at the same time, based on the
timer input; however, only the primary timer (CCPxTMRL) can use the timer Sync functionality.
The secondary timer (CCPxTMRH) does not have timer Sync functionality.
The CCPxPRL register controls the period for the primary 16-bit time base when
SYNC[4:0] = 00000. When the module is configured to use an external synchronization source,
the primary 16-bit time base is reset when the source selected by SYNC[4:0] is asserted. The
module’s Sync signal is generated whenever the time base rolls over or is reset to ‘0’.
The primary timer can generate the CCP interrupt when the value of CCPxTMRL resets to
0000h. When SYNC[4:0] = 00000, this occurs when CCPxTMRL matches CCPxPRL. If
SYNC[4:0] is not ‘00000’, CCPxTMRL resets and generates a CCT Interrupt Flag (CCTxIF)
event whenever the signal selected by SYNC[4:0] is asserted.
The CCPxPRH register controls the count period of the secondary 16-bit timer. The secondary
timer does not support external synchronization and is not affected by the selected SYNC[4:0]
input. The secondary time base begins counting when the CCPON bit (CCPxCON1L[15]) is set.
When a match occurs between the CCPxPRH register and the CCPxTMRH count value, the
secondary 16-bit time base is reset and a timer rollover interrupt event (CCPxIF) is generated.
If either of the 16-bit timers is not used in the application, the timer can be disabled by writing
0000h to the corresponding period register. The timer is held in Reset, and no interrupts are
generated, as long as the period register’s value is 0. The CCPxPRH and CCPxPRL registers
are not buffered in this operating mode.
To use the module in Dual 16-Bit Timer mode:
1. Set CCSEL = 0to select the Time Base/Output Compare mode of the module.
2. Set T32 = 0to select the 16-bit time base operation.
3. Set MOD[3:0] = 0000 to select the Time Base mode.
4. Set SYNC[4:0] to the desired time base synchronization source:
- Configure and enable the external source selected by SYNC[4:0] before enabling
the timer.
- If the timer is not using an external Sync source (SYNC[4:0] = 00000), or if the module
is synchronizing to itself (the SYNC[4:0] bits select the module’s own value as a Sync
source), write the desired count period of the primary 16-bit time base to CCPxPRL.
5. If the secondary timer is also being used, write a non-zero value to CCPxPRH to specify
the count period.
6. If the special A/D trigger is being used, set CCPxRB for the desired trigger output time
7. Enable the module by setting the CCPON bit.
8. If an external synchronization source is selected in Step 4, configure and enable that
source to allow the primary 16-bit time base to begin counting.
5.1.1 SPECIAL EVENT TRIGGER
In select devices, the Dual 16-Bit Timer mode can be used to generate a Special Event Trigger
output signal. Refer to the device-specific data sheet’s ADC trigger source for availability. The
primary timer can be used to start A/D conversions and trigger other peripheral events. The
trigger period is set by the value of the CCPxRB register and must be less than the counter
period, as defined by the CCPxPRL register.

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5.2 32-Bit Timer Mode
The 32-Bit Timer mode is selected when T32 = 1. In this mode, the CCPxTMRL and CCPxTMRH
registers function together as a 32-bit timer. When CCPxTMRL overflows, CCPxTMRH
increments by one.
This mode provides a simple timer function when it is important to track long time periods. It is
useful for the following functions:
• Periodic CPU Interrupts
• Synchronization and Trigger Generation for Other CCP Modules
• Periodic ADC Conversion Triggering
• Periodic Wake from Sleep (if an appropriate clock source is available)
No input or output functions are available from the CCP module in this operating mode.
Figure 5-2: 32-Bit Timer Mode
When external synchronization is not selected (SYNC[4:0] = 00000), the CCPxPRH/L registers
set the count period for the timer. A match between the CCPxTMR and the CCPxPRH registers
also automatically generates the Sync output signal whenever the module is enabled
(CCPON = 1).
To use the module in 32-Bit Timer mode:
1. Set CCSEL = 0to select the Time Base/Output Compare mode of the module.
2. Set T32 = 1to select the 32-bit time base operation.
3. Set MOD[3:0] = 0000 to select the Time Base mode.
4. Set SYNC[4:0] to the desired timer synchronization source:
- Configure and enable the external source selected by SYNC[4:0] before enabling
the timer.
- If the timer is not using an external Sync source (SYNC[4:0] = 00000), or if the module
is synchronizing to itself (SYNC[4:0] selects the module’s own value as a Sync
source), write the desired count period of the primary 16-bit time base to CCPxPRL/H.
5. Enable the module by setting the CCPON bit.
5.3 Clock Gating For Timer Modes
When operating in Timer mode, time base gating can be used to gate the timer’s operation (see
Section 4.1 “Gating Logic” for more information). This function provides a simple way to
measure the time of an external event. Timer clock gating is enabled whenever one or more of
the ASDG[7:0] bits (CCPxCON2L[7:0]) is set, or when the SSDG bit (CCPxCON2L[12]) is set.
Note: To avoid reading during an overflow, read the CCPxTMRL register first to make
certain that it is not about to roll over.
CCPxTMRL
CCPxPRL
Comparator Set CCTxIF
CCPxTMRH
CCPxPRH
Clock
Sources
Reset/
Trigger
Control
SYNC[4:0]
or Special Event Trigger
Time Base
Generator