Microchip Technology dsPIC33 series User manual

2013-2019 Microchip Technology Inc. DS30003035B-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ...................................................................................................................... 2
2.0 Registers.......................................................................................................................... 3
3.0 Register Map.................................................................................................................... 4
4.0 Time Base Generator..................................................................................................... 17
8.0 Module Sync Outputs..................................................................................................... 57
9.0 Sync and Triggered Operation ....................................................................................... 58
5.0 Timer Modes ..................................................................................................................18
10.0 Operation During Sleep and Idle Modes........................................................................ 64
10.0 Operation During Sleep and Idle Modes........................................................................ 64
10.0 Operation During Sleep and Idle Modes........................................................................ 64
11.0 Effects of a Reset........................................................................................................... 64
12.0 Related Application Notes.............................................................................................. 65
13.0 Revision History ............................................................................................................. 66
Capture/Compare/PWM/Timer (MCCP and SCCP)

dsPIC33/PIC24 Family Reference Manual
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1.0 INTRODUCTION
Select dsPIC33/PIC24 family devices include one or more Capture/Compare/PWM/Timer (CCP)
modules. These modules are similar to the multipurpose timer modules found on many other
16-bit microcontrollers. They also provide the functionality of the comparable Input Capture, Output
Compare and General Purpose Timer peripherals found in all other devices.
CCP modules can operate in one of three major modes:
• General Purpose Timer
• Input Capture
• Output Compare/PWM
There are two different forms of the module, distinguished by the number of PWM outputs that
the module can generate. Single output modules (SCCPs) provide only one PWM output.
Multiple output modules (MCCPs) can provide up to six outputs and an extended range of output
control features, depending on the pin count of the particular device.
All modules (SCCP and MCCP) include these features.
• User-Selectable Clock Inputs, Including System Clock and External Clock Input Pins
• Input Clock Prescaler for Time Base
• Output Postscaler for Module Interrupt Events or Triggers
• Synchronization Output Signal for Coordinating Other MCCP/SCCP Modules
with User-Configurable Alternate and Auxiliary Source Options
• Fully Asynchronous Operation in All Modes and in Low-Power Operation
• Special Output Trigger for A/D Conversions
• 16-Bit and 32-Bit General Purpose Timer Modes with Optional Gated Operation for Simple
Time Measurements
• Capture Modes:
- Backward compatible with previous Input Capture peripherals of the dsPIC33/PIC24 families
- 16-bit or 32-bit capture of time base on external event
- Up to four-level deep FIFO capture buffer
- Capture source input multiplexer
- Gated capture operation to reduce noise-induced false captures
• Output Compare/PWM Modes:
- Backward compatible with previous Output Compare peripherals of the dsPIC33/PIC24 families
- Single Edge and Dual Edge Compare modes
- Center-Aligned Compare mode
- Variable Frequency Pulse mode
- External Input mode
MCCP modules also include these extended PWM features:
• Single Output Steerable mode
• Brush DC Motor (Forward and Reverse) Modes
• Half-Bridge with Dead-Time Delay
• Push-Pull PWM Mode
• Output Scan Mode
• Auto-Shutdown with Programmable Source and Shutdown State
• Programmable Output Polarity
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the “Capture/Compare/PWM/Timer
Modules (SCCP/MCCP)” chapter in the current device data sheet to check
whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Website at: http://www.microchip.com

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Capture/Compare/PWM/Timer (MCCP and SCCP)
The SCCP and MCCP modules can be operated only in one of the three major modes (Capture,
Compare or Timer) at any time. The other modes are not available unless the module is
reconfigured.
A conceptual block diagram for the module is shown in Figure 1-1. All three modes use the Time
Base Generator and the common Timer register pair (CCPxTMRH/L). Other shared hardware
components, such as comparators and buffer registers, are activated and used as a particular
mode requires.
Figure 1-1: MCCP/SCCP Conceptual Block Diagram
2.0 REGISTERS
Each MCCP/SCCP module has up to seven control and status registers and eight buffer/counter
registers:
• CCPxTMRH and CCPxTMRL are the 32-Bit Timer/Counter register pair
• CCPxPRH and CCPxPRL are the 32-Bit Timer Period register pair
• CCPxRA is the 16-bit primary data buffer for Output Compare operations
• CCPxRB is the 16-bit secondary data buffer for Output Compare operations
• CCPxBUFH and CCPxBUFL are the 32-Bit Buffer register pair, which are used in Input
Capture FIFO operations
Time Base
Generator
Clock
Sources
Input Capture
Output Compare/
PWM
T32
CCSEL
MOD[3:0]
Sync and
Gating
Sources
16/32-Bit
Auxiliary Output
CCPxIF
CCTxIF
External
Capture
Compare/PWM
Output(s)
OCFA/OCFB
Timer
CCP Sync Out
Special Event Trigger Out (A/D)
Input
CCPxTMRH/L

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3.0 REGISTER MAP
A summary of the registers associated with the CCP modules (MCCP and SCCP) is shown in Tab le 3 -1 . This represents the superset
MCCP module; registers and individual bits that are not implemented in the SCCP module are noted.
Table 3-1: MCCP/SCCP Module Register Map
Register
Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
CCPxCON1L CCPON — CCPSIDL CCPSLP TMRSYNC CLKSEL[2:0] TMRPS[1:0] T32 CCSEL MOD[3:0] 0000
CCPxCON1H OPSSRC RTRGEN —— OPS[3:0] TRIGEN ONESHOT ALTSYNC SYNC[4:0] 0000
CCPxCON2L PWMRSEN ASDGM — SSDG — — — —ASDG[7:0]0000
CCPxCON2H OENSYNC — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN ICGSM[1:0] — AUXOUT[1:0] ICS[2:0] 0100
CCPxCON3L — — — — — — — — — —DT[5:0]0000
CCPxCON3H OETRIG OSCNT[2:0] —OUTM[2:0}—— POLACE POLBDF PSSACE[1:0] PSSBDF[1:0] 0000
CCPxSTATL — — — — — — — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000
CCPxTMRL CCPx Time Base Register, Low Word 0000
CCPxTMRH CCPx Time Base Register, High Word 0000
CCPxPRL CCPx Period Register, Low Word FFFF
CCPxPRH CCPx Period Register, High Word FFFF
CCPxRA CCPx Primary Compare Register 0000
CCPxRB CCPx Secondary Compare Register 0000
CCPxBUFL CCPx Capture Buffer Register, Low Word 0000
CCPxBUFH CCPx Capture Buffer Register, High Word 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-1: CCPxCON1L: Capture/Compare/PWMx Control 1 Low Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCPON — CCPSIDL CCPSLP TMRSYNC CLKSEL[2:0](1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMRPS[1:0] T32 CCSEL MOD[3:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CCPON: CCPx Module Enable
1= Module is enabled with operating mode specified by MOD[3:0]
0= Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 CCPSIDL: CCPx Stop in Idle Mode Bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12 CCPSLP: CCPx Sleep Mode Enable bit
1= Module continues to operate in Sleep modes
0= Module does not operate in Sleep modes
bit 11 TMRSYNC: Time Base Clock Synchronization bit
1= Module time base clock is synchronized to internal system clocks; timing restrictions apply
0= Module time base clock is not synchronized to internal system clocks
bit 10-8 CLKSEL[2:0]: CCPx Time Base Clock Select bits(1)
111 = Clock 7
110 = Clock 6
101 = Clock 5
100 = Clock 4
011 = Clock 3
010 = Clock 2
001 = Clock 1
000 = System Clock (TCY)
bit 7-6 TMRPS[1:0]: CCPx Time Base Prescale Select bits
11 = 1:64 Prescaler
10 = 1:16 Prescaler
01 = 1:4 Prescaler
00 = 1:1 Prescaler
bit 5 T32: 32-Bit Time Base Select bit
1= 32-bit time base for timer, single edge Output Compare or Input Capture function
0= 16-bit time base for timer, single edge Output Compare or Input Capture function
bit 4 CCSEL: Capture/Compare Mode Select bit
1= Input Capture mode
0= Output Compare/PWM or Timer mode (exact function selected by MOD[3:0] bits)
Note 1: Refer to the device data sheet for available clock sources for a specific device family.

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bit 3-0 MOD[3:0]: CCPx Mode Select bits
CCSEL = 1(Input Capture modes):
1xxx = Reserved
011x = Reserved
0101 = Capture every 16th rising edge
0100 = Capture every 4th rising edge
0011 = Capture every rising and falling edge
0010 = Capture every falling edge
0001 = Capture every rising edge
0000 = Capture every rising and falling edge (Edge Detect mode)
CCSEL = 0(Output Compare modes):
1111 = External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110 = Reserved
110x = Reserved
10xx = Reserved
0111 = Variable Frequency Pulse mode
0110 = Center-Aligned Pulse Compare mode, buffered
0101 = Dual Edge Compare mode, buffered
0100 = Dual Edge Compare mode
0011 = 16-Bit/32-Bit Single Edge mode: Toggles output on compare match
0010 = 16-Bit/32-Bit Single Edge mode: Drives output low on compare match
0001 = 16-Bit/32-Bit Single Edge mode: Drives output high on compare match
0000 = 16-Bit/32-Bit Timer mode: Output functions are disabled
Register 3-1: CCPxCON1L: Capture/Compare/PWMx Control 1 Low Register (Continued)
Note 1: Refer to the device data sheet for available clock sources for a specific device family.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-2: CCPxCON1H: Capture/Compare/PWMx Control 1 High Register
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
OPSSRC(1)RTRGEN(2)—— OPS[3:0](3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRIGEN ONESHOT ALTSYNC SYNC[4:0](3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OPSSRC: Output Postscaler Source Select bit(1)
1= Output postscaler scales Special Event Trigger output events
0= Output postscaler scales timer interrupt events
bit 14 RTRGEN: Retrigger Enable bit(2)
1= Time base can be retriggered when CCPTRIG = 1
0= Time base may not be retriggered when CCPTRIG = 1
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 OPS[3:0]: CCPx Interrupt Output Postscale Select bits(3)
1111 = Interrupt every 16th time base period match
1110 = Interrupt every 15th time base period match
...
0100 = Interrupt every 5th time base period match
0011 = Interrupt every 4th time base period match or 4th Input Capture event
0010 = Interrupt every 3rd time base period match or 3rd Input Capture event
0001 = Interrupt every 2nd time base period match or 2nd Input Capture event
0000 = Interrupt after each time base period match or Input Capture event
bit 7 TRIGEN: CCPx Triggered Enable bit
1= Triggered operation of timer is enabled
0= Triggered operation of timer is disabled
bit 6 ONESHOT: One-Shot Mode Enable bit
1= One-Shot Triggered mode is enabled; trigger duration is set by OSCNT[2:0]
0= One-Shot Triggered mode is disabled
bit 5 ALTSYNC: CCPx Alternate Synchronization Output Signal Select bit
1= An alternate signal is used as the module synchronization output signal
0= The module synchronization output signal is the Time Base Reset/rollover event
bit 4-0 SYNC[4:0]: CCPx Synchronization Source Select bits(4)
11111 = Timer is in the Free-Running mode and rolls over at FFFFh (period register is ignored)
11110 = Timer is synchronized to Source #30
...
00001 = Time base is synchronized to Source #1
00000 = No external synchronization; timer rolls over at FFFFh or matches with period register
Note 1: Control bit has no function in Input Capture modes.
2: Control bit has no function when TRIGEN = 0.
3: Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.
4: Refer to the device data sheet for Sync sources for a specific device family.

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Register 3-3: CCPxCON2L: Capture/Compare/PWMx Control 2 Low Register
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
PWMRSEN ASDGM — SSDG — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ASDG[7:0](1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWMRSEN: CCPx PWM Restart Enable bit
1= ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input
has ended
0= ASEVT bit must be cleared in software to resume PWM activity on output pins
bit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit
1= Waits until next Time Base Reset or rollover for shutdown to occur
0= Shutdown event occurs immediately
bit 13 Unimplemented: Read as ‘0’
bit 12 SSDG: CCPx Software Shutdown/Gate Control bit
1= Manually forces auto-shutdown, timer clock gate or Input Capture signal gate event (setting of
ASDGM bit still applies)
0= Normal module operation
bit 11-8 Unimplemented: Read as ‘0’
bit 7-0 ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits(1)
1= Auto-Shutdown/Gating Source n is enabled
0= Auto-Shutdown/Gating Source n is disabled
Note 1: Refer to the device data sheet for the specific gating sources implemented for a device family.

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Capture/Compare/PWM/Timer (MCCP and SCCP)
Register 3-4: CCPxCON2H: Capture/Compare/PWMx Control 2 High Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
OENSYNC —OCFEN
(1)OCEEN(1)OCDEN(1)OCCEN(1)OCBEN(1)OCAEN
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ICGSM[1:0] — AUXOUT[1:0](2)ICS[2:0](3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OENSYNC: Output Enable Synchronization bit
1= Update by output enable bits occurs on the next Time Base Reset or rollover
0= Update by output enable bits occurs immediately
bit 14 Unimplemented: Read as ‘0’
bit 13-8 OC[F:A]EN: Output Enable/Steering Control bits(1)
1= OCx pin is controlled by the CCPx module and produces an Output Compare or PWM signal
0= OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
bit 7-6 ICGSM[1:0]: Input Capture Gating Source Mode Control bits
11 = Reserved
10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low
level will disable future capture events.
bit 5 Unimplemented: Read as ‘0’
bit 4-3 AUXOUT[1:0]: Auxiliary Output Signal on Event Selection bits(2)
11 = Input Capture or Output Compare event; no signal in Timer mode
10 = Signal output depends on module operating mode (see Tabl e 8 -2)
01 = Time base rollover event (all modes)
00 = Disabled
bit 2-0 ICS[2:0]: Input Capture Source Select bits(3)
111 = Capture Source 8
110 = Capture Source 7
101 = Capture Source 6
100 = Capture Source 5
011 = Capture Source 4
010 = Capture Source 3
001 = Capture Source 2
000 = Capture Source 1 (ICx pin)
Note 1: OCFEN through OCBEN (bits[13:9]) are implemented in MCCP modules only.
2: Auxiliary output is not implemented in all devices. Refer to the device data sheet for details.
3: Refer to the device data sheet for specific Input Capture sources.

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Register 3-5: CCPxCON3L: Capture Compare PWMx Control 3 Low Register(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——DT[5:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 DT[5:0]: PWM Dead-Time Select bits
111111 = Inserts 63 dead-time delay periods between complementary output signals
111110 = Inserts 62 dead-time delay periods between complementary output signals
...
000010 = Inserts 2 dead-time delay periods between complementary output signals
000001 = Inserts 1 dead-time delay period between complementary output signals
000000 = Dead-time logic is disabled
Note 1: This register is implemented in MCCP modules only.