Motorola MVME167-32 User manual

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MVME167
Single Board Computer
User’s Manual
Character User Interface:

vii
Contents
CHAPTER 1 GENERAL INFORMATION
Introduction................................................................................................................1-1
Model Designations ...................................................................................................1-1
Features......................................................................................................................1-2
Specifications.............................................................................................................1-3
Cooling Requirements ........................................................................................1-3
FCC Compliance.................................................................................................1-4
General Description ...................................................................................................1-5
Equipment Required ..................................................................................................1-6
Related Documentation..............................................................................................1-7
Support Information...................................................................................................1-8
Manual Terminology..................................................................................................1-9
CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION
Introduction................................................................................................................2-1
Unpacking Instructions ..............................................................................................2-1
Hardware Preparation ................................................................................................2-1
General Purpose Readable Jumpers on Header J1..............................................2-2
System Controller Header J2..............................................................................2-2
Serial Port 4 Clock Configuration Select Headers J6 and J7..............................2-4
SRAM Backup Power Source Select Header J8.................................................2-5
Installation Instructions..............................................................................................2-6
MVME167 Module Installation..........................................................................2-6
System Considerations........................................................................................2-7
CHAPTER 3 OPERATING INSTRUCTIONS
Introduction................................................................................................................3-1
Controls and Indicators..............................................................................................3-1
ABORT Switch S1..............................................................................................3-1
RESET Switch S2...............................................................................................3-1
Front Panel Indicators (DS1 - DS4)....................................................................3-2
Memory Maps............................................................................................................3-3
Local Bus Memory Map.....................................................................................3-3

viii
Normal Address Range ...............................................................................3-3
Detailed I/O Memory Maps............................................................................3-6
BBRAM,TOD Clock Memory Map .............................................................3-26
Interrupt Acknowledge Map .........................................................................3-28
VMEbus Memory Map ........................................................................................3-29
VMEbus Accesses to the Local Bus .............................................................3-29
VMEbus Short I/O Memory Map .................................................................3-29
Software Initialization .................................................................................................3-30
Multi-MPU Programming Considerations...........................................................3-30
Local Reset Operation..........................................................................................3-30
CHAPTER 4 FUNCTIONAL DESCRIPTION
Introduction ...................................................................................................................4-1
MVME167 Functional Description...............................................................................4-1
Data Bus Structure..................................................................................................4-1
MC68040 MPU......................................................................................................4-2
EPROM..................................................................................................................4-2
SRAM.....................................................................................................................4-2
Onboard DRAM.....................................................................................................4-3
Battery Backed Up RAM and Clock......................................................................4-4
VMEbus Interface ..................................................................................................4-4
I/O Interfaces..........................................................................................................4-5
Serial Port Interface.........................................................................................4-5
Parallel Port Interface......................................................................................4-6
Ethernet Interface............................................................................................4-6
SCSI Interface.................................................................................................4-7
SCSI Termination............................................................................................4-7
Local Resources .....................................................................................................4-7
Programmable Tick Timers.............................................................................4-7
Watchdog Timer..............................................................................................4-8
Software-Programmable Hardware Interrupts................................................4-8
Local Bus Timeout..........................................................................................4-8
Timing Performance...............................................................................................4-8
Local Bus to DRAM Cycle Times..................................................................4-8
ROM Cycle Times ..........................................................................................4-9
SCSI Transfers ................................................................................................4-9
LAN DMA Transfers......................................................................................4-9
Remote Status and Control...................................................................................4-10

ix
APPENDIX A EIA-232-D INTERCONNECTIONS
Introduction.................................................................................................................. A-1
Levels of Implementation ............................................................................................ A-3
Signal Adaptations................................................................................................ A-3
Sample Configurations ......................................................................................... A-4
Proper Grounding ................................................................................................. A-6

x

xi
List of Figures
Figure 2-1. MVME167 Switches, Headers, Connectors, Fuses, and LEDs ..............2-3
Figure 4-1. MVME167 Main Module Block Diagram............................................4-11
Figure 4-2. Parity DRAM Mezzanine Module Block Diagram...............................4-12
Figure 4-3. ECC DRAM Mezzanine Module Block Diagram ................................4-13
Figure A-1. Middle-of-the-Road EIA-232-D Configuration....................................A-4
Figure A-2. Minimum EIA-232-D Connection ........................................................A-5

xii

xiii
List of Tables
Table 1-1. MVME167 Model Designations...............................................................1-1
Table 1-2. MVME167 Specifications ........................................................................1-4
Table 3-1. Local Bus Memory Map...........................................................................3-4
Table 3-2. Local I/O Devices Memory Map..............................................................3-5
Table 3-3. VMEchip2 Memory Map (Sheet 1 of 3)...................................................3-8
Table 3-4. PCCchip2 Memory Map.........................................................................3-14
Table 3-5. Printer Memory Map ..............................................................................3-16
Table 3-6. MEMC040 Internal Register Memory Map ...........................................3-17
Table 3-7. MCECC Internal Register Memory Map................................................3-17
Table 3-8. Cirrus Logic CD2401 Serial Port Memory Map ....................................3-19
Table 3-9. 82596CA Ethernet LAN Memory Map..................................................3-23
Table 3-10. 53C710 SCSI Memory Map .................................................................3-24
Table 3-11. MK48T08 BBRAM,TOD Clock Memory Map ...................................3-25
Table 3-12. BBRAM Configuration Area Memory Map.........................................3-25
Table 3-13. TOD Clock Memory Map.....................................................................3-26
Table A-1. EIA-232-D Interconnections...................................................................A-2

xiv

MVME167/D31-1
1
GENERAL INFORMATION
Introduction
This manual provides general information, preparation for use and installation
instructions, operating instructions, and functional description for the MVME167
series of Single Board Computers (referred to as the MVME167 throughout this
manual).
Model Designations
The MVME167 is available in several models, which are listed in Table 1-1.
MVME167 Model Designations on page 1-1.
Table 1-1. MVME167 Model Designations
Model Number Speed Major Differences
MVME167-001B (was MVME167-01 or -001A) 25 MHz 4MB Onboard Parity DRAM
MVME167-002B (was MVME167-02 or -002A) 25 MHz 8MB Onboard Parity DRAM
MVME167-003B (was MVME167-03 or -003A) 25 MHz 16MB Onboard Parity DRAM
MVME167-004B (was MVME167-04 or -004A) 25 MHz 32MB Onboard Parity DRAM
MVME167-031B (was MVME167-31 or -031A) 33 MHz 4MB Onboard ECC DRAM
MVME167-032B (was MVME167-32 or -032A) 33 MHz 8MB Onboard ECC DRAM
MVME167-033B (was MVME167-33 or -033A) 33 MHz 16MB Onboard ECC DRAM
MVME167-034B (was MVME167-34 or -034A) 33 MHz 32MB Onboard ECC DRAM
MVME167-035B (was MVME167-035A) 33 MHz 64MB Onboard ECC DRAM
MVME167-036B (was MVME167-036A) 33 MHz 128MB Onboard ECC DRAM

General Information
1-2 MVME167 Single Board Computer User’s Manual
1
Features
Features of the MVME167 are listed below.
❏MC68040 Microprocessor at 25 MHz (-00X models), or 33 MHz
(-03X models)
❏4/8/16/32/64MB of 32-bit DRAM with parity protection
or 4/8/16/32/64/128/256MB of DRAM with ECC protection
❏Four 44-pin PLCC ROM sockets (organized as two banks of 32 bits)
❏128KB SRAM (with optional battery backup)
❏Status LEDs for FAIL, STAT, RUN, SCON, LAN, +12V (LAN power), SCSI,
and VME.
❏8K by 8 RAM and time of day clock with battery backup
❏RESET and ABORT switches
❏Four 32-bit tick timers for periodic interrupts
❏Watchdog timer
❏Eight software interrupts
❏I/O
– SCSI Bus interface with DMA
– Four serial ports with EIA-232-D buffers with DMA
– Centronics printer port
– Ethernet transceiver interface with DMA
❏VMEbus interface
– VMEbus system controller functions
– VMEbus interface to local bus (A24/A32,
D8/D16/D32 (D8/D16/D32/D64BLT) (BLT = Block Transfer)
– Local bus to VMEbus interface (A16/A24/A32, D8/D16/D32)
– VMEbus interrupter
– VMEbus interrupt handler
– Global CSR for interprocessor communications
– DMA for fast local memory - VMEbus transfers (A16/A24/A32,
D16/D32 (D16/D32/D64BLT)

Specifications
MVME167/D3 1-3
1
Specifications
General specifications for the MVME167 are listed in Table 1-2. MVME167
Specifications on page 1-4.
The following sections detail cooling requirements and FCC compliance.
Cooling Requirements
The Motorola MVME167 VMEmodule is specified, designed, and tested to operate
reliably with an incoming air temperature range from 0° to 55° C
(32° to 131° F) with forced air cooling at a velocity typically achievable by using a 100
CFM axial fan. Temperature qualification is performed in a standard Motorola
VMEsystem chassis. Twenty-five watt load boards are inserted in two card slots, one
on each side, adjacent to the board under test, to simulate a high power density system
configuration. An assembly of three axial fans, rated at 100 CFM per fan, is placed
directly under the VME card cage. The incomingair temperature is measuredbetween
the fan assembly and the card cage, where the incoming airstream first encounters the
module under test. Test software is executed as the module is subjected to ambient
temperature variations. Case temperatures of critical, high power density integrated
circuits are monitored to ensure component vendors specifications are not exceeded.
While the exact amount of airflow required for cooling depends on the ambient air
temperature and the type, number, and location of boards and other heat sources,
adequate cooling can usually be achieved with 10CFM and 490 LFM flowing over the
module. Less airflow is required to cool the module in environments having lower
maximum ambients. Under more favorable thermal conditions, it may be possible to
operate the module reliably at higher than 55° C with increased airflow. It is important
to note that there are several factors, in addition to the rated CFM of the air mover,
which determine the actual volume and speed of air flowing over a module.

General Information
1-4 MVME167 Single Board Computer User’s Manual
1
FCC Compliance
The MVME167 was tested in an FCC-compliant chassis, and meets the requirements
for Class A equipment. FCC compliance was achieved under the following conditions:
1. Shielded cables on all external I/O ports.
2. Cable shields connected to earth ground via metal shell connectors bonded to a
conductive module front panel.
3. Conductive chassis rails connected to earth ground. This provides the path for
connecting shields to earth ground.
4. Front panel screws properly tightened.
Table 1-2. MVME167 Specifications
Characteristics Specifications
Power requirements
(with all four EPROM
sockets populated and
excluding external
LAN transceiver)
+5 Vdc (± 5%), 3.5 A (typical), 4.5 A (max.)
(at 25 MHz, with 32MB parity DRAM);
5.0 A (typical), 6.5 A (max.)
(at 33 MHz, with 128MB ECC DRAM)
+12 Vdc (± 5%), 100 mA (max.)
(1.0 A (max.) with offboard LAN
transceiver)
-12 Vdc (± 5%), 100 mA (max.)
Operating temperature (refer to
Cooling Requirements section) 0° to 55° C at point of entry of forced air (approximately 490 LFM)
Storage temperature -40° to +85° C
Relative humidity 5% to 90% (non-condensing)
Physical dimensions
PC board with mezzanine module
only Height
Depth
Thickness
PC boards with connectors and front
panelHeight
Depth
Thickness
Double-high VMEboard
9.187 inches (233.35 mm)
6.299 inches (160.00 mm)
0.662 inches (16.77 mm)
10.309 inches (261.85 mm)
7.4 inches (188 mm)
0.80 inches (20.32 mm)

General Description
MVME167/D3 1-5
1
For minimum RF emissions, it is essential that the conditions above be implemented;
failure to do so could compromise the FCC compliance of the equipment containing
the module.
General Description
TheMVME167isadouble-highVMEmodulebased onthe MC68040microprocessor.
The MVME167 has 4/8/16/32/64 MB of parity-protected DRAM or
4/8/16/32/64/128/256 MB of ECC-protected DRAM, 8KB of static RAM and time of
day clock (with battery backup), Ethernet transceiver interface, four serial ports with
EIA-232-D interface, four tick timers, watchdog timer, four ROM sockets, SCSI bus
interface with DMA, Centronics printer port, A16/A24/A32/D8/D16/D32/D64
VMEbus master/slave interface, 128KB of static RAM (with optional battery backup),
and VMEbus system controller.
The I/O on the MVME167 is connected to the VMEbus P2 connector. The main board
is connected through a P2 transition board and cables to the transition boards. The
MVME167 supports the transition boards MVME712-12, MVME712-13,
MVME712M, MVME712A, MVME712AM, and MVME712B (referred to in this
manual as MVME712X, unless separately specified). The MVME712X transition
boards provide configuration headers and provide industry standard connectors for the
I/O devices.
The VMEbus interface is provided by an ASIC called the VMEchip2. The VMEchip2
includestwoticktimers, a watchdogtimer,programmablemapdecoders forthemaster
and slave interfaces, and a VMEbus to/from local bus DMA controller, a VMEbus
to/from local bus non-DMA programmed access interface, a VMEbus interrupter, a
VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers can be D8, D16, or D32. VMEchip2 DMA transfers to
the VMEbus, however, can be D16, D32, D16/BLT, D32/BLT, or D64/MBLT.
The PCCchip2 ASIC provides two tick timers and the interface to the LAN chip, SCSI
chip, serial port chip, printer port, and BBRAM.
The MEMC040memory controller ASIC provides the programmable interface forthe
parity-protected DRAM mezzanine board.
The MCECC memory controller ASIC provides the programmable interface for the
ECC-protected DRAM mezzanine board.

General Information
1-6 MVME167 Single Board Computer User’s Manual
1
Equipment Required
The following equipment is required to make acomplete system using the MVME167:
❏Terminal
❏Disk drives and controllers
❏Transition module MVME712-12, MVME712-13, MVME712M, MVME712A,
MVME712AM, or MVME712B, and connecting cables and P2 adapter
❏Operating system
The MVME167Bug debug monitor firmware (167Bug) is provided in two of the four
EPROM sockets on the MVME167 main module. It provides over 50 debug,
up/downline load, and disk bootstrap load commands, as well as a full set of onboard
diagnostics and a one-line assembler/disassembler. 167Bug includes a user interface
which accepts commands from the system console terminal. 167Bug can also operate
in a System Mode, which includes choices from a service menu. Refer to the
MVME167Bug Debugging Package User’s Manual and the Debugging Package for
Motorola 68K CISC CPUs User’s Manual for details.
The MVME712X series of transition modules provide the interface between the
MVME167 module and peripheral devices. They connect the MVME167 to
EIA-232-D serial devices, Centronics-compatible parallel devices, SCSI devices, and
Ethernet devices. The MVME712X series work with cables and a P2 adapter.
SoftwareavailablefortheMVME167includes SYSTEM V/68andreal-time operating
systems,programming languages, and othertools and applications. Contact your local
Motorola sales office for more details.

Related Documentation
MVME167/D3 1-7
1
Related Documentation
The following publications are applicable to the MVME167 and may provide
additional helpful information. If not shipped with this product, they may be purchased
by contacting your local Motorola sales office. Non-Motorola documents may be
purchased from the sources listed.
Note Although not shown in the above list, each Motorola Computer
Group manual publication number is suffixed with characters
which represent the revision level of the document, such as
"/D2" (the second revision of a manual); a supplement bears the
same number as a manual but has a suffix such as "/D2A1" (the
first supplement to the second edition of the manual).
Document Title Motorola Publication
Number
MVME167 Single Board Computer Support Information
(Refer to Support Information on page 1-8) SIMVME167
MVME167Bug Debugging Package User’s Manual MVME167BUG
Debugging Package for Motorola 68K CISC CPUs User’s Manual 68KBUG
Single Board Computers SCSI Software User’s Manual SBCSCSI
MVME166/MVME167/MVME187 Single Board Computers
Programmer’s Reference Guide MVME187PG
MVME712M Transition Module and P2 Adapter Board User’s
Manual MVME712M
MVME712-12, MVME712-13, MVME712A, MVME712AM, and
MVME712B Transition Module and LCP2 Adapter Board User’s
Manual
MVME712A
M68040 Microprocessor User’s Manual M68040UM

General Information
1-8 MVME167 Single Board Computer User’s Manual
1
The following publications are available from the sources indicated.
Versatile Backplane Bus: VMEbus, ANSI/IEEE Std 1014-1987, The Institute of
Electrical and Electronics Engineers, Inc., 345 East47th Street, New York, NY 10017
(VMEbus Specification). This is also available as Microprocessor system bus for 1 to
4 byte data, IEC 821 BUS, Bureau Central de la Commission Electrotechnique
Internationale; 3, rue de Varembé, Geneva, Switzerland.
ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131-198X,
Revision 10c; Global Engineering Documents, P.O. Box 19539, Irvine, CA 92714.
CL-CD2400/2401 Four-Channel Multi-Protocol Communications Controller Data
Sheet, order number 542400-003; Cirrus Logic, Inc., 3100 West Warren Ave.,
Fremont, CA 94538.
82596CA Local Area Network Coprocessor Data Sheet, order number 290218; and
82596 User’s Manual, order number 296853; Intel Corporation, Literature Sales, P.O.
Box 58130, Santa Clara, CA 95052-8130.
NCR 53C710 SCSI I/O Processor Data Manual, order number NCR53C710DM; and
NCR 53C710 SCSI I/O Processor Programmer’s Guide, order number
NCR53C710PG; NCR Corporation, Microelectronics Products Division, Colorado
Springs, CO.
MK48T08(B) Timekeeper TM and 8Kx8 Zeropower TM RAM data sheet in Static
RAMs Databook, order number DBSRAM71; SGS-THOMPSON Microelectronics
Group; North & South American Marketing Headquarters, 1000 East Bell Road,
Phoenix, AZ 85022-2699.
Support Information
The SIMVME167 manual contains the connector interconnect signal information,
parts lists, and the schematics for the MVME167.
This manual may be obtained free of charge by contacting your local Motorola sales
office.

Manual Terminology
MVME167/D3 1-9
1
Manual Terminology
Throughout this manual, a convention is used which precedes data and address
parameters by a character identifying the numeric format as follows:
Unless otherwise specified, all address references are in hexadecimal.
An asterisk (*) following the signal name for signals which are level significant
denotes that the signal is true or valid when the signal is low.
An asterisk (*) following the signal name for signals which are edge significant
denotes that the actions initiated by that signal occur on high to low transition.
In this manual, assertion and negation are used to specify forcing a signal to a
particular state. In particular, assertion and assert referto a signal that is active or true;
negation an negate indicate a signal that is inactive or false. These terms are used
independently of the voltage level (high or low) that they represent.
Data and address sizes are defined as follows:
❏A byte is eight bits, numbered 0 through 7, with bit 0 being the least significant.
❏A word is 16 bits, numbered 0 through 15, with bit 0 being the least significant.
❏A longword is 32 bits, numbered 0 through 31, with bit 0 being the least
significant.
$ dollar specifies a hexadecimal character
% percent specifies a binary number
& ampersand specifies a decimal number